fpga: tools: Fix -quiet in modify_bdtcl

Original-commit: 342221055021cbb63387362e26184d24d61746da
2024-03-13 21:30:52 -05:00
parent 2e0177484c
commit a8937b3500
1 changed files with 1 additions and 1 deletions
@@ -130,7 +130,7 @@ if { [string compare $cmd "create"] == 0 } {
            puts "INFO: BD TCL source updated: $src_dir/$src_rootname.tcl"
            # Export HDL source files into a seperate TCL file
            puts "INFO: Generating hdl_sources.tcl file from project..."
-            set hdlSources -quiet [get_files -filter {FILE_TYPE == VHDL || FILE_TYPE == Verilog || FILE_TYPE == SystemVerilog}]
+            set hdlSources [get_files -quiet -filter {FILE_TYPE == VHDL || FILE_TYPE == Verilog || FILE_TYPE == SystemVerilog}]
            if {[llength $hdlSources] == 0} {
                puts "INFO: No HDL sources found in project"
            } else {