From a8937b3500a58d864e9d737d7d01bd3390869e5a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Max=20K=C3=B6hler?= <max.koehler@ni.com>
Date: Wed, 13 Mar 2024 10:22:08 +0100
Subject: [PATCH] fpga: tools: Fix -quiet in modify_bdtcl

Original-commit: 342221055021cbb63387362e26184d24d61746da
---
 tools/scripts/viv_ip_utils.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/scripts/viv_ip_utils.tcl b/tools/scripts/viv_ip_utils.tcl
index 1ebee8d..e406076 100644
--- a/tools/scripts/viv_ip_utils.tcl
+++ b/tools/scripts/viv_ip_utils.tcl
@@ -130,7 +130,7 @@ if { [string compare $cmd "create"] == 0 } {
             puts "INFO: BD TCL source updated: $src_dir/$src_rootname.tcl"
             # Export HDL source files into a seperate TCL file
             puts "INFO: Generating hdl_sources.tcl file from project..."
-            set hdlSources -quiet [get_files -filter {FILE_TYPE == VHDL || FILE_TYPE == Verilog || FILE_TYPE == SystemVerilog}]
+            set hdlSources [get_files -quiet -filter {FILE_TYPE == VHDL || FILE_TYPE == Verilog || FILE_TYPE == SystemVerilog}]
             if {[llength $hdlSources] == 0} {
                 puts "INFO: No HDL sources found in project"
             } else {