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fpga: x400: zbx: Add support for XO3 CPLD variant.

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The main changes included are:
- Variant-dependent pin-out instantiation.
- Update clocking scheme in top level file
  to include XO3 PLL
- Add ability to shift outgoing data for
  the GPIO communication interface with
  the X410 FPGA.
- Include project files required to build
  the XO3 variant of the ZBX CPLD.
- Add build flow for Lattice Diamond designs.
- Add ability to build XO3 variant of ZBX CPLD.


Original-commit: 2c7813acb21383f302353a1b6cf57f0946fa0b6b
This commit is contained in:
Javier Valenzuela
2022-06-28 16:33:05 -05:00
committed by Wade Fife
parent 27aae37722
commit a6fc53b4e6
23 changed files with 1888 additions and 84 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/x400/dboards/zbx/cpld/lattice/build.tcl
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#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
#
# This file contains the sequence of steps required to
# build and generate outputs for the ZBX CPLD, XO3 variant.
# It is intended to be use as a parameter for
# pnmainc (Diamond TCL console).
# pnmainc.exe build.tcl > <LOG_FILE_NAME>
prj_project open "zbx_top_cpld.ldf"
prj_run Synthesis -impl impl1
prj_run Translate -impl impl1
prj_run Map -impl impl1
prj_run PAR -impl impl1
prj_run PAR -impl impl1 -task PARTrace
prj_run Export -impl impl1 -task Bitgen
prj_run Export -impl impl1 -task Jedecgen
prj_run Export -impl impl1 -task Jedec4Xo3l
prj_project close
top/x400/dboards/zbx/cpld/lattice/ip/pll/pll.ipx
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<?xml version="1.0" encoding="UTF-8"?>
<DiamondModule name="pll" module="pll" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2022 03 03 14:15:50.923" version="5.8" type="Module" synthesis="synplify" source_format="Verilog HDL">
<Package>
<File name="pll.lpc" type="lpc" modified="2022 03 03 14:15:48.492"/>
<File name="pll.v" type="top_level_verilog" modified="2022 03 03 14:15:48.597"/>
<File name="pll_tmpl.v" type="template_verilog" modified="2022 03 03 14:15:48.597"/>
</Package>
</DiamondModule>
top/x400/dboards/zbx/cpld/lattice/ip/pll/pll.lpc
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[Device]
Family=machxo3lf
PartType=LCMXO3LF-9400C
PartName=LCMXO3LF-9400C-6BG256I
SpeedGrade=6
Package=CABGA256
OperatingCondition=IND
Status=S
[IP]
VendorName=Lattice Semiconductor Corporation
CoreType=LPM
CoreStatus=Demo
CoreName=PLL
CoreRevision=5.8
ModuleName=pll
SourceFormat=Verilog HDL
ParameterFileVersion=1.0
Date=03/03/2022
Time=14:15:48
[Parameters]
Verilog=1
VHDL=0
EDIF=1
Destination=Synplicity
Expression=None
Order=None
IO=0
mode=Frequency
CLKI=64
CLKI_DIV=1
BW=6.139
VCO=512.000
fb_mode=CLKOP
CLKFB_DIV=1
FRACN_ENABLE=0
FRACN_DIV=0
DynamicPhase=STATIC
ClkEnable=1
Standby=0
Enable_sel=0
PLLRst=0
PLLMRst=0
ClkOS2Rst=0
ClkOS3Rst=0
LockSig=1
LockStk=0
WBProt=0
OPBypass=0
OPUseDiv=0
CLKOP_DIV=8
FREQ_PIN_CLKOP=64
OP_Tol=0.0
CLKOP_AFREQ=64.000000
CLKOP_PHASEADJ=0
CLKOP_TRIM_POL=Rising
CLKOP_TRIM_DELAY=0
EnCLKOS=1
OSBypass=0
OSUseDiv=0
CLKOS_DIV=8
FREQ_PIN_CLKOS=64
OS_Tol=0.0
CLKOS_AFREQ=64.000000
CLKOS_PHASEADJ=225
CLKOS_TRIM_POL=Rising
CLKOS_TRIM_DELAY=0
EnCLKOS2=0
OS2Bypass=0
OS2UseDiv=0
CLKOS2_DIV=1
FREQ_PIN_CLKOS2=64
OS2_Tol=0.0
CLKOS2_AFREQ=64.000000
CLKOS2_PHASEADJ=225
EnCLKOS3=0
OS3Bypass=0
OS3UseDiv=0
CLKOS3_DIV=1
FREQ_PIN_CLKOS3=100
OS3_Tol=0.0
CLKOS3_AFREQ=
CLKOS3_PHASEADJ=0
[Command]
cmd_line= -w -n pll -lang verilog -synth synplify -arch xo3c00f -type pll -fin 64 -fclkop 64 -fclkop_tol 0.0 -fclkos 64 -fclkos_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 225 -trims_r -phase_cntl STATIC -enable_ports -fb_mode 1 -lock
top/x400/dboards/zbx/cpld/lattice/ip/pll/pll.v
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/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.0.240.2 */
/* Module Version: 5.7 */
/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll -lang verilog -synth synplify -arch xo3c00f -type pll -fin 64 -fclkop 64 -fclkop_tol 0.0 -fclkos 64 -fclkos_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 225 -trims_r -phase_cntl STATIC -enable_ports -fb_mode 1 -lock */
/* Thu Mar 03 14:15:48 2022 */
`timescale 1 ns / 1 ps
module pll (CLKI, ENCLKOP, ENCLKOS, CLKOP, CLKOS, LOCK)/* synthesis NGD_DRC_MASK=1 */;
input wire CLKI;
input wire ENCLKOP;
input wire ENCLKOS;
output wire CLKOP;
output wire CLKOS;
output wire LOCK;
wire CLKOS_t;
wire CLKOP_t;
wire scuba_vlo;
VLO scuba_vlo_inst (.Z(scuba_vlo));
defparam PLLInst_0.DDRST_ENA = "DISABLED" ;
defparam PLLInst_0.DCRST_ENA = "DISABLED" ;
defparam PLLInst_0.MRST_ENA = "DISABLED" ;
defparam PLLInst_0.PLLRST_ENA = "DISABLED" ;
defparam PLLInst_0.INTFB_WAKE = "DISABLED" ;
defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ;
defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ;
defparam PLLInst_0.PLL_USE_WB = "DISABLED" ;
defparam PLLInst_0.CLKOS3_FPHASE = 0 ;
defparam PLLInst_0.CLKOS3_CPHASE = 0 ;
defparam PLLInst_0.CLKOS2_FPHASE = 0 ;
defparam PLLInst_0.CLKOS2_CPHASE = 0 ;
defparam PLLInst_0.CLKOS_FPHASE = 0 ;
defparam PLLInst_0.CLKOS_CPHASE = 12 ;
defparam PLLInst_0.CLKOP_FPHASE = 0 ;
defparam PLLInst_0.CLKOP_CPHASE = 7 ;
defparam PLLInst_0.PLL_LOCK_MODE = 0 ;
defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ;
defparam PLLInst_0.CLKOS_TRIM_POL = "RISING" ;
defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ;
defparam PLLInst_0.CLKOP_TRIM_POL = "RISING" ;
defparam PLLInst_0.FRACN_DIV = 0 ;
defparam PLLInst_0.FRACN_ENABLE = "DISABLED" ;
defparam PLLInst_0.OUTDIVIDER_MUXD2 = "DIVD" ;
defparam PLLInst_0.PREDIVIDER_MUXD1 = 0 ;
defparam PLLInst_0.VCO_BYPASS_D0 = "DISABLED" ;
defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ;
defparam PLLInst_0.OUTDIVIDER_MUXC2 = "DIVC" ;
defparam PLLInst_0.PREDIVIDER_MUXC1 = 0 ;
defparam PLLInst_0.VCO_BYPASS_C0 = "DISABLED" ;
defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ;
defparam PLLInst_0.OUTDIVIDER_MUXB2 = "DIVB" ;
defparam PLLInst_0.PREDIVIDER_MUXB1 = 0 ;
defparam PLLInst_0.VCO_BYPASS_B0 = "DISABLED" ;
defparam PLLInst_0.CLKOS_ENABLE = "DISABLED" ;
defparam PLLInst_0.OUTDIVIDER_MUXA2 = "DIVA" ;
defparam PLLInst_0.PREDIVIDER_MUXA1 = 0 ;
defparam PLLInst_0.VCO_BYPASS_A0 = "DISABLED" ;
defparam PLLInst_0.CLKOP_ENABLE = "DISABLED" ;
defparam PLLInst_0.CLKOS3_DIV = 1 ;
defparam PLLInst_0.CLKOS2_DIV = 1 ;
defparam PLLInst_0.CLKOS_DIV = 8 ;
defparam PLLInst_0.CLKOP_DIV = 8 ;
defparam PLLInst_0.CLKFB_DIV = 1 ;
defparam PLLInst_0.CLKI_DIV = 1 ;
defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ;
EHXPLLJ PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo),
.PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo),
.LOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo),
.RST(scuba_vlo), .RESETM(scuba_vlo), .RESETC(scuba_vlo), .RESETD(scuba_vlo),
.ENCLKOP(ENCLKOP), .ENCLKOS(ENCLKOS), .ENCLKOS2(scuba_vlo), .ENCLKOS3(scuba_vlo),
.PLLCLK(scuba_vlo), .PLLRST(scuba_vlo), .PLLSTB(scuba_vlo), .PLLWE(scuba_vlo),
.PLLADDR4(scuba_vlo), .PLLADDR3(scuba_vlo), .PLLADDR2(scuba_vlo),
.PLLADDR1(scuba_vlo), .PLLADDR0(scuba_vlo), .PLLDATI7(scuba_vlo),
.PLLDATI6(scuba_vlo), .PLLDATI5(scuba_vlo), .PLLDATI4(scuba_vlo),
.PLLDATI3(scuba_vlo), .PLLDATI2(scuba_vlo), .PLLDATI1(scuba_vlo),
.PLLDATI0(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(CLKOS_t), .CLKOS2(),
.CLKOS3(), .LOCK(LOCK), .INTLOCK(), .REFCLK(), .CLKINTFB(), .DPHSRC(),
.PLLACK(), .PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(),
.PLLDATO2(), .PLLDATO1(), .PLLDATO0())
/* synthesis FREQUENCY_PIN_CLKOS="64.000000" */
/* synthesis FREQUENCY_PIN_CLKOP="64.000000" */
/* synthesis FREQUENCY_PIN_CLKI="64.000000" */
/* synthesis ICP_CURRENT="9" */
/* synthesis LPF_RESISTOR="72" */;
assign CLKOS = CLKOS_t;
assign CLKOP = CLKOP_t;
// exemplar begin
// exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOS 64.000000
// exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 64.000000
// exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 64.000000
// exemplar attribute PLLInst_0 ICP_CURRENT 9
// exemplar attribute PLLInst_0 LPF_RESISTOR 72
// exemplar end
endmodule
top/x400/dboards/zbx/cpld/lattice/ip/pll/pll_tmpl.v
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/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.0.240.2 */
/* Module Version: 5.7 */
/* Thu Mar 03 14:15:48 2022 */
/* parameterized module instance */
pll __ (.CLKI( ), .ENCLKOP( ), .ENCLKOS( ), .CLKOP( ), .CLKOS( ),
.LOCK( ));
top/x400/dboards/zbx/cpld/lattice/zbx_top_cpld.ldf
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<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="zbx_top_cpld" device="LCMXO3LF-9400C-6BG256I" default_implementation="impl1">
<Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="zbx_cpld_strat">
<Options VERILOG_DIRECTIVES="VARIANT_XO3" def_top="zbx_top_cpld" top="zbx_top_cpld"/>
<Source name="../zbx_cpld_core.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../zbx_top_cpld.v" type="Verilog" type_short="Verilog">
<Options top_module="zbx_top_cpld"/>
</Source>
<Source name="../../../../../../lib/control/handshake.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/control/pulse_synchronizer.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/control/ram_2port.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/control/reset_sync.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/control/synchronizer.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/control/synchronizer_impl.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../cpld/reconfig_engine.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../ctrlport_byte_deserializer.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/rfnoc/utils/ctrlport_splitter.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/wb_spi/rtl/verilog/spi_clgen.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/wb_spi/rtl/verilog/spi_shift.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/wb_spi/rtl/verilog/spi_top.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../cpld/spi_slave.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../cpld/spi_slave_to_ctrlport_master.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/rfnoc/utils/ctrlport_window.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../register_endpoints/atr_controller.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../register_endpoints/basic_regs.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../register_endpoints/dsa_control.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../register_endpoints/led_control.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../register_endpoints/lo_control.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../register_endpoints/power_regs.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../register_endpoints/switch_control.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/rfnoc/utils/ctrlport_clk_cross.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/rfnoc/utils/ctrlport_combiner.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="ip/pll/pll.ipx" type="IPX_Module" type_short="IPX">
<Options/>
</Source>
<Source name="zbx_top_cpld.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
<Source name="../zbx_top_cpld_gpio.ldc" type="LSE Design Constraints File" type_short="LDC" excluded="TRUE">
<Options/>
</Source>
</Implementation>
<Strategy name="zbx_cpld_strat" file="zbx_top_cpld.sty"/>
</BaliProject>
top/x400/dboards/zbx/cpld/lattice/zbx_top_cpld.lpf
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#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# This file follows the Lattice Preference File style to describe
# timing constraints for a Lattice Diamond Synplify build flow.
#
##### GENERAL TIMING DISCLAIMER ########
# Multiple constraints within this file use constant numbers to describe their
# respective input and output delays. The values presented were generated by
# evaluating constraints described for the MAX10 variant of this CPLD.
# Additional considerations were used when a constraint could not be written
# in the same way for both variants(such as in additional delays present in
# the datapath or data being generated on falling edges). In such cases,
# additional comments describing the origin of the value used are provided.
# The original constraints used to compute the values used in this file are
# located at:
# ../quartus/zbx_top_cpld.qsf
######################################################################################
# Timing
######################################################################################
# base clocks
@define $prc_clock_period 15.625 ;
@define $ctrl_sclk_period $prc_clock_period * 3.0 ;
PERIOD PORT "CPLD_REFCLK" $prc_clock_period ;
PERIOD PORT "MB_CTRL_SCK" $ctrl_sclk_period ;
FREQUENCY NET "clk_int_osc" 66.500000 MHz ;
############# MB GPIO ##################
# OUTPUT PATH
# --------------------------------------------------------------------------------------
# P&R fails when using delay values from original design. To make it easier for
# timing to be met, this interface uses an adjusted version of the clock, shifted
# by 225 degrees. Unfortunately, the use of a shifted clock result in the analysis
# of this input path to be incorrect
# The following diagram represents the timing for the GPIO communication interface
# considering data generated on a shifted clock.
#
# *Launch Edge(according to Diamond)
# |
# | * Latch edge(according to Diamond)
# | |
# | | * Actual Latch Edge.
# | | |
# ref_clk __/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\
# Max Output Delay _____________XXXXXXXX__________________________________________
# Min Output Delay ________XXX____________________________________________________
# shifted clk ----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\____
# |
# |
# * Data gets generated by shifted clock
# A potential solution for this would be to use multi-cycle path constraints to
# shift the analysis to the actual latch edge. This is not supported in Diamond,
# as output delay constraints are incompatible with multi-cycle constraints.
#
# After contacting Lattice, it was determined that the best solution was to compensate
# the delay that would be inserted by a multi-cycle constraint in the output delay
# constraint(effectively analyzing the timing from the detected to the actual
# latch edge).
# An advantage of this implementation is the ability to consider the worst-case clock
# frequency for the different scenarios analyzed.
# Maximum path delay = 8.5 ns
# Minimum path delay = -2 ns
# To shift timing analysis to the correct edges, the timing windows is shifted by
# one clock cycle, which is performed by subtracting a prc_clock period from
# the original path delays.
@define $gpio_max_output_delay 8.5 - $prc_clock_period ;
@define $gpio_min_output_delay -2.0 - $prc_clock_period ;
# This analysis results in the following constraint.
CLOCK_TO_OUT PORT "MB_FPGA_GPIO*" OUTPUT_DELAY $gpio_max_output_delay ns
MIN $gpio_min_output_delay ns
CLKPORT "CPLD_REFCLK" ;
# INPUT PATH
# --------------------------------------------------------------------------------------
# This path uses prc_clk with no phase alterations.
# The input path for GPIO lanes is driven in the falling edge of the clock, and some correction
# is performed for this adjustment.
#
# *Launch Edge(according to Diamond)
# |
# | * Actual Launch Edge
# | |
# | | * Actual Latch Edge.
# | | |
# ref_clk __/-----------\___________/-----------\___________/-----------\___________/------
# Max Delay ______________XXXXX______________________________________________________________
# Min Delay ______________XXX________________________________________________________________
# Maximum path delay = 4.561
# Minimum path delay = 4.045
# To adjust the analysis to the correct launch edge, we increase the input delays by
# half a prc_clock period. The CLK_OFFSET option is not used as it only changes
# the analysis on the receiving flop.
@define $gpio_max_input_delay $prc_clock_period / 2.0 + 4.561 ;
@define $gpio_min_input_delay $prc_clock_period / 2.0 + 4.045 ;
# Invert value for hold constraint
@define $gpio_min_input_hold -1.0 * $gpio_min_input_delay ;
# The adjusted values are used in the input constraint.
INPUT_SETUP PORT "MB_FPGA_GPIO*" INPUT_DELAY $gpio_max_input_delay ns
HOLD $gpio_min_input_hold ns
CLKPORT "CPLD_REFCLK" ;
############# LO SYNC ##################
INPUT_SETUP PORT MB_SYNTH_SYNC INPUT_DELAY 6.747 HOLD -5.860 ns CLKPORT "CPLD_REFCLK" ;
DEFINE PORT GROUP "LO_SYNC"
"RX0_LO*_SYNC"
"RX1_LO*_SYNC"
"TX0_LO*_SYNC"
"TX1_LO*_SYNC" ;
CLOCK_TO_OUT GROUP LO_SYNC OUTPUT_DELAY 2.445 MIN 2.145 ns CLKPORT "CPLD_REFCLK" ;
#####################################################################
# Timing exceptions
#####################################################################
## synchronizers
BLOCK PATH FROM PORT "CTRL_REG_ARST" TO CELL "*synchronizer_false_path*value_0*" ;
#####################################################################
# Asynchronous IO
#####################################################################
# For general I/O that don't have tight timing constraints, we can constrain
# these paths by creating a generic flip-flop that will interface to the
# device.
# For asynchronous outputs
@define $generic_ext_flop_tsu 1 ;
@define $generic_ext_flop_th 0 ;
# # For asynchronous inputs
@define $generic_ext_flop_max_tco 1 ;
@define $generic_ext_flop_min_tco 1 ;
# REF CLK
#--------------------------------------------------------------------
DEFINE PORT GROUP "ASYNC_REFCLK_OUTPUTS"
"CH*_*X*_LED"
"RX*_DSA*_*[*]"
"TX*_DSA*[*]"
"*X*_SW*" ;
CLOCK_TO_OUT GROUP ASYNC_REFCLK_OUTPUTS OUTPUT_DELAY $generic_ext_flop_tsu ns
MIN $generic_ext_flop_th ns
CLKPORT "CPLD_REFCLK" ;
DEFINE PORT GROUP "ASYNC_REFCLK_INPUTS"
"CTRL_REG_ARST" ;
INPUT_SETUP GROUP ASYNC_REFCLK_INPUTS INPUT_DELAY $generic_ext_flop_max_tco ns
HOLD $generic_ext_flop_min_tco ns
CLKPORT "CPLD_REFCLK" ;
# INT OSC
#--------------------------------------------------------------------
DEFINE PORT GROUP "ASYNC_INTOSC_OUTPUTS"
"P*_ENABLE*" ;
CLOCK_TO_OUT GROUP ASYNC_INTOSC_OUTPUTS OUTPUT_DELAY $generic_ext_flop_tsu ns
MIN $generic_ext_flop_th ns
CLKNET "clk_int_osc" ;
DEFINE PORT GROUP "ASYNC_INTOSC_INPUTS"
"P7V_PG_*" ;
INPUT_SETUP GROUP ASYNC_INTOSC_INPUTS INPUT_DELAY $generic_ext_flop_max_tco ns
HOLD $generic_ext_flop_min_tco ns
CLKNET "clk_int_osc" ;
#####################################################################
# MB CPLD <-> DB CPLD CTRL SPI interface
#####################################################################
# The timing constants of the MB CPLD are defined in
# fpga/usrp3/top/x400/cpld/db_spi_shared_constants.sdc
@define $ctrl_spi_input_max_delay -2.014 ;
@define $ctrl_spi_input_min_delay -4.500 ;
DEFINE PORT GROUP "CTRL_SLAVE_INPUTS"
"MB_CTRL_MOSI"
"MB_CTRL_CS" ;
INPUT_SETUP GROUP CTRL_SLAVE_INPUTS INPUT_DELAY $ctrl_spi_input_max_delay ns
HOLD $ctrl_spi_input_min_delay ns
CLKPORT "MB_CTRL_SCK"
SS ;
@define $ctrl_spi_output_max_delay 17.254 ;
@define $ctrl_spi_output_min_delay -0.500 ;
DEFINE PORT GROUP "CTRL_SLAVE_OUTPUTS"
"MB_CTRL_MISO" ;
CLOCK_TO_OUT GROUP CTRL_SLAVE_OUTPUTS OUTPUT_DELAY $ctrl_spi_output_max_delay ns
MIN $ctrl_spi_output_min_delay ns
CLKPORT "MB_CTRL_SCK" ;
# Additionally, Lattice detects an unconstrained path from MB_CTRL_CS
# to clk_int_osc. Since MB_CTRL_CS is asynchronous to that clock net,
# we use the same constraint strategy as for other asynchronous
# inputs.
INPUT_SETUP PORT "MB_CTRL_CS" INPUT_DELAY $generic_ext_flop_max_tco ns
HOLD $generic_ext_flop_min_tco ns
CLKNET "clk_int_osc" ;
#####################################################################
# LO SPI interface
#####################################################################
PERIOD PORT "TX0_LO1_SCK" $prc_clock_period ;
PERIOD PORT "RX0_LO1_SCK" $prc_clock_period ;
PERIOD PORT "TX0_LO2_SCK" $prc_clock_period ;
PERIOD PORT "RX0_LO2_SCK" $prc_clock_period ;
PERIOD PORT "TX1_LO1_SCK" $prc_clock_period ;
PERIOD PORT "RX1_LO1_SCK" $prc_clock_period ;
PERIOD PORT "TX1_LO2_SCK" $prc_clock_period ;
PERIOD PORT "RX1_LO2_SCK" $prc_clock_period ;
DEFINE PORT GROUP "LO_SPI_CLKS"
"*X*_LO*_SCK" ;
DEFINE PORT GROUP "LO_SPI_TX0_LO1_OUTPUT_PORTS"
"RX_TX_LO_SDI"
"TX0_LO1_CSB" ;
DEFINE PORT GROUP "LO_SPI_TX0_LO2_OUTPUT_PORTS"
"RX_TX_LO_SDI"
"TX0_LO2_CSB" ;
DEFINE PORT GROUP "LO_SPI_TX1_LO1_OUTPUT_PORTS"
"RX_TX_LO_SDI"
"TX1_LO1_CSB" ;
DEFINE PORT GROUP "LO_SPI_TX1_LO2_OUTPUT_PORTS"
"RX_TX_LO_SDI"
"TX1_LO2_CSB" ;
DEFINE PORT GROUP "LO_SPI_RX0_LO1_OUTPUT_PORTS"
"RX_TX_LO_SDI"
"RX0_LO1_CSB" ;
DEFINE PORT GROUP "LO_SPI_RX0_LO2_OUTPUT_PORTS"
"RX_TX_LO_SDI"
"RX0_LO2_CSB" ;
DEFINE PORT GROUP "LO_SPI_RX1_LO1_OUTPUT_PORTS"
"RX_TX_LO_SDI"
"RX1_LO1_CSB" ;
DEFINE PORT GROUP "LO_SPI_RX1_LO2_OUTPUT_PORTS"
"RX_TX_LO_SDI"
"RX1_LO2_CSB" ;
DEFINE PORT GROUP "LO_SPI_INPUT_PORTS"
"*X*_LO*_MUXOUT" ;
# -- Multi-cycle path for SPI CS and SDI --
# ----------------------------------------
# edge # 1 2 3 4 5
# clk50 __/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/--
# sclk __/-----------------------\_______________________/--------------
# | launch edge (due to negedge reg)
# | | |
# 0 1 2 -- Edge used for setup analysis
#
# | | |
# 3 2 1
# | |
# | \____ Edge used for hold
# |
# \____ Actual hold edge
#
# Maximum path delay = 13 ns
# To shift timing analysis to the correct edges, the timing windows is shifted by
# one clock cycle, which is performed by subtracting a prc_clock period from
# the original path delays.
@define $lo_spi_output_max_delay 13.0 - $prc_clock_period ;
# Minimum path delay = -13 ns
# This constraint can be left unmodified, this will result in a more conservative constraint
# (using edge #2 instead of edge #1 for timing analysis). The main reason for this
# over-constraining is that edge#1 requires making the minimum delay a positive number,
# higher than the maximum delay. The current state of this constraint still
# guarantees that data is held stable during the hold period.
@define $lo_spi_output_min_delay -13.000 ;
CLOCK_TO_OUT GROUP LO_SPI_TX0_LO1_OUTPUT_PORTS OUTPUT_DELAY $lo_spi_output_max_delay ns
MIN $lo_spi_output_min_delay ns
CLKPORT "CPLD_REFCLK"
CLKOUT PORT "TX0_LO1_SCK" ;
CLOCK_TO_OUT GROUP LO_SPI_TX0_LO2_OUTPUT_PORTS OUTPUT_DELAY $lo_spi_output_max_delay ns
MIN $lo_spi_output_min_delay ns
CLKPORT "CPLD_REFCLK"
CLKOUT PORT "TX0_LO2_SCK" ;
CLOCK_TO_OUT GROUP LO_SPI_TX1_LO1_OUTPUT_PORTS OUTPUT_DELAY $lo_spi_output_max_delay ns
MIN $lo_spi_output_min_delay ns
CLKPORT "CPLD_REFCLK"
CLKOUT PORT "TX1_LO1_SCK" ;
CLOCK_TO_OUT GROUP LO_SPI_TX1_LO2_OUTPUT_PORTS OUTPUT_DELAY $lo_spi_output_max_delay ns
MIN $lo_spi_output_min_delay ns
CLKPORT "CPLD_REFCLK"
CLKOUT PORT "TX1_LO2_SCK" ;
CLOCK_TO_OUT GROUP LO_SPI_RX0_LO1_OUTPUT_PORTS OUTPUT_DELAY $lo_spi_output_max_delay ns
MIN $lo_spi_output_min_delay ns
CLKPORT "CPLD_REFCLK"
CLKOUT PORT "RX0_LO1_SCK" ;
CLOCK_TO_OUT GROUP LO_SPI_RX0_LO2_OUTPUT_PORTS OUTPUT_DELAY $lo_spi_output_max_delay ns
MIN $lo_spi_output_min_delay ns
CLKPORT "CPLD_REFCLK"
CLKOUT PORT "RX0_LO2_SCK" ;
CLOCK_TO_OUT GROUP LO_SPI_RX1_LO1_OUTPUT_PORTS OUTPUT_DELAY $lo_spi_output_max_delay ns
MIN $lo_spi_output_min_delay ns
CLKPORT "CPLD_REFCLK"
CLKOUT PORT "RX1_LO1_SCK" ;
CLOCK_TO_OUT GROUP LO_SPI_RX1_LO2_OUTPUT_PORTS OUTPUT_DELAY $lo_spi_output_max_delay ns
MIN $lo_spi_output_min_delay ns
CLKPORT "CPLD_REFCLK"
CLKOUT PORT "RX1_LO2_SCK" ;
# -- Multi-cycle path for SPI MUXOUT --
# ----------------------------------------
# edge # 1 2 3 4 5 6 7 8
# clk50 __/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/--
# sclk __/-----------------------\_______________________/-----------------------\_______________________/--
# muxout MSB | MSB-1
# launch edge |
# | | |
# 0 1 2
# \_ Edge used for setup analysis
# | | |
# 3 2 1
# |
# \____ Edge used for hold = 3
#
# Maximum path delay = 16 ns
# Setup analysis can be shifted from edge #4 to edge #5 by
# subtracting a clock period from the maximum delay.
@define $lo_spi_input_max_delay 16.000 - $prc_clock_period ;
# For hold analysis, we conservatively set the minimum delay of the
# MUXOUT path to 0.
@define $lo_spi_input_min_delay 0.000 ;
INPUT_SETUP GROUP LO_SPI_INPUT_PORTS INPUT_DELAY $lo_spi_input_max_delay ns
HOLD $lo_spi_input_min_delay ns
CLKPORT "CPLD_REFCLK";
# Add very loose timing requirements for clocks
CLOCK_TO_OUT GROUP LO_SPI_CLKS OUTPUT_DELAY $generic_ext_flop_tsu ns
MIN $generic_ext_flop_th ns
CLKPORT "CPLD_REFCLK" ;
#####################################################################
# Clock Shift paths
#####################################################################
# pll_ref_clk_adjusted flip-flops will show hold violations from pll_ref_clk signals
# as Diamond fails to recognize the proper edges to use for the timing analysis.
# A multi-cycle constraint is used to analyze against the previous ref_clk cycle.
#
# *Launch Edge(with adjustments)
# |
# | * Launch edge(according to Diamond)
# | |
# | |
# ref_clk __/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\
# shifted clk ----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\____
# |
# |
# Capture edge
MULTICYCLE FROM CLKNET "pll_ref_clk" TO CLKNET "pll_ref_clk_adjusted" 0 X;
######################################################################################
# Pin Location Information
######################################################################################
LOCATE COMP "TX0_SW3_B" SITE "B1" ;
LOCATE COMP "MB_FPGA_GPIO[1]" SITE "D3" ;
LOCATE COMP "MB_CTRL_CS" SITE "D1" ;
LOCATE COMP "MB_CTRL_MOSI" SITE "E2" ;
LOCATE COMP "MB_FPGA_GPIO[12]" SITE "E3" ;
LOCATE COMP "MB_FPGA_GPIO[9]" SITE "C1" ;
LOCATE COMP "MB_FPGA_GPIO[10]" SITE "D2" ;
LOCATE COMP "MB_CTRL_SCK" SITE "E1" ;
LOCATE COMP "MB_FPGA_GPIO[13]" SITE "F2" ;
LOCATE COMP "MB_FPGA_GPIO[2]" SITE "F4" ;
LOCATE COMP "MB_FPGA_GPIO[0]" SITE "G6" ;
LOCATE COMP "MB_FPGA_GPIO[5]" SITE "F3" ;
LOCATE COMP "MB_FPGA_GPIO[6]" SITE "F1" ;
LOCATE COMP "MB_FPGA_GPIO[4]" SITE "G5" ;
LOCATE COMP "MB_CTRL_MISO" SITE "G4" ;
LOCATE COMP "MB_FPGA_GPIO[8]" SITE "G2" ;
LOCATE COMP "MB_FPGA_GPIO[7]" SITE "G3" ;
LOCATE COMP "MB_FPGA_GPIO[11]" SITE "F5" ;
LOCATE COMP "MB_FPGA_GPIO[3]" SITE "H6" ;
LOCATE COMP "TX1_SW3_A" SITE "G1" ;
LOCATE COMP "TX0_SW6_A" SITE "H2" ;
LOCATE COMP "TX0_SW4_B" SITE "H4" ;
LOCATE COMP "TX1_SW3_B" SITE "H3" ;
LOCATE COMP "TX0_SW6_B" SITE "J6" ;
LOCATE COMP "TX1_SW6_B" SITE "H1" ;
LOCATE COMP "MB_SYNTH_SYNC" SITE "J1" ;
LOCATE COMP "TX1_SW6_A" SITE "J3" ;
LOCATE COMP "TX0_SW4_A" SITE "J2" ;
LOCATE COMP "TX0_SW3_A" SITE "H5" ;
LOCATE COMP "TX1_SW4_B" SITE "K1" ;
LOCATE COMP "TX1_SW4_A" SITE "J4" ;
LOCATE COMP "TX0_SW5_B" SITE "K3" ;
LOCATE COMP "CTRL_REG_ARST" SITE "K2" ;
LOCATE COMP "TX0_SW5_A" SITE "J5" ;
LOCATE COMP "RX1_SW11_V3" SITE "L1" ;
LOCATE COMP "RX0_DSA1_n[3]" SITE "L3" ;
LOCATE COMP "RX0_SW11_V3" SITE "K4" ;
LOCATE COMP "RX0_DSA1_n[1]" SITE "L5" ;
LOCATE COMP "RX0_DSA1_n[2]" SITE "L2" ;
LOCATE COMP "TX1_SW5_B" SITE "M1" ;
LOCATE COMP "CH1_TX_LED" SITE "K5" ;
LOCATE COMP "TX1_DSA2[2]" SITE "L4" ;
LOCATE COMP "RX1_DSA2_n[4]" SITE "N2" ;
LOCATE COMP "RX1_DSA3_B_n[4]" SITE "P1" ;
LOCATE COMP "RX0_SW5_A" SITE "M3" ;
LOCATE COMP "TX1_SW5_A" SITE "N1" ;
LOCATE COMP "RX0_DSA1_n[4]" SITE "M2" ;
LOCATE COMP "RX1_DSA2_n[3]" SITE "N3" ;
LOCATE COMP "RX0_DSA3_B_n[1]" SITE "R1" ;
LOCATE COMP "RX0_DSA2_n[1]" SITE "P2" ;
LOCATE COMP "RX0_DSA2_n[3]" SITE "P4" ;
LOCATE COMP "RX0_DSA3_B_n[3]" SITE "T4" ;
LOCATE COMP "RX1_DSA3_B_n[3]" SITE "T2" ;
LOCATE COMP "RX0_DSA3_B_n[2]" SITE "R3" ;
LOCATE COMP "RX0_DSA2_n[4]" SITE "R5" ;
LOCATE COMP "RX1_DSA1_n[3]" SITE "P5" ;
LOCATE COMP "RX1_DSA3_B_n[2]" SITE "T3" ;
LOCATE COMP "RX1_DSA3_B_n[1]" SITE "R4" ;
LOCATE COMP "RX0_DSA3_B_n[4]" SITE "T5" ;
LOCATE COMP "TX0_SW10_A" SITE "R6" ;
LOCATE COMP "RX1_DSA2_n[1]" SITE "P6" ;
LOCATE COMP "TX0_SW10_B" SITE "T6" ;
LOCATE COMP "RX1_DSA1_n[2]" SITE "N6" ;
LOCATE COMP "RX1_SW4_A" SITE "L7" ;
LOCATE COMP "RX0_SW1_A" SITE "R7" ;
LOCATE COMP "RX0_SW2_A" SITE "P7" ;
LOCATE COMP "RX1_SW5_B" SITE "M7" ;
LOCATE COMP "RX0_DSA2_n[2]" SITE "N7" ;
LOCATE COMP "RX0_SW5_B" SITE "M6" ;
LOCATE COMP "CH1_RX_LED" SITE "L8" ;
LOCATE COMP "RX0_SW1_B" SITE "T7" ;
LOCATE COMP "RX1_SW6_A" SITE "R8" ;
LOCATE COMP "RX1_SW2_A" SITE "P8" ;
LOCATE COMP "RX1_SW6_B" SITE "T8" ;
LOCATE COMP "RX1_DSA1_n[1]" SITE "N8" ;
LOCATE COMP "TX1_DSA2[5]" SITE "L9" ;
LOCATE COMP "RX1_DSA2_n[2]" SITE "M8" ;
LOCATE COMP "RX0_SW11_V1" SITE "N9" ;
LOCATE COMP "RX0_SW6_B" SITE "T9" ;
LOCATE COMP "RX1_SW11_V2" SITE "P9" ;
LOCATE COMP "RX1_SW3_V1" SITE "R9" ;
LOCATE COMP "RX0_SW6_A" SITE "T10" ;
LOCATE COMP "RX1_DSA1_n[4]" SITE "M9" ;
LOCATE COMP "RX1_SW5_A" SITE "L10" ;
LOCATE COMP "RX0_SW10_V1" SITE "P10" ;
LOCATE COMP "RX0_SW3_V3" SITE "R10" ;
LOCATE COMP "RX1_SW10_V1" SITE "N10" ;
LOCATE COMP "RX0_DSA3_A_n[1]" SITE "M11" ;
LOCATE COMP "TX0_SW11_B" SITE "T11" ;
LOCATE COMP "RX1_LO2_MUXOUT" SITE "P11" ;
LOCATE COMP "CH0_RX2_LED" SITE "M10" ;
LOCATE COMP "CH0_TX_LED" SITE "N11" ;
LOCATE COMP "RX0_LO1_MUXOUT" SITE "R13" ;
LOCATE COMP "RX1_SW3_V2" SITE "T14" ;
LOCATE COMP "CH0_RX_LED" SITE "R11" ;
LOCATE COMP "TX0_SW11_A" SITE "T12" ;
LOCATE COMP "RX0_LO2_MUXOUT" SITE "P12" ;
LOCATE COMP "RX0_SW3_V1" SITE "T13" ;
LOCATE COMP "RX1_SW11_V1" SITE "T15" ;
LOCATE COMP "RX1_SW3_V3" SITE "R14" ;
LOCATE COMP "RX0_SW11_V2" SITE "R16" ;
LOCATE COMP "RX0_DSA3_A_n[2]" SITE "P15" ;
LOCATE COMP "RX0_SW9_V1" SITE "N14" ;
LOCATE COMP "P7V_PG_A" SITE "N16" ;
LOCATE COMP "P7V_ENABLE_B" SITE "P16" ;
LOCATE COMP "P7V_ENABLE_A" SITE "M15" ;
LOCATE COMP "P3D3VA_ENABLE" SITE "N15" ;
LOCATE COMP "RX1_LO1_MUXOUT" SITE "M14" ;
LOCATE COMP "RX1_SW9_V1" SITE "L13" ;
LOCATE COMP "P7V_PG_B" SITE "M16" ;
LOCATE COMP "RX0_SW4_A" SITE "K11" ;
LOCATE COMP "RX0_DSA3_A_n[4]" SITE "L15" ;
LOCATE COMP "RX1_DSA3_A_n[1]" SITE "K12" ;
LOCATE COMP "RX0_DSA3_A_n[3]" SITE "L14" ;
LOCATE COMP "RX1_DSA3_A_n[2]" SITE "K13" ;
LOCATE COMP "RX1_LO2_SYNC" SITE "L16" ;
LOCATE COMP "RX0_SW3_V2" SITE "L12" ;
LOCATE COMP "RX1_LO2_SCK" SITE "K15" ;
LOCATE COMP "RX0_LO2_CSB" SITE "J11" ;
LOCATE COMP "RX1_DSA3_A_n[3]" SITE "K14" ;
LOCATE COMP "RX1_DSA3_A_n[4]" SITE "J13" ;
LOCATE COMP "RX0_LO2_SYNC" SITE "K16" ;
LOCATE COMP "TX1_LO1_CSB" SITE "H11" ;
LOCATE COMP "RX1_LO1_SCK" SITE "J15" ;
LOCATE COMP "TX1_LO2_SYNC" SITE "J14" ;
LOCATE COMP "RX0_LO1_SCK" SITE "J16" ;
LOCATE COMP "RX1_LO1_SYNC" SITE "H16" ;
LOCATE COMP "RX0_LO2_SCK" SITE "J12" ;
LOCATE COMP "CPLD_REFCLK" SITE "H14" ;
LOCATE COMP "RX1_LO2_CSB" SITE "H13" ;
LOCATE COMP "RX0_LO1_SYNC" SITE "H15" ;
LOCATE COMP "RX0_LO1_CSB" SITE "G16" ;
LOCATE COMP "TX0_LO1_SCK" SITE "H12" ;
LOCATE COMP "TX1_LO2_SCK" SITE "G14" ;
LOCATE COMP "TX1_DSA2[4]" SITE "G11" ;
LOCATE COMP "TX0_LO2_SCK" SITE "G15" ;
LOCATE COMP "RX1_LO1_CSB" SITE "G13" ;
LOCATE COMP "TX0_LO2_CSB" SITE "F16" ;
LOCATE COMP "RX1_SW7_SW8_CTRL" SITE "F12" ;
LOCATE COMP "TX0_LO1_SYNC" SITE "F14" ;
LOCATE COMP "TX0_LO2_MUXOUT" SITE "G12" ;
LOCATE COMP "RX_TX_LO_SDI" SITE "F15" ;
LOCATE COMP "TX0_DSA1[3]" SITE "F13" ;
LOCATE COMP "TX1_LO2_CSB" SITE "E16" ;
LOCATE COMP "TX0_DSA1[6]" SITE "D15" ;
LOCATE COMP "TX1_LO1_SYNC" SITE "C16" ;
LOCATE COMP "TX1_LO1_SCK" SITE "E14" ;
LOCATE COMP "TX0_LO1_CSB" SITE "D16" ;
LOCATE COMP "TX1_DSA1[4]" SITE "B16" ;
LOCATE COMP "TX0_LO2_SYNC" SITE "E15" ;
LOCATE COMP "TX1_SW1_SW2_CTRL" SITE "C15" ;
LOCATE COMP "TX1_DSA1[3]" SITE "D14" ;
LOCATE COMP "TX1_DSA1[5]" SITE "A15" ;
LOCATE COMP "TX1_DSA1[6]" SITE "B14" ;
LOCATE COMP "TX1_LO2_MUXOUT" SITE "B12" ;
LOCATE COMP "TX1_DSA1[2]" SITE "C12" ;
LOCATE COMP "TX0_DSA1[4]" SITE "A14" ;
LOCATE COMP "TX0_DSA1[5]" SITE "B13" ;
LOCATE COMP "TX0_SW1_SW2_CTRL" SITE "A12" ;
LOCATE COMP "TX0_SW14_V1" SITE "B11" ;
LOCATE COMP "RX0_SW7_SW8_CTRL" SITE "D11" ;
LOCATE COMP "TX0_DSA1[2]" SITE "C11" ;
LOCATE COMP "TX1_DSA2[3]" SITE "F10" ;
LOCATE COMP "CH1_RX2_LED" SITE "A11" ;
LOCATE COMP "TX0_DSA2[5]" SITE "E10" ;
LOCATE COMP "TX1_LO1_MUXOUT" SITE "D10" ;
LOCATE COMP "TX0_SW13_V1" SITE "E11" ;
LOCATE COMP "TX1_DSA2[6]" SITE "F9" ;
LOCATE COMP "TX1_SW13_V1" SITE "A10" ;
LOCATE COMP "TX1_SW14_V1" SITE "B9" ;
LOCATE COMP "TX0_SW8_V1" SITE "D9" ;
LOCATE COMP "TX1_SW8_V1" SITE "C9" ;
LOCATE COMP "TX1_SW10_A" SITE "F8" ;
LOCATE COMP "TX0_LO1_MUXOUT" SITE "A9" ;
LOCATE COMP "RX1_SW1_B" SITE "E9" ;
LOCATE COMP "TX1_SW8_V2" SITE "D8" ;
LOCATE COMP "TX1_SW8_V3" SITE "A8" ;
LOCATE COMP "TX0_SW8_V2" SITE "C8" ;
LOCATE COMP "RX1_SW1_A" SITE "E8" ;
LOCATE COMP "TX1_SW11_B" SITE "F7" ;
LOCATE COMP "TX1_SW11_A" SITE "D7" ;
LOCATE COMP "TX0_DSA2[3]" SITE "C7" ;
LOCATE COMP "TX0_SW7_B" SITE "E6" ;
LOCATE COMP "TX1_SW9_B" SITE "B7" ;
LOCATE COMP "TX1_SW10_B" SITE "E7" ;
LOCATE COMP "TX0_DSA2[4]" SITE "D6" ;
LOCATE COMP "TX0_DSA2[6]" SITE "B4" ;
LOCATE COMP "TX0_DSA2[2]" SITE "A3" ;
LOCATE COMP "TX0_SW8_V3" SITE "B6" ;
LOCATE COMP "TX0_SW9_A" SITE "A5" ;
LOCATE COMP "TX1_SW7_B" SITE "C5" ;
LOCATE COMP "TX0_SW9_B" SITE "A4" ;
LOCATE COMP "TX1_SW9_A" SITE "B5" ;
LOCATE COMP "TX1_SW7_A" SITE "B3" ;
LOCATE COMP "TX0_SW7_A" SITE "C4" ;
######################################################################################
# Bank Voltage Information
######################################################################################
BANK 5 VCCIO 1.8 V;
BANK 4 VCCIO 1.8 V;
BANK 3 VCCIO 3.3 V;
BANK 2 VCCIO 3.3 V;
BANK 1 VCCIO 3.3 V;
BANK 0 VCCIO 3.3 V;
######################################################################################
# Pin Drive information
######################################################################################
#Below is a starting point for Drive strength selection, each designer must decide what drive strength is appropriate for their design
#HYSTERSIS is not specified for all inputs and assume default value, they may be turned on as follows SMALL and LARGE are available options, assuming you want LVCMOS25
#IOBUF PORT "SigName" IO_TYPE=LVCMOS25 PULLMODE=NONE CLAMP=OFF HYSTERESIS=SMALL ;
#CLAMP=OFF set to all pins, may be changed as desired.
#Drive set to 8mA SLOW for all pins, may be changed as desired. In future could have tool auto determine best drive, but for now defaults to 8mA slow
IOBUF PORT "TX0_SW3_B" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "MB_FPGA_GPIO[1]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "MB_CTRL_CS" IO_TYPE=LVCMOS18 PULLMODE=NONE CLAMP=OFF ;
IOBUF PORT "MB_CTRL_MOSI" IO_TYPE=LVCMOS18 PULLMODE=NONE CLAMP=OFF ;
IOBUF PORT "MB_FPGA_GPIO[12]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "MB_FPGA_GPIO[9]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "MB_FPGA_GPIO[10]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "MB_CTRL_SCK" IO_TYPE=LVCMOS18 PULLMODE=NONE CLAMP=OFF ;
IOBUF PORT "MB_FPGA_GPIO[13]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "MB_FPGA_GPIO[2]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "MB_FPGA_GPIO[0]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "MB_FPGA_GPIO[5]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "MB_FPGA_GPIO[6]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "MB_FPGA_GPIO[4]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "MB_CTRL_MISO" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "MB_FPGA_GPIO[8]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "MB_FPGA_GPIO[7]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "MB_FPGA_GPIO[11]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "MB_FPGA_GPIO[3]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_SW3_A" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_SW6_A" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_SW4_B" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_SW3_B" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_SW6_B" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_SW6_B" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "MB_SYNTH_SYNC" IO_TYPE=LVCMOS18 PULLMODE=NONE CLAMP=OFF ;
IOBUF PORT "TX1_SW6_A" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_SW4_A" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_SW3_A" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_SW4_B" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_SW4_A" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_SW5_B" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "CTRL_REG_ARST" IO_TYPE=LVCMOS18 PULLMODE=NONE CLAMP=OFF ;
IOBUF PORT "TX0_SW5_A" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_SW11_V3" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_DSA1_n[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_SW11_V3" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_DSA1_n[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_DSA1_n[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_SW5_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "CH1_TX_LED" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_DSA2[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_DSA2_n[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_DSA3_B_n[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_SW5_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_SW5_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_DSA1_n[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_DSA2_n[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_DSA3_B_n[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_DSA2_n[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_DSA2_n[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_DSA3_B_n[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_DSA3_B_n[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_DSA3_B_n[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_DSA2_n[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_DSA1_n[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_DSA3_B_n[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_DSA3_B_n[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_DSA3_B_n[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_SW10_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_DSA2_n[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_SW10_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_DSA1_n[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_SW4_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_SW1_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_SW2_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_SW5_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_DSA2_n[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_SW5_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "CH1_RX_LED" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_SW1_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_SW6_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_SW2_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_SW6_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_DSA1_n[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_DSA2[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_DSA2_n[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_SW11_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_SW6_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_SW11_V2" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_SW3_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_SW6_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_DSA1_n[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_SW5_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_SW10_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_SW3_V3" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_SW10_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_DSA3_A_n[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_SW11_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_LO2_MUXOUT" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ;
IOBUF PORT "CH0_RX2_LED" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "CH0_TX_LED" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_LO1_MUXOUT" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ;
IOBUF PORT "RX1_SW3_V2" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "CH0_RX_LED" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_SW11_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_LO2_MUXOUT" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ;
IOBUF PORT "RX0_SW3_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_SW11_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_SW3_V3" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_SW11_V2" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_DSA3_A_n[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_SW9_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "P7V_PG_A" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ;
IOBUF PORT "P7V_ENABLE_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "P7V_ENABLE_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "P3D3VA_ENABLE" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_LO1_MUXOUT" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ;
IOBUF PORT "RX1_SW9_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "P7V_PG_B" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ;
IOBUF PORT "RX0_SW4_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_DSA3_A_n[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_DSA3_A_n[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_DSA3_A_n[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_DSA3_A_n[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_LO2_SYNC" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_SW3_V2" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_LO2_SCK" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_LO2_CSB" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_DSA3_A_n[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_DSA3_A_n[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_LO2_SYNC" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_LO1_CSB" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_LO1_SCK" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_LO2_SYNC" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_LO1_SCK" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_LO1_SYNC" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_LO2_SCK" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "CPLD_REFCLK" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ;
IOBUF PORT "RX1_LO2_CSB" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_LO1_SYNC" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_LO1_CSB" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_LO1_SCK" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_LO2_SCK" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_DSA2[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_LO2_SCK" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_LO1_CSB" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_LO2_CSB" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_SW7_SW8_CTRL" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_LO1_SYNC" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_LO2_MUXOUT" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ;
IOBUF PORT "RX_TX_LO_SDI" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=16 SLEWRATE=FAST CLAMP=OFF ;
IOBUF PORT "TX0_DSA1[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_LO2_CSB" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_DSA1[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_LO1_SYNC" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_LO1_SCK" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_LO1_CSB" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_DSA1[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_LO2_SYNC" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_SW1_SW2_CTRL" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_DSA1[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_DSA1[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_DSA1[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_LO2_MUXOUT" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ;
IOBUF PORT "TX1_DSA1[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_DSA1[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_DSA1[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_SW1_SW2_CTRL" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_SW14_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX0_SW7_SW8_CTRL" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_DSA1[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_DSA2[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "CH1_RX2_LED" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_DSA2[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_LO1_MUXOUT" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ;
IOBUF PORT "TX0_SW13_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_DSA2[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_SW13_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_SW14_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_SW8_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_SW8_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_SW10_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_LO1_MUXOUT" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ;
IOBUF PORT "RX1_SW1_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_SW8_V2" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_SW8_V3" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_SW8_V2" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "RX1_SW1_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_SW11_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_SW11_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_DSA2[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_SW7_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_SW9_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_SW10_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_DSA2[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_DSA2[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_DSA2[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_SW8_V3" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_SW9_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_SW7_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_SW9_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_SW9_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX1_SW7_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
IOBUF PORT "TX0_SW7_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
top/x400/dboards/zbx/cpld/lattice/zbx_top_cpld.sty
+205
View File
@@ -0,0 +1,205 @@
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE strategy>
<Strategy version="1.0" predefined="0" description="" label="zbx_cpld_strat">
<Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
<Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
<Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
<Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
<Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
<Property name="PROP_BD_EdfMemPath" value="" time="0"/>
<Property name="PROP_BD_ParSearchPath" value="" time="0"/>
<Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
<Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
<Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
<Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
<Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
<Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
<Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
<Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
<Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
<Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
<Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
<Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
<Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
<Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
<Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
<Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
<Property name="PROP_BIT_NoHeader" value="False" time="0"/>
<Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
<Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/>
<Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
<Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
<Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
<Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
<Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
<Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
<Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
<Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
<Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
<Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
<Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
<Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
<Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
<Property name="PROP_LST_CarryChain" value="True" time="0"/>
<Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
<Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
<Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
<Property name="PROP_LST_DSPUtil" value="100" time="0"/>
<Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
<Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
<Property name="PROP_LST_EBRUtil" value="100" time="0"/>
<Property name="PROP_LST_EdfFrequency" value="100" time="0"/>
<Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
<Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
<Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
<Property name="PROP_LST_EdfMemPath" value="" time="0"/>
<Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
<Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
<Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
<Property name="PROP_LST_IOInsertion" value="True" time="0"/>
<Property name="PROP_LST_InterFileDump" value="False" time="0"/>
<Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
<Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
<Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
<Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
<Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/>
<Property name="PROP_LST_PropagatConst" value="True" time="0"/>
<Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
<Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
<Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
<Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
<Property name="PROP_LST_ResourceShare" value="True" time="0"/>
<Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
<Property name="PROP_LST_UseLPF" value="True" time="0"/>
<Property name="PROP_LST_VHDL2008" value="False" time="0"/>
<Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
<Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
<Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
<Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
<Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
<Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
<Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
<Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
<Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
<Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
<Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
<Property name="PROP_MAP_MAPIORegister" value="Output" time="0"/>
<Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
<Property name="PROP_MAP_MapModArgs" value="" time="0"/>
<Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
<Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
<Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
<Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
<Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
<Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
<Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
<Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
<Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
<Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
<Property name="PROP_PARSTA_CheckUnconstrainedConns" value="True" time="0"/>
<Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="True" time="0"/>
<Property name="PROP_PARSTA_FullName" value="False" time="0"/>
<Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
<Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
<Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
<Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
<Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
<Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
<Property name="PROP_PAR_CrDlyStFileParDes" value="True" time="0"/>
<Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
<Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
<Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
<Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
<Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
<Property name="PROP_PAR_PARModArgs" value="" time="0"/>
<Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
<Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
<Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
<Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
<Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
<Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
<Property name="PROP_PAR_RouteDlyRedParDes" value="1" time="0"/>
<Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
<Property name="PROP_PAR_RouteResOptParDes" value="3" time="0"/>
<Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
<Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
<Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
<Property name="PROP_PAR_RunTimeReduction" value="True" time="0"/>
<Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
<Property name="PROP_PAR_StopZero" value="True" time="0"/>
<Property name="PROP_PAR_parHold" value="On" time="0"/>
<Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
<Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
<Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
<Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
<Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
<Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
<Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
<Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
<Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
<Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
<Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
<Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
<Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
<Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
<Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
<Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
<Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
<Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
<Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
<Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
<Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
<Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
<Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
<Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
<Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
<Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
<Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
<Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
<Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
<Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
<Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
<Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
<Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
<Property name="PROP_SYN_DisableRegisterRep" value="False" time="0"/>
<Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
<Property name="PROP_SYN_EdfArea" value="False" time="0"/>
<Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
<Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
<Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
<Property name="PROP_SYN_EdfFrequency" value="100" time="0"/>
<Property name="PROP_SYN_EdfGSR" value="Auto" time="0"/>
<Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
<Property name="PROP_SYN_EdfNumCritPath" value="3" time="0"/>
<Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
<Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
<Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
<Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
<Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
<Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
<Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
<Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
<Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
<Property name="PROP_SYN_LibPath" value="" time="0"/>
<Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
<Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
<Property name="PROP_SYN_UseLPF" value="True" time="0"/>
<Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
<Property name="PROP_THERMAL_DefaultFreq" value="64" time="0"/>
<Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
<Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
<Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
<Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
<Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
<Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
<Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
<Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
<Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
<Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
<Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
</Strategy>