Javier Valenzuela
a6fc53b4e6
The main changes included are: - Variant-dependent pin-out instantiation. - Update clocking scheme in top level file to include XO3 PLL - Add ability to shift outgoing data for the GPIO communication interface with the X410 FPGA. - Include project files required to build the XO3 variant of the ZBX CPLD. - Add build flow for Lattice Diamond designs. - Add ability to build XO3 variant of ZBX CPLD. Original-commit: 2c7813acb21383f302353a1b6cf57f0946fa0b6b
96 lines
4.5 KiB
XML
96 lines
4.5 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<BaliProject version="3.2" title="zbx_top_cpld" device="LCMXO3LF-9400C-6BG256I" default_implementation="impl1">
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<Options/>
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<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="zbx_cpld_strat">
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<Options VERILOG_DIRECTIVES="VARIANT_XO3" def_top="zbx_top_cpld" top="zbx_top_cpld"/>
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<Source name="../zbx_cpld_core.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../zbx_top_cpld.v" type="Verilog" type_short="Verilog">
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<Options top_module="zbx_top_cpld"/>
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</Source>
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<Source name="../../../../../../lib/control/handshake.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../../../../../lib/control/pulse_synchronizer.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../../../../../lib/control/ram_2port.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../../../../../lib/control/reset_sync.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../../../../../lib/control/synchronizer.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../../../../../lib/control/synchronizer_impl.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../../../cpld/reconfig_engine.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../../ctrlport_byte_deserializer.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../../../../../lib/rfnoc/utils/ctrlport_splitter.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../../../../../lib/wb_spi/rtl/verilog/spi_clgen.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../../../../../lib/wb_spi/rtl/verilog/spi_shift.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../../../../../lib/wb_spi/rtl/verilog/spi_top.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../../../cpld/spi_slave.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../../../cpld/spi_slave_to_ctrlport_master.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../../../../../lib/rfnoc/utils/ctrlport_window.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../register_endpoints/atr_controller.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../register_endpoints/basic_regs.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../register_endpoints/dsa_control.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../register_endpoints/led_control.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../register_endpoints/lo_control.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../register_endpoints/power_regs.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../register_endpoints/switch_control.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../../../../../lib/rfnoc/utils/ctrlport_clk_cross.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../../../../../../lib/rfnoc/utils/ctrlport_combiner.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="ip/pll/pll.ipx" type="IPX_Module" type_short="IPX">
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<Options/>
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</Source>
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<Source name="zbx_top_cpld.lpf" type="Logic Preference" type_short="LPF">
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<Options/>
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</Source>
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<Source name="../zbx_top_cpld_gpio.ldc" type="LSE Design Constraints File" type_short="LDC" excluded="TRUE">
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<Options/>
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</Source>
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</Implementation>
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<Strategy name="zbx_cpld_strat" file="zbx_top_cpld.sty"/>
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</BaliProject>
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