Javier Valenzuela
a6fc53b4e6
The main changes included are: - Variant-dependent pin-out instantiation. - Update clocking scheme in top level file to include XO3 PLL - Add ability to shift outgoing data for the GPIO communication interface with the X410 FPGA. - Include project files required to build the XO3 variant of the ZBX CPLD. - Add build flow for Lattice Diamond designs. - Add ability to build XO3 variant of ZBX CPLD. Original-commit: 2c7813acb21383f302353a1b6cf57f0946fa0b6b
804 lines
48 KiB
Plaintext
804 lines
48 KiB
Plaintext
#
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# Copyright 2022 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# This file follows the Lattice Preference File style to describe
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# timing constraints for a Lattice Diamond Synplify build flow.
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#
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##### GENERAL TIMING DISCLAIMER ########
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# Multiple constraints within this file use constant numbers to describe their
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# respective input and output delays. The values presented were generated by
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# evaluating constraints described for the MAX10 variant of this CPLD.
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# Additional considerations were used when a constraint could not be written
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# in the same way for both variants(such as in additional delays present in
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# the datapath or data being generated on falling edges). In such cases,
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# additional comments describing the origin of the value used are provided.
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# The original constraints used to compute the values used in this file are
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# located at:
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# ../quartus/zbx_top_cpld.qsf
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######################################################################################
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# Timing
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######################################################################################
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# base clocks
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@define $prc_clock_period 15.625 ;
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@define $ctrl_sclk_period $prc_clock_period * 3.0 ;
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PERIOD PORT "CPLD_REFCLK" $prc_clock_period ;
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PERIOD PORT "MB_CTRL_SCK" $ctrl_sclk_period ;
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FREQUENCY NET "clk_int_osc" 66.500000 MHz ;
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############# MB GPIO ##################
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# OUTPUT PATH
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# --------------------------------------------------------------------------------------
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# P&R fails when using delay values from original design. To make it easier for
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# timing to be met, this interface uses an adjusted version of the clock, shifted
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# by 225 degrees. Unfortunately, the use of a shifted clock result in the analysis
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# of this input path to be incorrect
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# The following diagram represents the timing for the GPIO communication interface
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# considering data generated on a shifted clock.
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#
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# *Launch Edge(according to Diamond)
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# |
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# | * Latch edge(according to Diamond)
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# | |
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# | | * Actual Latch Edge.
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# | | |
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# ref_clk __/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\
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# Max Output Delay _____________XXXXXXXX__________________________________________
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# Min Output Delay ________XXX____________________________________________________
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# shifted clk ----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\____
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# |
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# |
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# * Data gets generated by shifted clock
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# A potential solution for this would be to use multi-cycle path constraints to
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# shift the analysis to the actual latch edge. This is not supported in Diamond,
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# as output delay constraints are incompatible with multi-cycle constraints.
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#
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# After contacting Lattice, it was determined that the best solution was to compensate
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# the delay that would be inserted by a multi-cycle constraint in the output delay
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# constraint(effectively analyzing the timing from the detected to the actual
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# latch edge).
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# An advantage of this implementation is the ability to consider the worst-case clock
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# frequency for the different scenarios analyzed.
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# Maximum path delay = 8.5 ns
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# Minimum path delay = -2 ns
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# To shift timing analysis to the correct edges, the timing windows is shifted by
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# one clock cycle, which is performed by subtracting a prc_clock period from
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# the original path delays.
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@define $gpio_max_output_delay 8.5 - $prc_clock_period ;
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@define $gpio_min_output_delay -2.0 - $prc_clock_period ;
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# This analysis results in the following constraint.
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CLOCK_TO_OUT PORT "MB_FPGA_GPIO*" OUTPUT_DELAY $gpio_max_output_delay ns
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MIN $gpio_min_output_delay ns
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CLKPORT "CPLD_REFCLK" ;
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# INPUT PATH
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# --------------------------------------------------------------------------------------
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# This path uses prc_clk with no phase alterations.
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# The input path for GPIO lanes is driven in the falling edge of the clock, and some correction
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# is performed for this adjustment.
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#
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# *Launch Edge(according to Diamond)
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# |
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# | * Actual Launch Edge
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# | |
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# | | * Actual Latch Edge.
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# | | |
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# ref_clk __/-----------\___________/-----------\___________/-----------\___________/------
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# Max Delay ______________XXXXX______________________________________________________________
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# Min Delay ______________XXX________________________________________________________________
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# Maximum path delay = 4.561
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# Minimum path delay = 4.045
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# To adjust the analysis to the correct launch edge, we increase the input delays by
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# half a prc_clock period. The CLK_OFFSET option is not used as it only changes
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# the analysis on the receiving flop.
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@define $gpio_max_input_delay $prc_clock_period / 2.0 + 4.561 ;
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@define $gpio_min_input_delay $prc_clock_period / 2.0 + 4.045 ;
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# Invert value for hold constraint
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@define $gpio_min_input_hold -1.0 * $gpio_min_input_delay ;
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# The adjusted values are used in the input constraint.
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INPUT_SETUP PORT "MB_FPGA_GPIO*" INPUT_DELAY $gpio_max_input_delay ns
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HOLD $gpio_min_input_hold ns
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CLKPORT "CPLD_REFCLK" ;
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############# LO SYNC ##################
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INPUT_SETUP PORT MB_SYNTH_SYNC INPUT_DELAY 6.747 HOLD -5.860 ns CLKPORT "CPLD_REFCLK" ;
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DEFINE PORT GROUP "LO_SYNC"
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"RX0_LO*_SYNC"
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"RX1_LO*_SYNC"
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"TX0_LO*_SYNC"
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"TX1_LO*_SYNC" ;
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CLOCK_TO_OUT GROUP LO_SYNC OUTPUT_DELAY 2.445 MIN 2.145 ns CLKPORT "CPLD_REFCLK" ;
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#####################################################################
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# Timing exceptions
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#####################################################################
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## synchronizers
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BLOCK PATH FROM PORT "CTRL_REG_ARST" TO CELL "*synchronizer_false_path*value_0*" ;
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#####################################################################
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# Asynchronous IO
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#####################################################################
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# For general I/O that don't have tight timing constraints, we can constrain
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# these paths by creating a generic flip-flop that will interface to the
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# device.
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# For asynchronous outputs
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@define $generic_ext_flop_tsu 1 ;
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@define $generic_ext_flop_th 0 ;
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# # For asynchronous inputs
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@define $generic_ext_flop_max_tco 1 ;
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@define $generic_ext_flop_min_tco 1 ;
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# REF CLK
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#--------------------------------------------------------------------
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DEFINE PORT GROUP "ASYNC_REFCLK_OUTPUTS"
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"CH*_*X*_LED"
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"RX*_DSA*_*[*]"
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"TX*_DSA*[*]"
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"*X*_SW*" ;
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CLOCK_TO_OUT GROUP ASYNC_REFCLK_OUTPUTS OUTPUT_DELAY $generic_ext_flop_tsu ns
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MIN $generic_ext_flop_th ns
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CLKPORT "CPLD_REFCLK" ;
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DEFINE PORT GROUP "ASYNC_REFCLK_INPUTS"
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"CTRL_REG_ARST" ;
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INPUT_SETUP GROUP ASYNC_REFCLK_INPUTS INPUT_DELAY $generic_ext_flop_max_tco ns
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HOLD $generic_ext_flop_min_tco ns
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CLKPORT "CPLD_REFCLK" ;
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# INT OSC
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#--------------------------------------------------------------------
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DEFINE PORT GROUP "ASYNC_INTOSC_OUTPUTS"
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"P*_ENABLE*" ;
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CLOCK_TO_OUT GROUP ASYNC_INTOSC_OUTPUTS OUTPUT_DELAY $generic_ext_flop_tsu ns
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MIN $generic_ext_flop_th ns
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CLKNET "clk_int_osc" ;
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DEFINE PORT GROUP "ASYNC_INTOSC_INPUTS"
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"P7V_PG_*" ;
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INPUT_SETUP GROUP ASYNC_INTOSC_INPUTS INPUT_DELAY $generic_ext_flop_max_tco ns
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HOLD $generic_ext_flop_min_tco ns
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CLKNET "clk_int_osc" ;
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#####################################################################
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# MB CPLD <-> DB CPLD CTRL SPI interface
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#####################################################################
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# The timing constants of the MB CPLD are defined in
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# fpga/usrp3/top/x400/cpld/db_spi_shared_constants.sdc
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@define $ctrl_spi_input_max_delay -2.014 ;
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@define $ctrl_spi_input_min_delay -4.500 ;
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DEFINE PORT GROUP "CTRL_SLAVE_INPUTS"
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"MB_CTRL_MOSI"
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"MB_CTRL_CS" ;
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INPUT_SETUP GROUP CTRL_SLAVE_INPUTS INPUT_DELAY $ctrl_spi_input_max_delay ns
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HOLD $ctrl_spi_input_min_delay ns
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CLKPORT "MB_CTRL_SCK"
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SS ;
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@define $ctrl_spi_output_max_delay 17.254 ;
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@define $ctrl_spi_output_min_delay -0.500 ;
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DEFINE PORT GROUP "CTRL_SLAVE_OUTPUTS"
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"MB_CTRL_MISO" ;
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CLOCK_TO_OUT GROUP CTRL_SLAVE_OUTPUTS OUTPUT_DELAY $ctrl_spi_output_max_delay ns
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MIN $ctrl_spi_output_min_delay ns
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CLKPORT "MB_CTRL_SCK" ;
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# Additionally, Lattice detects an unconstrained path from MB_CTRL_CS
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# to clk_int_osc. Since MB_CTRL_CS is asynchronous to that clock net,
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# we use the same constraint strategy as for other asynchronous
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# inputs.
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INPUT_SETUP PORT "MB_CTRL_CS" INPUT_DELAY $generic_ext_flop_max_tco ns
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HOLD $generic_ext_flop_min_tco ns
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CLKNET "clk_int_osc" ;
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#####################################################################
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# LO SPI interface
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#####################################################################
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PERIOD PORT "TX0_LO1_SCK" $prc_clock_period ;
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PERIOD PORT "RX0_LO1_SCK" $prc_clock_period ;
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PERIOD PORT "TX0_LO2_SCK" $prc_clock_period ;
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PERIOD PORT "RX0_LO2_SCK" $prc_clock_period ;
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PERIOD PORT "TX1_LO1_SCK" $prc_clock_period ;
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PERIOD PORT "RX1_LO1_SCK" $prc_clock_period ;
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PERIOD PORT "TX1_LO2_SCK" $prc_clock_period ;
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PERIOD PORT "RX1_LO2_SCK" $prc_clock_period ;
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DEFINE PORT GROUP "LO_SPI_CLKS"
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"*X*_LO*_SCK" ;
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DEFINE PORT GROUP "LO_SPI_TX0_LO1_OUTPUT_PORTS"
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"RX_TX_LO_SDI"
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"TX0_LO1_CSB" ;
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DEFINE PORT GROUP "LO_SPI_TX0_LO2_OUTPUT_PORTS"
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"RX_TX_LO_SDI"
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"TX0_LO2_CSB" ;
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DEFINE PORT GROUP "LO_SPI_TX1_LO1_OUTPUT_PORTS"
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"RX_TX_LO_SDI"
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"TX1_LO1_CSB" ;
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DEFINE PORT GROUP "LO_SPI_TX1_LO2_OUTPUT_PORTS"
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"RX_TX_LO_SDI"
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"TX1_LO2_CSB" ;
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DEFINE PORT GROUP "LO_SPI_RX0_LO1_OUTPUT_PORTS"
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"RX_TX_LO_SDI"
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"RX0_LO1_CSB" ;
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DEFINE PORT GROUP "LO_SPI_RX0_LO2_OUTPUT_PORTS"
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"RX_TX_LO_SDI"
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"RX0_LO2_CSB" ;
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DEFINE PORT GROUP "LO_SPI_RX1_LO1_OUTPUT_PORTS"
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"RX_TX_LO_SDI"
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"RX1_LO1_CSB" ;
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DEFINE PORT GROUP "LO_SPI_RX1_LO2_OUTPUT_PORTS"
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"RX_TX_LO_SDI"
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"RX1_LO2_CSB" ;
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DEFINE PORT GROUP "LO_SPI_INPUT_PORTS"
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"*X*_LO*_MUXOUT" ;
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# -- Multi-cycle path for SPI CS and SDI --
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# ----------------------------------------
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# edge # 1 2 3 4 5
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# clk50 __/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/--
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# sclk __/-----------------------\_______________________/--------------
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# | launch edge (due to negedge reg)
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# | | |
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# 0 1 2 -- Edge used for setup analysis
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#
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# | | |
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# 3 2 1
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# | |
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# | \____ Edge used for hold
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# |
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# \____ Actual hold edge
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#
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# Maximum path delay = 13 ns
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# To shift timing analysis to the correct edges, the timing windows is shifted by
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# one clock cycle, which is performed by subtracting a prc_clock period from
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# the original path delays.
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@define $lo_spi_output_max_delay 13.0 - $prc_clock_period ;
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# Minimum path delay = -13 ns
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# This constraint can be left unmodified, this will result in a more conservative constraint
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# (using edge #2 instead of edge #1 for timing analysis). The main reason for this
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# over-constraining is that edge#1 requires making the minimum delay a positive number,
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# higher than the maximum delay. The current state of this constraint still
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# guarantees that data is held stable during the hold period.
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@define $lo_spi_output_min_delay -13.000 ;
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CLOCK_TO_OUT GROUP LO_SPI_TX0_LO1_OUTPUT_PORTS OUTPUT_DELAY $lo_spi_output_max_delay ns
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MIN $lo_spi_output_min_delay ns
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CLKPORT "CPLD_REFCLK"
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CLKOUT PORT "TX0_LO1_SCK" ;
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CLOCK_TO_OUT GROUP LO_SPI_TX0_LO2_OUTPUT_PORTS OUTPUT_DELAY $lo_spi_output_max_delay ns
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MIN $lo_spi_output_min_delay ns
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CLKPORT "CPLD_REFCLK"
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CLKOUT PORT "TX0_LO2_SCK" ;
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CLOCK_TO_OUT GROUP LO_SPI_TX1_LO1_OUTPUT_PORTS OUTPUT_DELAY $lo_spi_output_max_delay ns
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MIN $lo_spi_output_min_delay ns
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CLKPORT "CPLD_REFCLK"
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CLKOUT PORT "TX1_LO1_SCK" ;
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CLOCK_TO_OUT GROUP LO_SPI_TX1_LO2_OUTPUT_PORTS OUTPUT_DELAY $lo_spi_output_max_delay ns
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MIN $lo_spi_output_min_delay ns
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CLKPORT "CPLD_REFCLK"
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CLKOUT PORT "TX1_LO2_SCK" ;
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CLOCK_TO_OUT GROUP LO_SPI_RX0_LO1_OUTPUT_PORTS OUTPUT_DELAY $lo_spi_output_max_delay ns
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MIN $lo_spi_output_min_delay ns
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CLKPORT "CPLD_REFCLK"
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CLKOUT PORT "RX0_LO1_SCK" ;
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CLOCK_TO_OUT GROUP LO_SPI_RX0_LO2_OUTPUT_PORTS OUTPUT_DELAY $lo_spi_output_max_delay ns
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MIN $lo_spi_output_min_delay ns
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CLKPORT "CPLD_REFCLK"
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CLKOUT PORT "RX0_LO2_SCK" ;
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CLOCK_TO_OUT GROUP LO_SPI_RX1_LO1_OUTPUT_PORTS OUTPUT_DELAY $lo_spi_output_max_delay ns
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MIN $lo_spi_output_min_delay ns
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CLKPORT "CPLD_REFCLK"
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CLKOUT PORT "RX1_LO1_SCK" ;
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CLOCK_TO_OUT GROUP LO_SPI_RX1_LO2_OUTPUT_PORTS OUTPUT_DELAY $lo_spi_output_max_delay ns
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MIN $lo_spi_output_min_delay ns
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CLKPORT "CPLD_REFCLK"
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CLKOUT PORT "RX1_LO2_SCK" ;
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# -- Multi-cycle path for SPI MUXOUT --
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# ----------------------------------------
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# edge # 1 2 3 4 5 6 7 8
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# clk50 __/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/--
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# sclk __/-----------------------\_______________________/-----------------------\_______________________/--
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# muxout MSB | MSB-1
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# launch edge |
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# | | |
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# 0 1 2
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# \_ Edge used for setup analysis
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# | | |
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# 3 2 1
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# |
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# \____ Edge used for hold = 3
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#
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# Maximum path delay = 16 ns
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# Setup analysis can be shifted from edge #4 to edge #5 by
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# subtracting a clock period from the maximum delay.
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@define $lo_spi_input_max_delay 16.000 - $prc_clock_period ;
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# For hold analysis, we conservatively set the minimum delay of the
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# MUXOUT path to 0.
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@define $lo_spi_input_min_delay 0.000 ;
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INPUT_SETUP GROUP LO_SPI_INPUT_PORTS INPUT_DELAY $lo_spi_input_max_delay ns
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HOLD $lo_spi_input_min_delay ns
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CLKPORT "CPLD_REFCLK";
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# Add very loose timing requirements for clocks
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CLOCK_TO_OUT GROUP LO_SPI_CLKS OUTPUT_DELAY $generic_ext_flop_tsu ns
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MIN $generic_ext_flop_th ns
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CLKPORT "CPLD_REFCLK" ;
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#####################################################################
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# Clock Shift paths
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#####################################################################
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# pll_ref_clk_adjusted flip-flops will show hold violations from pll_ref_clk signals
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# as Diamond fails to recognize the proper edges to use for the timing analysis.
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# A multi-cycle constraint is used to analyze against the previous ref_clk cycle.
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#
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# *Launch Edge(with adjustments)
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# |
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# | * Launch edge(according to Diamond)
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# | |
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# | |
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# ref_clk __/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\
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# shifted clk ----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\____
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# |
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# |
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# Capture edge
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MULTICYCLE FROM CLKNET "pll_ref_clk" TO CLKNET "pll_ref_clk_adjusted" 0 X;
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######################################################################################
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# Pin Location Information
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######################################################################################
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LOCATE COMP "TX0_SW3_B" SITE "B1" ;
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LOCATE COMP "MB_FPGA_GPIO[1]" SITE "D3" ;
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LOCATE COMP "MB_CTRL_CS" SITE "D1" ;
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LOCATE COMP "MB_CTRL_MOSI" SITE "E2" ;
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LOCATE COMP "MB_FPGA_GPIO[12]" SITE "E3" ;
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LOCATE COMP "MB_FPGA_GPIO[9]" SITE "C1" ;
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LOCATE COMP "MB_FPGA_GPIO[10]" SITE "D2" ;
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LOCATE COMP "MB_CTRL_SCK" SITE "E1" ;
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LOCATE COMP "MB_FPGA_GPIO[13]" SITE "F2" ;
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LOCATE COMP "MB_FPGA_GPIO[2]" SITE "F4" ;
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LOCATE COMP "MB_FPGA_GPIO[0]" SITE "G6" ;
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LOCATE COMP "MB_FPGA_GPIO[5]" SITE "F3" ;
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LOCATE COMP "MB_FPGA_GPIO[6]" SITE "F1" ;
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LOCATE COMP "MB_FPGA_GPIO[4]" SITE "G5" ;
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LOCATE COMP "MB_CTRL_MISO" SITE "G4" ;
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LOCATE COMP "MB_FPGA_GPIO[8]" SITE "G2" ;
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LOCATE COMP "MB_FPGA_GPIO[7]" SITE "G3" ;
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LOCATE COMP "MB_FPGA_GPIO[11]" SITE "F5" ;
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LOCATE COMP "MB_FPGA_GPIO[3]" SITE "H6" ;
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LOCATE COMP "TX1_SW3_A" SITE "G1" ;
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LOCATE COMP "TX0_SW6_A" SITE "H2" ;
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LOCATE COMP "TX0_SW4_B" SITE "H4" ;
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LOCATE COMP "TX1_SW3_B" SITE "H3" ;
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LOCATE COMP "TX0_SW6_B" SITE "J6" ;
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LOCATE COMP "TX1_SW6_B" SITE "H1" ;
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LOCATE COMP "MB_SYNTH_SYNC" SITE "J1" ;
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LOCATE COMP "TX1_SW6_A" SITE "J3" ;
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LOCATE COMP "TX0_SW4_A" SITE "J2" ;
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LOCATE COMP "TX0_SW3_A" SITE "H5" ;
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LOCATE COMP "TX1_SW4_B" SITE "K1" ;
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LOCATE COMP "TX1_SW4_A" SITE "J4" ;
|
|
LOCATE COMP "TX0_SW5_B" SITE "K3" ;
|
|
LOCATE COMP "CTRL_REG_ARST" SITE "K2" ;
|
|
LOCATE COMP "TX0_SW5_A" SITE "J5" ;
|
|
LOCATE COMP "RX1_SW11_V3" SITE "L1" ;
|
|
LOCATE COMP "RX0_DSA1_n[3]" SITE "L3" ;
|
|
LOCATE COMP "RX0_SW11_V3" SITE "K4" ;
|
|
LOCATE COMP "RX0_DSA1_n[1]" SITE "L5" ;
|
|
LOCATE COMP "RX0_DSA1_n[2]" SITE "L2" ;
|
|
LOCATE COMP "TX1_SW5_B" SITE "M1" ;
|
|
LOCATE COMP "CH1_TX_LED" SITE "K5" ;
|
|
LOCATE COMP "TX1_DSA2[2]" SITE "L4" ;
|
|
LOCATE COMP "RX1_DSA2_n[4]" SITE "N2" ;
|
|
LOCATE COMP "RX1_DSA3_B_n[4]" SITE "P1" ;
|
|
LOCATE COMP "RX0_SW5_A" SITE "M3" ;
|
|
LOCATE COMP "TX1_SW5_A" SITE "N1" ;
|
|
LOCATE COMP "RX0_DSA1_n[4]" SITE "M2" ;
|
|
LOCATE COMP "RX1_DSA2_n[3]" SITE "N3" ;
|
|
LOCATE COMP "RX0_DSA3_B_n[1]" SITE "R1" ;
|
|
LOCATE COMP "RX0_DSA2_n[1]" SITE "P2" ;
|
|
LOCATE COMP "RX0_DSA2_n[3]" SITE "P4" ;
|
|
LOCATE COMP "RX0_DSA3_B_n[3]" SITE "T4" ;
|
|
LOCATE COMP "RX1_DSA3_B_n[3]" SITE "T2" ;
|
|
LOCATE COMP "RX0_DSA3_B_n[2]" SITE "R3" ;
|
|
LOCATE COMP "RX0_DSA2_n[4]" SITE "R5" ;
|
|
LOCATE COMP "RX1_DSA1_n[3]" SITE "P5" ;
|
|
LOCATE COMP "RX1_DSA3_B_n[2]" SITE "T3" ;
|
|
LOCATE COMP "RX1_DSA3_B_n[1]" SITE "R4" ;
|
|
LOCATE COMP "RX0_DSA3_B_n[4]" SITE "T5" ;
|
|
LOCATE COMP "TX0_SW10_A" SITE "R6" ;
|
|
LOCATE COMP "RX1_DSA2_n[1]" SITE "P6" ;
|
|
LOCATE COMP "TX0_SW10_B" SITE "T6" ;
|
|
LOCATE COMP "RX1_DSA1_n[2]" SITE "N6" ;
|
|
LOCATE COMP "RX1_SW4_A" SITE "L7" ;
|
|
LOCATE COMP "RX0_SW1_A" SITE "R7" ;
|
|
LOCATE COMP "RX0_SW2_A" SITE "P7" ;
|
|
LOCATE COMP "RX1_SW5_B" SITE "M7" ;
|
|
LOCATE COMP "RX0_DSA2_n[2]" SITE "N7" ;
|
|
LOCATE COMP "RX0_SW5_B" SITE "M6" ;
|
|
LOCATE COMP "CH1_RX_LED" SITE "L8" ;
|
|
LOCATE COMP "RX0_SW1_B" SITE "T7" ;
|
|
LOCATE COMP "RX1_SW6_A" SITE "R8" ;
|
|
LOCATE COMP "RX1_SW2_A" SITE "P8" ;
|
|
LOCATE COMP "RX1_SW6_B" SITE "T8" ;
|
|
LOCATE COMP "RX1_DSA1_n[1]" SITE "N8" ;
|
|
LOCATE COMP "TX1_DSA2[5]" SITE "L9" ;
|
|
LOCATE COMP "RX1_DSA2_n[2]" SITE "M8" ;
|
|
LOCATE COMP "RX0_SW11_V1" SITE "N9" ;
|
|
LOCATE COMP "RX0_SW6_B" SITE "T9" ;
|
|
LOCATE COMP "RX1_SW11_V2" SITE "P9" ;
|
|
LOCATE COMP "RX1_SW3_V1" SITE "R9" ;
|
|
LOCATE COMP "RX0_SW6_A" SITE "T10" ;
|
|
LOCATE COMP "RX1_DSA1_n[4]" SITE "M9" ;
|
|
LOCATE COMP "RX1_SW5_A" SITE "L10" ;
|
|
LOCATE COMP "RX0_SW10_V1" SITE "P10" ;
|
|
LOCATE COMP "RX0_SW3_V3" SITE "R10" ;
|
|
LOCATE COMP "RX1_SW10_V1" SITE "N10" ;
|
|
LOCATE COMP "RX0_DSA3_A_n[1]" SITE "M11" ;
|
|
LOCATE COMP "TX0_SW11_B" SITE "T11" ;
|
|
LOCATE COMP "RX1_LO2_MUXOUT" SITE "P11" ;
|
|
LOCATE COMP "CH0_RX2_LED" SITE "M10" ;
|
|
LOCATE COMP "CH0_TX_LED" SITE "N11" ;
|
|
LOCATE COMP "RX0_LO1_MUXOUT" SITE "R13" ;
|
|
LOCATE COMP "RX1_SW3_V2" SITE "T14" ;
|
|
LOCATE COMP "CH0_RX_LED" SITE "R11" ;
|
|
LOCATE COMP "TX0_SW11_A" SITE "T12" ;
|
|
LOCATE COMP "RX0_LO2_MUXOUT" SITE "P12" ;
|
|
LOCATE COMP "RX0_SW3_V1" SITE "T13" ;
|
|
LOCATE COMP "RX1_SW11_V1" SITE "T15" ;
|
|
LOCATE COMP "RX1_SW3_V3" SITE "R14" ;
|
|
LOCATE COMP "RX0_SW11_V2" SITE "R16" ;
|
|
LOCATE COMP "RX0_DSA3_A_n[2]" SITE "P15" ;
|
|
LOCATE COMP "RX0_SW9_V1" SITE "N14" ;
|
|
LOCATE COMP "P7V_PG_A" SITE "N16" ;
|
|
LOCATE COMP "P7V_ENABLE_B" SITE "P16" ;
|
|
LOCATE COMP "P7V_ENABLE_A" SITE "M15" ;
|
|
LOCATE COMP "P3D3VA_ENABLE" SITE "N15" ;
|
|
LOCATE COMP "RX1_LO1_MUXOUT" SITE "M14" ;
|
|
LOCATE COMP "RX1_SW9_V1" SITE "L13" ;
|
|
LOCATE COMP "P7V_PG_B" SITE "M16" ;
|
|
LOCATE COMP "RX0_SW4_A" SITE "K11" ;
|
|
LOCATE COMP "RX0_DSA3_A_n[4]" SITE "L15" ;
|
|
LOCATE COMP "RX1_DSA3_A_n[1]" SITE "K12" ;
|
|
LOCATE COMP "RX0_DSA3_A_n[3]" SITE "L14" ;
|
|
LOCATE COMP "RX1_DSA3_A_n[2]" SITE "K13" ;
|
|
LOCATE COMP "RX1_LO2_SYNC" SITE "L16" ;
|
|
LOCATE COMP "RX0_SW3_V2" SITE "L12" ;
|
|
LOCATE COMP "RX1_LO2_SCK" SITE "K15" ;
|
|
LOCATE COMP "RX0_LO2_CSB" SITE "J11" ;
|
|
LOCATE COMP "RX1_DSA3_A_n[3]" SITE "K14" ;
|
|
LOCATE COMP "RX1_DSA3_A_n[4]" SITE "J13" ;
|
|
LOCATE COMP "RX0_LO2_SYNC" SITE "K16" ;
|
|
LOCATE COMP "TX1_LO1_CSB" SITE "H11" ;
|
|
LOCATE COMP "RX1_LO1_SCK" SITE "J15" ;
|
|
LOCATE COMP "TX1_LO2_SYNC" SITE "J14" ;
|
|
LOCATE COMP "RX0_LO1_SCK" SITE "J16" ;
|
|
LOCATE COMP "RX1_LO1_SYNC" SITE "H16" ;
|
|
LOCATE COMP "RX0_LO2_SCK" SITE "J12" ;
|
|
LOCATE COMP "CPLD_REFCLK" SITE "H14" ;
|
|
LOCATE COMP "RX1_LO2_CSB" SITE "H13" ;
|
|
LOCATE COMP "RX0_LO1_SYNC" SITE "H15" ;
|
|
LOCATE COMP "RX0_LO1_CSB" SITE "G16" ;
|
|
LOCATE COMP "TX0_LO1_SCK" SITE "H12" ;
|
|
LOCATE COMP "TX1_LO2_SCK" SITE "G14" ;
|
|
LOCATE COMP "TX1_DSA2[4]" SITE "G11" ;
|
|
LOCATE COMP "TX0_LO2_SCK" SITE "G15" ;
|
|
LOCATE COMP "RX1_LO1_CSB" SITE "G13" ;
|
|
LOCATE COMP "TX0_LO2_CSB" SITE "F16" ;
|
|
LOCATE COMP "RX1_SW7_SW8_CTRL" SITE "F12" ;
|
|
LOCATE COMP "TX0_LO1_SYNC" SITE "F14" ;
|
|
LOCATE COMP "TX0_LO2_MUXOUT" SITE "G12" ;
|
|
LOCATE COMP "RX_TX_LO_SDI" SITE "F15" ;
|
|
LOCATE COMP "TX0_DSA1[3]" SITE "F13" ;
|
|
LOCATE COMP "TX1_LO2_CSB" SITE "E16" ;
|
|
LOCATE COMP "TX0_DSA1[6]" SITE "D15" ;
|
|
LOCATE COMP "TX1_LO1_SYNC" SITE "C16" ;
|
|
LOCATE COMP "TX1_LO1_SCK" SITE "E14" ;
|
|
LOCATE COMP "TX0_LO1_CSB" SITE "D16" ;
|
|
LOCATE COMP "TX1_DSA1[4]" SITE "B16" ;
|
|
LOCATE COMP "TX0_LO2_SYNC" SITE "E15" ;
|
|
LOCATE COMP "TX1_SW1_SW2_CTRL" SITE "C15" ;
|
|
LOCATE COMP "TX1_DSA1[3]" SITE "D14" ;
|
|
LOCATE COMP "TX1_DSA1[5]" SITE "A15" ;
|
|
LOCATE COMP "TX1_DSA1[6]" SITE "B14" ;
|
|
LOCATE COMP "TX1_LO2_MUXOUT" SITE "B12" ;
|
|
LOCATE COMP "TX1_DSA1[2]" SITE "C12" ;
|
|
LOCATE COMP "TX0_DSA1[4]" SITE "A14" ;
|
|
LOCATE COMP "TX0_DSA1[5]" SITE "B13" ;
|
|
LOCATE COMP "TX0_SW1_SW2_CTRL" SITE "A12" ;
|
|
LOCATE COMP "TX0_SW14_V1" SITE "B11" ;
|
|
LOCATE COMP "RX0_SW7_SW8_CTRL" SITE "D11" ;
|
|
LOCATE COMP "TX0_DSA1[2]" SITE "C11" ;
|
|
LOCATE COMP "TX1_DSA2[3]" SITE "F10" ;
|
|
LOCATE COMP "CH1_RX2_LED" SITE "A11" ;
|
|
LOCATE COMP "TX0_DSA2[5]" SITE "E10" ;
|
|
LOCATE COMP "TX1_LO1_MUXOUT" SITE "D10" ;
|
|
LOCATE COMP "TX0_SW13_V1" SITE "E11" ;
|
|
LOCATE COMP "TX1_DSA2[6]" SITE "F9" ;
|
|
LOCATE COMP "TX1_SW13_V1" SITE "A10" ;
|
|
LOCATE COMP "TX1_SW14_V1" SITE "B9" ;
|
|
LOCATE COMP "TX0_SW8_V1" SITE "D9" ;
|
|
LOCATE COMP "TX1_SW8_V1" SITE "C9" ;
|
|
LOCATE COMP "TX1_SW10_A" SITE "F8" ;
|
|
LOCATE COMP "TX0_LO1_MUXOUT" SITE "A9" ;
|
|
LOCATE COMP "RX1_SW1_B" SITE "E9" ;
|
|
LOCATE COMP "TX1_SW8_V2" SITE "D8" ;
|
|
LOCATE COMP "TX1_SW8_V3" SITE "A8" ;
|
|
LOCATE COMP "TX0_SW8_V2" SITE "C8" ;
|
|
LOCATE COMP "RX1_SW1_A" SITE "E8" ;
|
|
LOCATE COMP "TX1_SW11_B" SITE "F7" ;
|
|
LOCATE COMP "TX1_SW11_A" SITE "D7" ;
|
|
LOCATE COMP "TX0_DSA2[3]" SITE "C7" ;
|
|
LOCATE COMP "TX0_SW7_B" SITE "E6" ;
|
|
LOCATE COMP "TX1_SW9_B" SITE "B7" ;
|
|
LOCATE COMP "TX1_SW10_B" SITE "E7" ;
|
|
LOCATE COMP "TX0_DSA2[4]" SITE "D6" ;
|
|
LOCATE COMP "TX0_DSA2[6]" SITE "B4" ;
|
|
LOCATE COMP "TX0_DSA2[2]" SITE "A3" ;
|
|
LOCATE COMP "TX0_SW8_V3" SITE "B6" ;
|
|
LOCATE COMP "TX0_SW9_A" SITE "A5" ;
|
|
LOCATE COMP "TX1_SW7_B" SITE "C5" ;
|
|
LOCATE COMP "TX0_SW9_B" SITE "A4" ;
|
|
LOCATE COMP "TX1_SW9_A" SITE "B5" ;
|
|
LOCATE COMP "TX1_SW7_A" SITE "B3" ;
|
|
LOCATE COMP "TX0_SW7_A" SITE "C4" ;
|
|
|
|
|
|
######################################################################################
|
|
# Bank Voltage Information
|
|
######################################################################################
|
|
BANK 5 VCCIO 1.8 V;
|
|
BANK 4 VCCIO 1.8 V;
|
|
BANK 3 VCCIO 3.3 V;
|
|
BANK 2 VCCIO 3.3 V;
|
|
BANK 1 VCCIO 3.3 V;
|
|
BANK 0 VCCIO 3.3 V;
|
|
|
|
|
|
######################################################################################
|
|
# Pin Drive information
|
|
######################################################################################
|
|
#Below is a starting point for Drive strength selection, each designer must decide what drive strength is appropriate for their design
|
|
#HYSTERSIS is not specified for all inputs and assume default value, they may be turned on as follows SMALL and LARGE are available options, assuming you want LVCMOS25
|
|
#IOBUF PORT "SigName" IO_TYPE=LVCMOS25 PULLMODE=NONE CLAMP=OFF HYSTERESIS=SMALL ;
|
|
|
|
#CLAMP=OFF set to all pins, may be changed as desired.
|
|
#Drive set to 8mA SLOW for all pins, may be changed as desired. In future could have tool auto determine best drive, but for now defaults to 8mA slow
|
|
|
|
|
|
IOBUF PORT "TX0_SW3_B" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "MB_FPGA_GPIO[1]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "MB_CTRL_CS" IO_TYPE=LVCMOS18 PULLMODE=NONE CLAMP=OFF ;
|
|
IOBUF PORT "MB_CTRL_MOSI" IO_TYPE=LVCMOS18 PULLMODE=NONE CLAMP=OFF ;
|
|
IOBUF PORT "MB_FPGA_GPIO[12]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "MB_FPGA_GPIO[9]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "MB_FPGA_GPIO[10]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "MB_CTRL_SCK" IO_TYPE=LVCMOS18 PULLMODE=NONE CLAMP=OFF ;
|
|
IOBUF PORT "MB_FPGA_GPIO[13]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "MB_FPGA_GPIO[2]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "MB_FPGA_GPIO[0]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "MB_FPGA_GPIO[5]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "MB_FPGA_GPIO[6]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "MB_FPGA_GPIO[4]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "MB_CTRL_MISO" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "MB_FPGA_GPIO[8]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "MB_FPGA_GPIO[7]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "MB_FPGA_GPIO[11]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "MB_FPGA_GPIO[3]" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_SW3_A" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_SW6_A" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_SW4_B" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_SW3_B" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_SW6_B" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_SW6_B" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "MB_SYNTH_SYNC" IO_TYPE=LVCMOS18 PULLMODE=NONE CLAMP=OFF ;
|
|
IOBUF PORT "TX1_SW6_A" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_SW4_A" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_SW3_A" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_SW4_B" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_SW4_A" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_SW5_B" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "CTRL_REG_ARST" IO_TYPE=LVCMOS18 PULLMODE=NONE CLAMP=OFF ;
|
|
IOBUF PORT "TX0_SW5_A" IO_TYPE=LVCMOS18 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "RX1_SW11_V3" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "RX0_DSA1_n[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "RX0_SW11_V3" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "RX0_DSA1_n[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "RX0_DSA1_n[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_SW5_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "CH1_TX_LED" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_DSA2[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "RX1_DSA2_n[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "RX1_DSA3_B_n[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "RX0_SW5_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_SW5_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "RX0_DSA1_n[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "RX1_DSA2_n[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "RX0_DSA3_B_n[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "RX0_DSA2_n[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "RX0_DSA2_n[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "RX0_DSA3_B_n[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "RX1_DSA3_B_n[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "RX0_DSA3_B_n[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "RX0_DSA2_n[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "RX1_DSA1_n[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "RX1_DSA3_B_n[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "RX1_DSA3_B_n[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "RX0_DSA3_B_n[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_SW10_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "RX1_DSA2_n[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_SW10_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "RX1_DSA1_n[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "RX1_SW4_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX0_SW1_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX0_SW2_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX1_SW5_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX0_DSA2_n[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX0_SW5_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "CH1_RX_LED" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX0_SW1_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX1_SW6_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX1_SW2_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX1_SW6_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX1_DSA1_n[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "TX1_DSA2[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX1_DSA2_n[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX0_SW11_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX0_SW6_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX1_SW11_V2" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX1_SW3_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX0_SW6_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX1_DSA1_n[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX1_SW5_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX0_SW10_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX0_SW3_V3" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX1_SW10_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX0_DSA3_A_n[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "TX0_SW11_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX1_LO2_MUXOUT" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ;
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IOBUF PORT "CH0_RX2_LED" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "CH0_TX_LED" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX0_LO1_MUXOUT" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ;
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IOBUF PORT "RX1_SW3_V2" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "CH0_RX_LED" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "TX0_SW11_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX0_LO2_MUXOUT" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ;
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IOBUF PORT "RX0_SW3_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX1_SW11_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX1_SW3_V3" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX0_SW11_V2" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX0_DSA3_A_n[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX0_SW9_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "P7V_PG_A" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ;
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IOBUF PORT "P7V_ENABLE_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "P7V_ENABLE_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "P3D3VA_ENABLE" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX1_LO1_MUXOUT" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ;
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IOBUF PORT "RX1_SW9_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "P7V_PG_B" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ;
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IOBUF PORT "RX0_SW4_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX0_DSA3_A_n[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX1_DSA3_A_n[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX0_DSA3_A_n[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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|
IOBUF PORT "RX1_DSA3_A_n[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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IOBUF PORT "RX1_LO2_SYNC" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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|
IOBUF PORT "RX0_SW3_V2" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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|
IOBUF PORT "RX1_LO2_SCK" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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|
IOBUF PORT "RX0_LO2_CSB" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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|
IOBUF PORT "RX1_DSA3_A_n[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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|
IOBUF PORT "RX1_DSA3_A_n[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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|
IOBUF PORT "RX0_LO2_SYNC" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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|
IOBUF PORT "TX1_LO1_CSB" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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|
IOBUF PORT "RX1_LO1_SCK" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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|
IOBUF PORT "TX1_LO2_SYNC" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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|
IOBUF PORT "RX0_LO1_SCK" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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|
IOBUF PORT "RX1_LO1_SYNC" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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|
IOBUF PORT "RX0_LO2_SCK" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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|
IOBUF PORT "CPLD_REFCLK" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ;
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|
IOBUF PORT "RX1_LO2_CSB" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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|
IOBUF PORT "RX0_LO1_SYNC" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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|
IOBUF PORT "RX0_LO1_CSB" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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|
IOBUF PORT "TX0_LO1_SCK" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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|
IOBUF PORT "TX1_LO2_SCK" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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|
IOBUF PORT "TX1_DSA2[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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|
IOBUF PORT "TX0_LO2_SCK" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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|
IOBUF PORT "RX1_LO1_CSB" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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|
IOBUF PORT "TX0_LO2_CSB" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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|
IOBUF PORT "RX1_SW7_SW8_CTRL" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_LO1_SYNC" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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|
IOBUF PORT "TX0_LO2_MUXOUT" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ;
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|
IOBUF PORT "RX_TX_LO_SDI" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=16 SLEWRATE=FAST CLAMP=OFF ;
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|
IOBUF PORT "TX0_DSA1[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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|
IOBUF PORT "TX1_LO2_CSB" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
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|
IOBUF PORT "TX0_DSA1[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_LO1_SYNC" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_LO1_SCK" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_LO1_CSB" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_DSA1[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_LO2_SYNC" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_SW1_SW2_CTRL" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_DSA1[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_DSA1[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_DSA1[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_LO2_MUXOUT" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ;
|
|
IOBUF PORT "TX1_DSA1[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_DSA1[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_DSA1[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_SW1_SW2_CTRL" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_SW14_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "RX0_SW7_SW8_CTRL" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_DSA1[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_DSA2[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "CH1_RX2_LED" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_DSA2[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_LO1_MUXOUT" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ;
|
|
IOBUF PORT "TX0_SW13_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_DSA2[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_SW13_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_SW14_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_SW8_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_SW8_V1" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_SW10_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_LO1_MUXOUT" IO_TYPE=LVCMOS33 PULLMODE=NONE CLAMP=OFF ;
|
|
IOBUF PORT "RX1_SW1_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_SW8_V2" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_SW8_V3" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_SW8_V2" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "RX1_SW1_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_SW11_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_SW11_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_DSA2[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_SW7_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_SW9_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_SW10_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_DSA2[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_DSA2[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_DSA2[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_SW8_V3" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_SW9_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_SW7_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_SW9_B" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_SW9_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX1_SW7_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|
|
IOBUF PORT "TX0_SW7_A" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW CLAMP=OFF ;
|