fpga: x400: sim: Add 10 GbE with wide CHDR
Adds simulation coverage for 10 GbE with 512-bit CHDR bus. Original-commit: 0e50a37b5ec6039ed4e8947421dd333047e24408
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@@ -28,6 +28,13 @@ module x4xx_qsfp_wrapper_all_tb;
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.USE_MAC (0)
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.USE_MAC (0)
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) ETH_10Gb_fast ();
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) ETH_10Gb_fast ();
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x4xx_qsfp_wrapper_tb #(
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.TEST_NAME ("10GbE_F_512"),
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.PROTOCOL0 (`MGT_10GbE),
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.CHDR_W (512),
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.USE_MAC (0)
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) ETH_10Gb_fast_512 ();
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x4xx_qsfp_wrapper_tb #(
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x4xx_qsfp_wrapper_tb #(
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.TEST_NAME ("10GbE_x4_F"),
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.TEST_NAME ("10GbE_x4_F"),
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.PROTOCOL0 (`MGT_10GbE),
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.PROTOCOL0 (`MGT_10GbE),
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@@ -67,6 +74,7 @@ module x4xx_qsfp_wrapper_all_tb;
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always_ff@(posedge clk) begin
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always_ff@(posedge clk) begin
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if (ETH_100Gb_fast.test.done &&
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if (ETH_100Gb_fast.test.done &&
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ETH_10Gb_fast.test.done &&
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ETH_10Gb_fast.test.done &&
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ETH_10Gb_fast_512.test.done &&
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ETH_10Gb_x4_fast.test.done &&
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ETH_10Gb_x4_fast.test.done &&
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ETH_100Gb_512serial.test.done &&
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ETH_100Gb_512serial.test.done &&
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ETH_100Gb_128serial.test.done &&
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ETH_100Gb_128serial.test.done &&
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