From a405111ce7e91a359fe559840ede677880344b8f Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Sat, 10 Jun 2023 15:55:18 -0500 Subject: [PATCH] fpga: x400: sim: Add 10 GbE with wide CHDR Adds simulation coverage for 10 GbE with 512-bit CHDR bus. Original-commit: 0e50a37b5ec6039ed4e8947421dd333047e24408 --- .../sim/x4xx_qsfp_wrapper/x4xx_qsfp_wrapper_all_tb.sv | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/top/x400/sim/x4xx_qsfp_wrapper/x4xx_qsfp_wrapper_all_tb.sv b/top/x400/sim/x4xx_qsfp_wrapper/x4xx_qsfp_wrapper_all_tb.sv index 2357d7c..d2420e7 100644 --- a/top/x400/sim/x4xx_qsfp_wrapper/x4xx_qsfp_wrapper_all_tb.sv +++ b/top/x400/sim/x4xx_qsfp_wrapper/x4xx_qsfp_wrapper_all_tb.sv @@ -28,6 +28,13 @@ module x4xx_qsfp_wrapper_all_tb; .USE_MAC (0) ) ETH_10Gb_fast (); + x4xx_qsfp_wrapper_tb #( + .TEST_NAME ("10GbE_F_512"), + .PROTOCOL0 (`MGT_10GbE), + .CHDR_W (512), + .USE_MAC (0) + ) ETH_10Gb_fast_512 (); + x4xx_qsfp_wrapper_tb #( .TEST_NAME ("10GbE_x4_F"), .PROTOCOL0 (`MGT_10GbE), @@ -67,6 +74,7 @@ module x4xx_qsfp_wrapper_all_tb; always_ff@(posedge clk) begin if (ETH_100Gb_fast.test.done && ETH_10Gb_fast.test.done && + ETH_10Gb_fast_512.test.done && ETH_10Gb_x4_fast.test.done && ETH_100Gb_512serial.test.done && ETH_100Gb_128serial.test.done &&