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fpga: tools: Add contents of directories for HDL source

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For HLS builds, the output file names aren't known in advance. This
makes it difficult to write the Makefile to pull in the files and pass
them to the build tools. This change allows you to add a directory as
your HDL source so that all files in the directory will be pulled in by
the build process.


Original-commit: 90933d9b2faf392fd26f3f7ca32f73719614a40a
This commit is contained in:
Wade Fife
2020-05-26 13:36:55 -05:00
parent af2aeccdc8
commit 98463e99d0
3 changed files with 26 additions and 5 deletions
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tools/make/viv_hls_ip_builder.mak
+1 -1
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@@ -4,7 +4,7 @@
# -------------------------------------------------------------------
# Usage: BUILD_VIVADO_HLS_IP
# Args: $1 = HLS_IP_NAME (High level synthsis IP name)
# Args: $1 = HLS_IP_NAME (High level synthesis IP name)
# $2 = PART_ID (<device>/<package>/<speedgrade>)
# $3 = HLS_IP_SRCS (Absolute paths to the HLS IP source files)
# $4 = HLS_IP_SRC_DIR (Absolute path to the top level HLS IP src dir)