From 98463e99d0a0a96deb7479550f38142114e7c010 Mon Sep 17 00:00:00 2001
From: Wade Fife <wade.fife@ettus.com>
Date: Fri, 15 May 2020 14:04:38 -0500
Subject: [PATCH] fpga: tools: Add contents of directories for HDL source

For HLS builds, the output file names aren't known in advance. This
makes it difficult to write the Makefile to pull in the files and pass
them to the build tools. This change allows you to add a directory as
your HDL source so that all files in the directory will be pulled in by
the build process.


Original-commit: 90933d9b2faf392fd26f3f7ca32f73719614a40a
---
 tools/make/viv_hls_ip_builder.mak |  2 +-
 tools/scripts/viv_sim_project.tcl | 20 ++++++++++++++++----
 tools/scripts/viv_utils.tcl       |  9 +++++++++
 3 files changed, 26 insertions(+), 5 deletions(-)

diff --git a/tools/make/viv_hls_ip_builder.mak b/tools/make/viv_hls_ip_builder.mak
index 77f0915..10c5a83 100644
--- a/tools/make/viv_hls_ip_builder.mak
+++ b/tools/make/viv_hls_ip_builder.mak
@@ -4,7 +4,7 @@
 
 # -------------------------------------------------------------------
 # Usage: BUILD_VIVADO_HLS_IP
-# Args: $1 = HLS_IP_NAME (High level synthsis IP name)
+# Args: $1 = HLS_IP_NAME (High level synthesis IP name)
 #       $2 = PART_ID (<device>/<package>/<speedgrade>)
 #       $3 = HLS_IP_SRCS (Absolute paths to the HLS IP source files)
 #       $4 = HLS_IP_SRC_DIR (Absolute path to the top level HLS IP src dir)
diff --git a/tools/scripts/viv_sim_project.tcl b/tools/scripts/viv_sim_project.tcl
index b524e33..922c1ed 100644
--- a/tools/scripts/viv_sim_project.tcl
+++ b/tools/scripts/viv_sim_project.tcl
@@ -40,6 +40,15 @@ if [expr ([string equal $simulator "XSim"] == 0) && ([string length $sim_complib
 puts "BUILDER: Creating Vivado simulation project part $part_name"
 create_project -part $part_name -force $project_name/$project_name
 
+# Expand directories to include their contents (needed for HLS outputs)
+foreach src_file $design_srcs {
+    if [expr [file isdirectory $src_file] == 1] {
+        puts "BUILDER: Expanding Directory : $src_file"
+        set dir_contents [glob $src_file/*.*]
+        append design_srcs " " $dir_contents
+    }
+}
+
 foreach src_file $design_srcs {
     set src_ext [file extension $src_file ]
     if [expr [lsearch {.vhd .vhdl} $src_ext] >= 0] {
@@ -60,12 +69,15 @@ foreach src_file $design_srcs {
     } elseif [expr [lsearch {.ngc .edif} $src_ext] >= 0] {
         puts "BUILDER: Adding Netlist : $src_file"
         read_edif $src_file
+    } elseif [expr [lsearch {.dat} $src_ext] >= 0] {
+        puts "BUILDER: Adding Data File : $src_file"
+        add_files -fileset $sim_fileset -norecurse $src_file
     } elseif [expr [lsearch {.bd} $src_ext] >= 0] {
-            puts "BUILDER: Adding Block Diagram: $src_file"
-            add_files -norecurse $src_file
+        puts "BUILDER: Adding Block Diagram: $src_file"
+        add_files -norecurse $src_file
     } elseif [expr [lsearch {.bxml} $src_ext] >= 0] {
-            puts "BUILDER: Adding Block Diagram XML: $src_file"
-            add_files -norecurse $src_file
+        puts "BUILDER: Adding Block Diagram XML: $src_file"
+        add_files -norecurse $src_file
     } else {
         puts "BUILDER: \[WARNING\] File ignored!!!: $src_file"
     }
diff --git a/tools/scripts/viv_utils.tcl b/tools/scripts/viv_utils.tcl
index 8f34df6..9ced39e 100644
--- a/tools/scripts/viv_utils.tcl
+++ b/tools/scripts/viv_utils.tcl
@@ -59,6 +59,15 @@ proc ::vivado_utils::initialize_project { {save_to_disk 0} } {
         create_project -in_memory -part $g_part_name
     }
 
+    # Expand directories to include their contents (needed for HLS outputs)
+    foreach src_file $g_source_files {
+        if [expr [file isdirectory $src_file] == 1] {
+            puts "BUILDER: Expanding Directory : $src_file"
+            set dir_contents [glob $src_file/*.*]
+            append design_srcs " " $dir_contents
+        }
+    }
+
     foreach src_file $g_source_files {
         set src_ext [file extension $src_file ]
         if [expr [lsearch {.vhd .vhdl} $src_ext] >= 0] {