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utils: image builder: Major update

Browse Source 
Most important effect of this change: rfnoc_image_builder is now
required to build bitfiles, 'make' alone won't suffice any longer!

This is a huge changeset to the image builder that combines multiple new
features:

- There no longer is a separate edge file for the static router. The
  static routes are generated as a Verilog parameter directly into the
  rfnoc_core_kernel (which is also modified).
- image_builder.py is split up into several smaller files. Code is moved
  into yaml_utils.py, and the new files grc.py, builder_config.py
- Generic module support is added. Aside from noc blocks and stream
  endpoints, we can now instantiate arbitrary modules (they also require
  a YAML description file).
- To enable such modules, resets are now also tracked the same way that
  clock domains are.
- The ImageBuilderConfig config object now more closes matches the
  original YAML file. The attributes 'clk_domain_con' and 'block_con' are
  removed. Instead, the attributes 'connections' and 'clk_domains' are
  sanitized and amended with extra annotations. The templates are
  updated to reflect this change.
- IO ports can now carry parameters, e.g., to have variable wire widths
  based on the configuration.
- Many Pylint warnings were resolved.
- Add inheritance support for image core YAML files.
  This allows image core files to (recursively) inherit from other image
  core files. To do so, simply put an 'inherit' entry at the top of the
  file:
```yaml
inherit: 'x410_radio_base.yml'
```
- The inheritance feature is used as part of the image core files.
- Image core and DTS files are now generated as a build artefact into
  the build directory. This requires the usage of rfnoc_image_builder to
  build images. As a consequence, it is no longer required to check in
  image core Verilog files.
- As another consequence, rfnoc_image_builder is required to build
  bitfiles!
- Image flavours are no longer defined through Makefiles, but purely
  from the image core YAML files.
- Remove all image core YAML files that do not generate a shipping
  image. Because of the inheritance feature and the requirement to use
  the image builder, it is trivial to add new YAML files.
- Add support for transport adapters through the YAML files. Before,
  transport adapters were inferred from the make target (e.g.,
  X410_X4_200 would have four 10GbE links based on the 'X4' substring).
  Now, transport adapters are defined via the image core YAML.
- This feature is currently only used (or can be used) by the X4xx
  series. Older devices may or may not be ported to allow custom
  transport adapters in the future.
- Add parameters to the BSP YAMLs and the devices itself. This allows
  setting global parameters in the image core files. For example, the
  X4x0 devices use this to decide if they instantiate DRAM channels.
- DTS includes and constraint files can now be requested by
  blocks/transport adapter through their YAML files. They do no longer
  need to be listed in the Makefile.
- Support for secure image cores. These are image cores that allow
  incorporating RFNoC blocks that require license keys and thus can't
  live in an open-source environment. This solution adds the option for
  secure image cores without touching the open source feature set.
- Add --reuse option to allow manual editing of generated artefacts
- Allow IO signatures from any module: until now IO signatures had to be
  defined in a single file (io_signatures). This file will persist. In
  addition each module can add its own IO signature as with the same
  format the core IO signatures placed under the top level key
  `io_signatures`.  IO signatures are still maintained in a global
  dictionary. The consequence is that they can be shared among
  independent modules as well as they have to have a globally unique
  name. The image builder will warn about detected name clashes for the
  signatures.
- As a consequence, some less commonly used IO signatures were moved to
  their corresponding module YAML files.

Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Lars Amsel <lars.amsel@ni.com>


Original-commit: a98ce2621e2a2dc25535fc700b49bfcb00b8eb59
This commit is contained in:
Martin Braun
2024-06-11 10:20:07 +02:00
committed by Joerg Hofrichter
co-authored by Wade Fife Lars Amsel
parent 77d07a9714
commit 8669c68048
93 changed files with 1716 additions and 20268 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/n3xx/Makefile
+6 -6
View File
@@ -42,12 +42,12 @@ XQ_DEFS=SFP0_WR=1 QSFP_10GBE=1 BUILD_WR=1 BUILD_10G=1
AQ_DEFS=SFP0_10GBE=1 SFP1_10GBE=1 QSFP_AURORA=1 BUILD_10G=1 BUILD_AURORA=1 QSFP_LANES=4 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
# Defaults specific to the various targets:
N300_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n300_rfnoc_image_core.v) DEFAULT_EDGE_FILE=$(abspath n300_static_router.hex)
N310_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n310_rfnoc_image_core.v) DEFAULT_EDGE_FILE=$(abspath n310_static_router.hex)
N320_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n320_rfnoc_image_core.v) DEFAULT_EDGE_FILE=$(abspath n320_static_router.hex)
N300AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n300_bist_image_core.v) DEFAULT_EDGE_FILE=$(abspath n300_bist_static_router.hex)
N310AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n310_bist_image_core.v) DEFAULT_EDGE_FILE=$(abspath n310_bist_static_router.hex)
N320AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n320_bist_image_core.v) DEFAULT_EDGE_FILE=$(abspath n320_bist_static_router.hex)
N300_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n300_rfnoc_image_core.v)
N310_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n310_rfnoc_image_core.v)
N320_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n320_rfnoc_image_core.v)
N300AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n300_bist_image_core.v)
N310AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n310_bist_image_core.v)
N320AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n320_bist_image_core.v)
# Set build option (check RTL, run synthesis, or do a full build)
ifndef TARGET
top/n3xx/Makefile.n3xx.inc
+1 -3
View File
@@ -56,7 +56,6 @@ include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_replay/Makefile.srcs
-include $(RFNOC_OOT_MAKEFILE_SRCS)
IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE)
EDGE_FILE ?= $(DEFAULT_EDGE_FILE)
##################################################
# Sources
@@ -146,7 +145,6 @@ $(RFNOC_BLOCK_RADIO_SRCS) \
$(RFNOC_BLOCK_REPLAY_SRCS) \
$(AXI4S_SV_SRCS) $(RFNOC_XPORT_SV_SRCS) \
EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))"
IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))"
##################################################
@@ -154,7 +152,7 @@ IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))"
##################################################
.SECONDEXPANSION:
VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) $(IMAGE_CORE_DEF)
VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_DEF)
# DESIGN_SRCS and VERILOG_DEFS must be defined
bin: .prereqs
top/n3xx/n300_bist_rfnoc_image_core.v
+41 -33
View File
@@ -42,27 +42,27 @@ module rfnoc_image_core #(
// IO ports /////////////////////////
// ctrlport_radio0
output wire [ 0:0] m_ctrlport_radio0_req_wr,
output wire [ 0:0] m_ctrlport_radio0_req_rd,
output wire m_ctrlport_radio0_req_wr,
output wire m_ctrlport_radio0_req_rd,
output wire [ 19:0] m_ctrlport_radio0_req_addr,
output wire [ 31:0] m_ctrlport_radio0_req_data,
output wire [ 3:0] m_ctrlport_radio0_req_byte_en,
output wire [ 0:0] m_ctrlport_radio0_req_has_time,
output wire m_ctrlport_radio0_req_has_time,
output wire [ 63:0] m_ctrlport_radio0_req_time,
input wire [ 0:0] m_ctrlport_radio0_resp_ack,
input wire m_ctrlport_radio0_resp_ack,
input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 31:0] m_ctrlport_radio0_resp_data,
// time
input wire [ 63:0] radio_time,
// radio0
input wire [1023:0] radio_rx_data_radio0,
input wire [ 31:0] radio_rx_stb_radio0,
output wire [ 31:0] radio_rx_running_radio0,
output wire [1023:0] radio_tx_data_radio0,
input wire [ 31:0] radio_tx_stb_radio0,
output wire [ 31:0] radio_tx_running_radio0,
input wire [ 63:0] radio_rx_data_radio0,
input wire [ 1:0] radio_rx_stb_radio0,
output wire [ 1:0] radio_rx_running_radio0,
output wire [ 63:0] radio_tx_data_radio0,
input wire [ 1:0] radio_tx_stb_radio0,
output wire [ 1:0] radio_tx_running_radio0,
// dram
input wire [ 0:0] axi_rst,
input wire axi_rst,
output wire [ 7:0] m_axi_awid,
output wire [ 383:0] m_axi_awaddr,
output wire [ 63:0] m_axi_awlen,
@@ -139,7 +139,6 @@ module rfnoc_image_core #(
input wire m_dma_tready
);
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
@@ -577,7 +576,16 @@ module rfnoc_image_core #(
.NUM_TRANSPORTS (3),
.NUM_EDGES (8),
.CHDR_XBAR_PRESENT (1),
.EDGE_TBL_FILE (EDGE_TBL_FILE)
.EDGE_TBL ({
{10'd06, 6'd01, 10'd04, 6'd00},
{10'd04, 6'd00, 10'd06, 6'd01},
{10'd06, 6'd00, 10'd03, 6'd00},
{10'd03, 6'd00, 10'd06, 6'd00},
{10'd05, 6'd01, 10'd02, 6'd00},
{10'd02, 6'd00, 10'd05, 6'd01},
{10'd05, 6'd00, 10'd01, 6'd00},
{10'd01, 6'd00, 10'd05, 6'd00}
})
) core_kernel_i (
.chdr_aclk (chdr_aclk),
.chdr_aclk_locked (1'b1),
@@ -621,25 +629,25 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire radio0_m_ctrlport_req_wr;
wire radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire radio0_m_ctrlport_req_has_time;
wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
// time
wire [ 63:0] radio0_radio_time;
// radio
wire [1023:0] radio0_radio_rx_data;
wire [ 31:0] radio0_radio_rx_stb;
wire [ 31:0] radio0_radio_rx_running;
wire [1023:0] radio0_radio_tx_data;
wire [ 31:0] radio0_radio_tx_stb;
wire [ 31:0] radio0_radio_tx_running;
wire [32*1*2-1:0] radio0_radio_rx_data;
wire [ 1:0] radio0_radio_rx_stb;
wire [ 1:0] radio0_radio_rx_running;
wire [32*1*2-1:0] radio0_radio_tx_data;
wire [ 1:0] radio0_radio_tx_stb;
wire [ 1:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (2),
@@ -679,12 +687,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio0_out_1_tready, m_radio0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
);
@@ -704,7 +712,7 @@ module rfnoc_image_core #(
wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready;
// axi_ram
wire [ 0:0] fifo0_axi_rst;
wire fifo0_axi_rst;
wire [ 7:0] fifo0_m_axi_awid;
wire [ 383:0] fifo0_m_axi_awaddr;
wire [ 63:0] fifo0_m_axi_awlen;
@@ -821,12 +829,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_fifo0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_fifo0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_fifo0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_fifo0_ctrl_tready)
);
@@ -891,7 +899,7 @@ module rfnoc_image_core #(
//---------------------------------------------------------------------------
// Clock Domains
// Clock Domains and Resets
//---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk;
top/n3xx/n300_bist_static_router.hex
-9
View File
@@ -1,9 +0,0 @@
00000008
00400140
01400040
00800141
01410080
00c00180
018000c0
01000181
01810100
top/n3xx/n300_rfnoc_image_core.v
+55 -41
View File
@@ -42,27 +42,27 @@ module rfnoc_image_core #(
// IO ports /////////////////////////
// ctrlport_radio0
output wire [ 0:0] m_ctrlport_radio0_req_wr,
output wire [ 0:0] m_ctrlport_radio0_req_rd,
output wire m_ctrlport_radio0_req_wr,
output wire m_ctrlport_radio0_req_rd,
output wire [ 19:0] m_ctrlport_radio0_req_addr,
output wire [ 31:0] m_ctrlport_radio0_req_data,
output wire [ 3:0] m_ctrlport_radio0_req_byte_en,
output wire [ 0:0] m_ctrlport_radio0_req_has_time,
output wire m_ctrlport_radio0_req_has_time,
output wire [ 63:0] m_ctrlport_radio0_req_time,
input wire [ 0:0] m_ctrlport_radio0_resp_ack,
input wire m_ctrlport_radio0_resp_ack,
input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 31:0] m_ctrlport_radio0_resp_data,
// time
input wire [ 63:0] radio_time,
// radio0
input wire [1023:0] radio_rx_data_radio0,
input wire [ 31:0] radio_rx_stb_radio0,
output wire [ 31:0] radio_rx_running_radio0,
output wire [1023:0] radio_tx_data_radio0,
input wire [ 31:0] radio_tx_stb_radio0,
output wire [ 31:0] radio_tx_running_radio0,
input wire [ 63:0] radio_rx_data_radio0,
input wire [ 1:0] radio_rx_stb_radio0,
output wire [ 1:0] radio_rx_running_radio0,
output wire [ 63:0] radio_tx_data_radio0,
input wire [ 1:0] radio_tx_stb_radio0,
output wire [ 1:0] radio_tx_running_radio0,
// dram
input wire [ 0:0] axi_rst,
input wire axi_rst,
output wire [ 7:0] m_axi_awid,
output wire [ 383:0] m_axi_awaddr,
output wire [ 63:0] m_axi_awlen,
@@ -139,7 +139,6 @@ module rfnoc_image_core #(
input wire m_dma_tready
);
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
@@ -585,7 +584,20 @@ module rfnoc_image_core #(
.NUM_TRANSPORTS (3),
.NUM_EDGES (12),
.CHDR_XBAR_PRESENT (1),
.EDGE_TBL_FILE (EDGE_TBL_FILE)
.EDGE_TBL ({
{10'd08, 6'd01, 10'd04, 6'd00},
{10'd04, 6'd00, 10'd08, 6'd01},
{10'd08, 6'd00, 10'd03, 6'd00},
{10'd03, 6'd00, 10'd08, 6'd00},
{10'd06, 6'd01, 10'd02, 6'd00},
{10'd07, 6'd01, 10'd06, 6'd01},
{10'd05, 6'd01, 10'd07, 6'd01},
{10'd02, 6'd00, 10'd05, 6'd01},
{10'd06, 6'd00, 10'd01, 6'd00},
{10'd07, 6'd00, 10'd06, 6'd00},
{10'd05, 6'd00, 10'd07, 6'd00},
{10'd01, 6'd00, 10'd05, 6'd00}
})
) core_kernel_i (
.chdr_aclk (chdr_aclk),
.chdr_aclk_locked (1'b1),
@@ -628,6 +640,7 @@ module rfnoc_image_core #(
wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid;
wire m_duc0_out_1_tready, m_duc0_out_0_tready;
rfnoc_block_duc #(
.THIS_PORTID (2),
.CHDR_W (BLOCK_CHDR_W),
@@ -649,12 +662,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_duc0_out_1_tlast , m_duc0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_duc0_out_1_tvalid, m_duc0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_duc0_out_1_tready, m_duc0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_duc0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_duc0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_duc0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_duc0_ctrl_tready)
);
@@ -673,6 +686,7 @@ module rfnoc_image_core #(
wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid;
wire m_ddc0_out_1_tready, m_ddc0_out_0_tready;
rfnoc_block_ddc #(
.THIS_PORTID (3),
.CHDR_W (BLOCK_CHDR_W),
@@ -694,12 +708,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_ddc0_out_1_tlast , m_ddc0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_ddc0_out_1_tready, m_ddc0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_ddc0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_ddc0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_ddc0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_ddc0_ctrl_tready)
);
@@ -719,25 +733,25 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire radio0_m_ctrlport_req_wr;
wire radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire radio0_m_ctrlport_req_has_time;
wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
// time
wire [ 63:0] radio0_radio_time;
// radio
wire [1023:0] radio0_radio_rx_data;
wire [ 31:0] radio0_radio_rx_stb;
wire [ 31:0] radio0_radio_rx_running;
wire [1023:0] radio0_radio_tx_data;
wire [ 31:0] radio0_radio_tx_stb;
wire [ 31:0] radio0_radio_tx_running;
wire [32*1*2-1:0] radio0_radio_rx_data;
wire [ 1:0] radio0_radio_rx_stb;
wire [ 1:0] radio0_radio_rx_running;
wire [32*1*2-1:0] radio0_radio_tx_data;
wire [ 1:0] radio0_radio_tx_stb;
wire [ 1:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (4),
@@ -777,12 +791,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio0_out_1_tready, m_radio0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
);
@@ -802,7 +816,7 @@ module rfnoc_image_core #(
wire m_replay0_out_1_tready, m_replay0_out_0_tready;
// axi_ram
wire [ 0:0] replay0_axi_rst;
wire replay0_axi_rst;
wire [ 7:0] replay0_m_axi_awid;
wire [ 383:0] replay0_m_axi_awaddr;
wire [ 63:0] replay0_m_axi_awlen;
@@ -914,12 +928,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_replay0_out_1_tlast , m_replay0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_replay0_out_1_tready, m_replay0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_replay0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_replay0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_replay0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_replay0_ctrl_tready)
);
@@ -996,7 +1010,7 @@ module rfnoc_image_core #(
//---------------------------------------------------------------------------
// Clock Domains
// Clock Domains and Resets
//---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk;
top/n3xx/n300_static_router.hex
-13
View File
@@ -1,13 +0,0 @@
0000000C
00400140
014001c0
01c00180
01800040
00800141
014101c1
01c10181
01810080
00c00200
020000c0
01000201
02010100
top/n3xx/n310_bist_rfnoc_image_core.v
+69 -57
View File
@@ -42,45 +42,45 @@ module rfnoc_image_core #(
// IO ports /////////////////////////
// ctrlport_radio0
output wire [ 0:0] m_ctrlport_radio0_req_wr,
output wire [ 0:0] m_ctrlport_radio0_req_rd,
output wire m_ctrlport_radio0_req_wr,
output wire m_ctrlport_radio0_req_rd,
output wire [ 19:0] m_ctrlport_radio0_req_addr,
output wire [ 31:0] m_ctrlport_radio0_req_data,
output wire [ 3:0] m_ctrlport_radio0_req_byte_en,
output wire [ 0:0] m_ctrlport_radio0_req_has_time,
output wire m_ctrlport_radio0_req_has_time,
output wire [ 63:0] m_ctrlport_radio0_req_time,
input wire [ 0:0] m_ctrlport_radio0_resp_ack,
input wire m_ctrlport_radio0_resp_ack,
input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 31:0] m_ctrlport_radio0_resp_data,
// ctrlport_radio1
output wire [ 0:0] m_ctrlport_radio1_req_wr,
output wire [ 0:0] m_ctrlport_radio1_req_rd,
output wire m_ctrlport_radio1_req_wr,
output wire m_ctrlport_radio1_req_rd,
output wire [ 19:0] m_ctrlport_radio1_req_addr,
output wire [ 31:0] m_ctrlport_radio1_req_data,
output wire [ 3:0] m_ctrlport_radio1_req_byte_en,
output wire [ 0:0] m_ctrlport_radio1_req_has_time,
output wire m_ctrlport_radio1_req_has_time,
output wire [ 63:0] m_ctrlport_radio1_req_time,
input wire [ 0:0] m_ctrlport_radio1_resp_ack,
input wire m_ctrlport_radio1_resp_ack,
input wire [ 1:0] m_ctrlport_radio1_resp_status,
input wire [ 31:0] m_ctrlport_radio1_resp_data,
// time
input wire [ 63:0] radio_time,
// radio0
input wire [1023:0] radio_rx_data_radio0,
input wire [ 31:0] radio_rx_stb_radio0,
output wire [ 31:0] radio_rx_running_radio0,
output wire [1023:0] radio_tx_data_radio0,
input wire [ 31:0] radio_tx_stb_radio0,
output wire [ 31:0] radio_tx_running_radio0,
input wire [ 63:0] radio_rx_data_radio0,
input wire [ 1:0] radio_rx_stb_radio0,
output wire [ 1:0] radio_rx_running_radio0,
output wire [ 63:0] radio_tx_data_radio0,
input wire [ 1:0] radio_tx_stb_radio0,
output wire [ 1:0] radio_tx_running_radio0,
// radio1
input wire [1023:0] radio_rx_data_radio1,
input wire [ 31:0] radio_rx_stb_radio1,
output wire [ 31:0] radio_rx_running_radio1,
output wire [1023:0] radio_tx_data_radio1,
input wire [ 31:0] radio_tx_stb_radio1,
output wire [ 31:0] radio_tx_running_radio1,
input wire [ 63:0] radio_rx_data_radio1,
input wire [ 1:0] radio_rx_stb_radio1,
output wire [ 1:0] radio_rx_running_radio1,
output wire [ 63:0] radio_tx_data_radio1,
input wire [ 1:0] radio_tx_stb_radio1,
output wire [ 1:0] radio_tx_running_radio1,
// dram
input wire [ 0:0] axi_rst,
input wire axi_rst,
output wire [ 7:0] m_axi_awid,
output wire [ 383:0] m_axi_awaddr,
output wire [ 63:0] m_axi_awlen,
@@ -157,7 +157,6 @@ module rfnoc_image_core #(
input wire m_dma_tready
);
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
@@ -763,7 +762,20 @@ module rfnoc_image_core #(
.NUM_TRANSPORTS (3),
.NUM_EDGES (12),
.CHDR_XBAR_PRESENT (1),
.EDGE_TBL_FILE (EDGE_TBL_FILE)
.EDGE_TBL ({
{10'd09, 6'd01, 10'd06, 6'd00},
{10'd06, 6'd00, 10'd09, 6'd01},
{10'd09, 6'd00, 10'd05, 6'd00},
{10'd05, 6'd00, 10'd09, 6'd00},
{10'd08, 6'd01, 10'd04, 6'd00},
{10'd04, 6'd00, 10'd08, 6'd01},
{10'd08, 6'd00, 10'd03, 6'd00},
{10'd03, 6'd00, 10'd08, 6'd00},
{10'd07, 6'd01, 10'd02, 6'd00},
{10'd02, 6'd00, 10'd07, 6'd01},
{10'd07, 6'd00, 10'd01, 6'd00},
{10'd01, 6'd00, 10'd07, 6'd00}
})
) core_kernel_i (
.chdr_aclk (chdr_aclk),
.chdr_aclk_locked (1'b1),
@@ -807,25 +819,25 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire radio0_m_ctrlport_req_wr;
wire radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire radio0_m_ctrlport_req_has_time;
wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
// time
wire [ 63:0] radio0_radio_time;
// radio
wire [1023:0] radio0_radio_rx_data;
wire [ 31:0] radio0_radio_rx_stb;
wire [ 31:0] radio0_radio_rx_running;
wire [1023:0] radio0_radio_tx_data;
wire [ 31:0] radio0_radio_tx_stb;
wire [ 31:0] radio0_radio_tx_running;
wire [32*1*2-1:0] radio0_radio_rx_data;
wire [ 1:0] radio0_radio_rx_stb;
wire [ 1:0] radio0_radio_rx_running;
wire [32*1*2-1:0] radio0_radio_tx_data;
wire [ 1:0] radio0_radio_tx_stb;
wire [ 1:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (2),
@@ -865,12 +877,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio0_out_1_tready, m_radio0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
);
@@ -890,25 +902,25 @@ module rfnoc_image_core #(
wire m_radio1_out_1_tready, m_radio1_out_0_tready;
// ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr;
wire [ 0:0] radio1_m_ctrlport_req_rd;
wire radio1_m_ctrlport_req_wr;
wire radio1_m_ctrlport_req_rd;
wire [ 19:0] radio1_m_ctrlport_req_addr;
wire [ 31:0] radio1_m_ctrlport_req_data;
wire [ 3:0] radio1_m_ctrlport_req_byte_en;
wire [ 0:0] radio1_m_ctrlport_req_has_time;
wire radio1_m_ctrlport_req_has_time;
wire [ 63:0] radio1_m_ctrlport_req_time;
wire [ 0:0] radio1_m_ctrlport_resp_ack;
wire radio1_m_ctrlport_resp_ack;
wire [ 1:0] radio1_m_ctrlport_resp_status;
wire [ 31:0] radio1_m_ctrlport_resp_data;
// time
wire [ 63:0] radio1_radio_time;
// radio
wire [1023:0] radio1_radio_rx_data;
wire [ 31:0] radio1_radio_rx_stb;
wire [ 31:0] radio1_radio_rx_running;
wire [1023:0] radio1_radio_tx_data;
wire [ 31:0] radio1_radio_tx_stb;
wire [ 31:0] radio1_radio_tx_running;
wire [32*1*2-1:0] radio1_radio_rx_data;
wire [ 1:0] radio1_radio_rx_stb;
wire [ 1:0] radio1_radio_rx_running;
wire [32*1*2-1:0] radio1_radio_tx_data;
wire [ 1:0] radio1_radio_tx_stb;
wire [ 1:0] radio1_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (3),
@@ -948,12 +960,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_radio1_out_1_tlast , m_radio1_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio1_out_1_tvalid, m_radio1_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio1_out_1_tready, m_radio1_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_radio1_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio1_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_radio1_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio1_ctrl_tready)
);
@@ -973,7 +985,7 @@ module rfnoc_image_core #(
wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready;
// axi_ram
wire [ 0:0] fifo0_axi_rst;
wire fifo0_axi_rst;
wire [ 7:0] fifo0_m_axi_awid;
wire [ 383:0] fifo0_m_axi_awaddr;
wire [ 63:0] fifo0_m_axi_awlen;
@@ -1090,12 +1102,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_fifo0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_fifo0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_fifo0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_fifo0_ctrl_tready)
);
@@ -1180,7 +1192,7 @@ module rfnoc_image_core #(
//---------------------------------------------------------------------------
// Clock Domains
// Clock Domains and Resets
//---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk;
top/n3xx/n310_bist_static_router.hex
-13
View File
@@ -1,13 +0,0 @@
0000000C
004001c0
01c00040
008001c1
01c10080
00c00200
020000c0
01000201
02010100
01400240
02400140
01800241
02410180
top/n3xx/n310_rfnoc_image_core.v
+101 -73
View File
@@ -42,45 +42,45 @@ module rfnoc_image_core #(
// IO ports /////////////////////////
// ctrlport_radio0
output wire [ 0:0] m_ctrlport_radio0_req_wr,
output wire [ 0:0] m_ctrlport_radio0_req_rd,
output wire m_ctrlport_radio0_req_wr,
output wire m_ctrlport_radio0_req_rd,
output wire [ 19:0] m_ctrlport_radio0_req_addr,
output wire [ 31:0] m_ctrlport_radio0_req_data,
output wire [ 3:0] m_ctrlport_radio0_req_byte_en,
output wire [ 0:0] m_ctrlport_radio0_req_has_time,
output wire m_ctrlport_radio0_req_has_time,
output wire [ 63:0] m_ctrlport_radio0_req_time,
input wire [ 0:0] m_ctrlport_radio0_resp_ack,
input wire m_ctrlport_radio0_resp_ack,
input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 31:0] m_ctrlport_radio0_resp_data,
// ctrlport_radio1
output wire [ 0:0] m_ctrlport_radio1_req_wr,
output wire [ 0:0] m_ctrlport_radio1_req_rd,
output wire m_ctrlport_radio1_req_wr,
output wire m_ctrlport_radio1_req_rd,
output wire [ 19:0] m_ctrlport_radio1_req_addr,
output wire [ 31:0] m_ctrlport_radio1_req_data,
output wire [ 3:0] m_ctrlport_radio1_req_byte_en,
output wire [ 0:0] m_ctrlport_radio1_req_has_time,
output wire m_ctrlport_radio1_req_has_time,
output wire [ 63:0] m_ctrlport_radio1_req_time,
input wire [ 0:0] m_ctrlport_radio1_resp_ack,
input wire m_ctrlport_radio1_resp_ack,
input wire [ 1:0] m_ctrlport_radio1_resp_status,
input wire [ 31:0] m_ctrlport_radio1_resp_data,
// time
input wire [ 63:0] radio_time,
// radio0
input wire [1023:0] radio_rx_data_radio0,
input wire [ 31:0] radio_rx_stb_radio0,
output wire [ 31:0] radio_rx_running_radio0,
output wire [1023:0] radio_tx_data_radio0,
input wire [ 31:0] radio_tx_stb_radio0,
output wire [ 31:0] radio_tx_running_radio0,
input wire [ 63:0] radio_rx_data_radio0,
input wire [ 1:0] radio_rx_stb_radio0,
output wire [ 1:0] radio_rx_running_radio0,
output wire [ 63:0] radio_tx_data_radio0,
input wire [ 1:0] radio_tx_stb_radio0,
output wire [ 1:0] radio_tx_running_radio0,
// radio1
input wire [1023:0] radio_rx_data_radio1,
input wire [ 31:0] radio_rx_stb_radio1,
output wire [ 31:0] radio_rx_running_radio1,
output wire [1023:0] radio_tx_data_radio1,
input wire [ 31:0] radio_tx_stb_radio1,
output wire [ 31:0] radio_tx_running_radio1,
input wire [ 63:0] radio_rx_data_radio1,
input wire [ 1:0] radio_rx_stb_radio1,
output wire [ 1:0] radio_rx_running_radio1,
output wire [ 63:0] radio_tx_data_radio1,
input wire [ 1:0] radio_tx_stb_radio1,
output wire [ 1:0] radio_tx_running_radio1,
// dram
input wire [ 0:0] axi_rst,
input wire axi_rst,
output wire [ 7:0] m_axi_awid,
output wire [ 383:0] m_axi_awaddr,
output wire [ 63:0] m_axi_awlen,
@@ -157,7 +157,6 @@ module rfnoc_image_core #(
input wire m_dma_tready
);
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
@@ -943,7 +942,32 @@ module rfnoc_image_core #(
.NUM_TRANSPORTS (3),
.NUM_EDGES (24),
.CHDR_XBAR_PRESENT (1),
.EDGE_TBL_FILE (EDGE_TBL_FILE)
.EDGE_TBL ({
{10'd15, 6'd03, 10'd08, 6'd00},
{10'd08, 6'd00, 10'd15, 6'd03},
{10'd15, 6'd02, 10'd07, 6'd00},
{10'd07, 6'd00, 10'd15, 6'd02},
{10'd15, 6'd01, 10'd06, 6'd00},
{10'd06, 6'd00, 10'd15, 6'd01},
{10'd15, 6'd00, 10'd05, 6'd00},
{10'd05, 6'd00, 10'd15, 6'd00},
{10'd13, 6'd01, 10'd04, 6'd00},
{10'd14, 6'd01, 10'd13, 6'd01},
{10'd12, 6'd01, 10'd14, 6'd01},
{10'd04, 6'd00, 10'd12, 6'd01},
{10'd13, 6'd00, 10'd03, 6'd00},
{10'd14, 6'd00, 10'd13, 6'd00},
{10'd12, 6'd00, 10'd14, 6'd00},
{10'd03, 6'd00, 10'd12, 6'd00},
{10'd10, 6'd01, 10'd02, 6'd00},
{10'd11, 6'd01, 10'd10, 6'd01},
{10'd09, 6'd01, 10'd11, 6'd01},
{10'd02, 6'd00, 10'd09, 6'd01},
{10'd10, 6'd00, 10'd01, 6'd00},
{10'd11, 6'd00, 10'd10, 6'd00},
{10'd09, 6'd00, 10'd11, 6'd00},
{10'd01, 6'd00, 10'd09, 6'd00}
})
) core_kernel_i (
.chdr_aclk (chdr_aclk),
.chdr_aclk_locked (1'b1),
@@ -986,6 +1010,7 @@ module rfnoc_image_core #(
wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid;
wire m_duc0_out_1_tready, m_duc0_out_0_tready;
rfnoc_block_duc #(
.THIS_PORTID (2),
.CHDR_W (BLOCK_CHDR_W),
@@ -1007,12 +1032,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_duc0_out_1_tlast , m_duc0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_duc0_out_1_tvalid, m_duc0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_duc0_out_1_tready, m_duc0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_duc0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_duc0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_duc0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_duc0_ctrl_tready)
);
@@ -1031,6 +1056,7 @@ module rfnoc_image_core #(
wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid;
wire m_ddc0_out_1_tready, m_ddc0_out_0_tready;
rfnoc_block_ddc #(
.THIS_PORTID (3),
.CHDR_W (BLOCK_CHDR_W),
@@ -1052,12 +1078,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_ddc0_out_1_tlast , m_ddc0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_ddc0_out_1_tready, m_ddc0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_ddc0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_ddc0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_ddc0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_ddc0_ctrl_tready)
);
@@ -1077,25 +1103,25 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire radio0_m_ctrlport_req_wr;
wire radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire radio0_m_ctrlport_req_has_time;
wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
// time
wire [ 63:0] radio0_radio_time;
// radio
wire [1023:0] radio0_radio_rx_data;
wire [ 31:0] radio0_radio_rx_stb;
wire [ 31:0] radio0_radio_rx_running;
wire [1023:0] radio0_radio_tx_data;
wire [ 31:0] radio0_radio_tx_stb;
wire [ 31:0] radio0_radio_tx_running;
wire [32*1*2-1:0] radio0_radio_rx_data;
wire [ 1:0] radio0_radio_rx_stb;
wire [ 1:0] radio0_radio_rx_running;
wire [32*1*2-1:0] radio0_radio_tx_data;
wire [ 1:0] radio0_radio_tx_stb;
wire [ 1:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (4),
@@ -1135,12 +1161,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio0_out_1_tready, m_radio0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
);
@@ -1159,6 +1185,7 @@ module rfnoc_image_core #(
wire m_duc1_out_1_tvalid, m_duc1_out_0_tvalid;
wire m_duc1_out_1_tready, m_duc1_out_0_tready;
rfnoc_block_duc #(
.THIS_PORTID (5),
.CHDR_W (BLOCK_CHDR_W),
@@ -1180,12 +1207,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_duc1_out_1_tlast , m_duc1_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_duc1_out_1_tvalid, m_duc1_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_duc1_out_1_tready, m_duc1_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_duc1_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_duc1_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_duc1_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_duc1_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_duc1_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_duc1_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_duc1_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_duc1_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_duc1_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_duc1_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_duc1_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_duc1_ctrl_tready)
);
@@ -1204,6 +1231,7 @@ module rfnoc_image_core #(
wire m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid;
wire m_ddc1_out_1_tready, m_ddc1_out_0_tready;
rfnoc_block_ddc #(
.THIS_PORTID (6),
.CHDR_W (BLOCK_CHDR_W),
@@ -1225,12 +1253,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_ddc1_out_1_tlast , m_ddc1_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_ddc1_out_1_tready, m_ddc1_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_ddc1_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_ddc1_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_ddc1_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_ddc1_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_ddc1_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_ddc1_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_ddc1_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_ddc1_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_ddc1_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_ddc1_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_ddc1_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_ddc1_ctrl_tready)
);
@@ -1250,25 +1278,25 @@ module rfnoc_image_core #(
wire m_radio1_out_1_tready, m_radio1_out_0_tready;
// ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr;
wire [ 0:0] radio1_m_ctrlport_req_rd;
wire radio1_m_ctrlport_req_wr;
wire radio1_m_ctrlport_req_rd;
wire [ 19:0] radio1_m_ctrlport_req_addr;
wire [ 31:0] radio1_m_ctrlport_req_data;
wire [ 3:0] radio1_m_ctrlport_req_byte_en;
wire [ 0:0] radio1_m_ctrlport_req_has_time;
wire radio1_m_ctrlport_req_has_time;
wire [ 63:0] radio1_m_ctrlport_req_time;
wire [ 0:0] radio1_m_ctrlport_resp_ack;
wire radio1_m_ctrlport_resp_ack;
wire [ 1:0] radio1_m_ctrlport_resp_status;
wire [ 31:0] radio1_m_ctrlport_resp_data;
// time
wire [ 63:0] radio1_radio_time;
// radio
wire [1023:0] radio1_radio_rx_data;
wire [ 31:0] radio1_radio_rx_stb;
wire [ 31:0] radio1_radio_rx_running;
wire [1023:0] radio1_radio_tx_data;
wire [ 31:0] radio1_radio_tx_stb;
wire [ 31:0] radio1_radio_tx_running;
wire [32*1*2-1:0] radio1_radio_rx_data;
wire [ 1:0] radio1_radio_rx_stb;
wire [ 1:0] radio1_radio_rx_running;
wire [32*1*2-1:0] radio1_radio_tx_data;
wire [ 1:0] radio1_radio_tx_stb;
wire [ 1:0] radio1_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (7),
@@ -1308,12 +1336,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_radio1_out_1_tlast , m_radio1_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio1_out_1_tvalid, m_radio1_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio1_out_1_tready, m_radio1_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_radio1_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio1_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_radio1_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio1_ctrl_tready)
);
@@ -1333,7 +1361,7 @@ module rfnoc_image_core #(
wire m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready;
// axi_ram
wire [ 0:0] replay0_axi_rst;
wire replay0_axi_rst;
wire [ 7:0] replay0_m_axi_awid;
wire [ 383:0] replay0_m_axi_awaddr;
wire [ 63:0] replay0_m_axi_awlen;
@@ -1445,12 +1473,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_replay0_out_3_tlast , m_replay0_out_2_tlast , m_replay0_out_1_tlast , m_replay0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_replay0_out_3_tvalid, m_replay0_out_2_tvalid, m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_replay0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_replay0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_replay0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_replay0_ctrl_tready)
);
@@ -1587,7 +1615,7 @@ module rfnoc_image_core #(
//---------------------------------------------------------------------------
// Clock Domains
// Clock Domains and Resets
//---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk;
top/n3xx/n310_static_router.hex
-25
View File
@@ -1,25 +0,0 @@
00000018
00400240
024002c0
02c00280
02800040
00800241
024102c1
02c10281
02810080
00c00300
03000380
03800340
034000c0
01000301
03010381
03810341
03410100
014003c0
03c00140
018003c1
03c10180
01c003c2
03c201c0
020003c3
03c30200
top/n3xx/n320_bist_rfnoc_image_core.v
+65 -57
View File
@@ -42,45 +42,45 @@ module rfnoc_image_core #(
// IO ports /////////////////////////
// ctrlport_radio0
output wire [ 0:0] m_ctrlport_radio0_req_wr,
output wire [ 0:0] m_ctrlport_radio0_req_rd,
output wire m_ctrlport_radio0_req_wr,
output wire m_ctrlport_radio0_req_rd,
output wire [ 19:0] m_ctrlport_radio0_req_addr,
output wire [ 31:0] m_ctrlport_radio0_req_data,
output wire [ 3:0] m_ctrlport_radio0_req_byte_en,
output wire [ 0:0] m_ctrlport_radio0_req_has_time,
output wire m_ctrlport_radio0_req_has_time,
output wire [ 63:0] m_ctrlport_radio0_req_time,
input wire [ 0:0] m_ctrlport_radio0_resp_ack,
input wire m_ctrlport_radio0_resp_ack,
input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 31:0] m_ctrlport_radio0_resp_data,
// ctrlport_radio1
output wire [ 0:0] m_ctrlport_radio1_req_wr,
output wire [ 0:0] m_ctrlport_radio1_req_rd,
output wire m_ctrlport_radio1_req_wr,
output wire m_ctrlport_radio1_req_rd,
output wire [ 19:0] m_ctrlport_radio1_req_addr,
output wire [ 31:0] m_ctrlport_radio1_req_data,
output wire [ 3:0] m_ctrlport_radio1_req_byte_en,
output wire [ 0:0] m_ctrlport_radio1_req_has_time,
output wire m_ctrlport_radio1_req_has_time,
output wire [ 63:0] m_ctrlport_radio1_req_time,
input wire [ 0:0] m_ctrlport_radio1_resp_ack,
input wire m_ctrlport_radio1_resp_ack,
input wire [ 1:0] m_ctrlport_radio1_resp_status,
input wire [ 31:0] m_ctrlport_radio1_resp_data,
// time
input wire [ 63:0] radio_time,
// radio0
input wire [1023:0] radio_rx_data_radio0,
input wire [ 31:0] radio_rx_stb_radio0,
output wire [ 31:0] radio_rx_running_radio0,
output wire [1023:0] radio_tx_data_radio0,
input wire [ 31:0] radio_tx_stb_radio0,
output wire [ 31:0] radio_tx_running_radio0,
input wire [ 63:0] radio_rx_data_radio0,
input wire [ 1:0] radio_rx_stb_radio0,
output wire [ 1:0] radio_rx_running_radio0,
output wire [ 63:0] radio_tx_data_radio0,
input wire [ 1:0] radio_tx_stb_radio0,
output wire [ 1:0] radio_tx_running_radio0,
// radio1
input wire [1023:0] radio_rx_data_radio1,
input wire [ 31:0] radio_rx_stb_radio1,
output wire [ 31:0] radio_rx_running_radio1,
output wire [1023:0] radio_tx_data_radio1,
input wire [ 31:0] radio_tx_stb_radio1,
output wire [ 31:0] radio_tx_running_radio1,
input wire [ 63:0] radio_rx_data_radio1,
input wire [ 1:0] radio_rx_stb_radio1,
output wire [ 1:0] radio_rx_running_radio1,
output wire [ 63:0] radio_tx_data_radio1,
input wire [ 1:0] radio_tx_stb_radio1,
output wire [ 1:0] radio_tx_running_radio1,
// dram
input wire [ 0:0] axi_rst,
input wire axi_rst,
output wire [ 7:0] m_axi_awid,
output wire [ 383:0] m_axi_awaddr,
output wire [ 63:0] m_axi_awlen,
@@ -157,7 +157,6 @@ module rfnoc_image_core #(
input wire m_dma_tready
);
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
@@ -599,7 +598,16 @@ module rfnoc_image_core #(
.NUM_TRANSPORTS (3),
.NUM_EDGES (8),
.CHDR_XBAR_PRESENT (1),
.EDGE_TBL_FILE (EDGE_TBL_FILE)
.EDGE_TBL ({
{10'd07, 6'd01, 10'd04, 6'd00},
{10'd04, 6'd00, 10'd07, 6'd01},
{10'd07, 6'd00, 10'd03, 6'd00},
{10'd03, 6'd00, 10'd07, 6'd00},
{10'd06, 6'd00, 10'd02, 6'd00},
{10'd02, 6'd00, 10'd06, 6'd00},
{10'd05, 6'd00, 10'd01, 6'd00},
{10'd01, 6'd00, 10'd05, 6'd00}
})
) core_kernel_i (
.chdr_aclk (chdr_aclk),
.chdr_aclk_locked (1'b1),
@@ -643,25 +651,25 @@ module rfnoc_image_core #(
wire m_radio0_out_0_tready;
// ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire radio0_m_ctrlport_req_wr;
wire radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire radio0_m_ctrlport_req_has_time;
wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
// time
wire [ 63:0] radio0_radio_time;
// radio
wire [1023:0] radio0_radio_rx_data;
wire [ 31:0] radio0_radio_rx_stb;
wire [ 31:0] radio0_radio_rx_running;
wire [1023:0] radio0_radio_tx_data;
wire [ 31:0] radio0_radio_tx_stb;
wire [ 31:0] radio0_radio_tx_running;
wire [32*1*1-1:0] radio0_radio_rx_data;
wire radio0_radio_rx_stb;
wire radio0_radio_rx_running;
wire [32*1*1-1:0] radio0_radio_tx_data;
wire radio0_radio_tx_stb;
wire radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (2),
@@ -701,12 +709,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_radio0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
);
@@ -726,25 +734,25 @@ module rfnoc_image_core #(
wire m_radio1_out_0_tready;
// ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr;
wire [ 0:0] radio1_m_ctrlport_req_rd;
wire radio1_m_ctrlport_req_wr;
wire radio1_m_ctrlport_req_rd;
wire [ 19:0] radio1_m_ctrlport_req_addr;
wire [ 31:0] radio1_m_ctrlport_req_data;
wire [ 3:0] radio1_m_ctrlport_req_byte_en;
wire [ 0:0] radio1_m_ctrlport_req_has_time;
wire radio1_m_ctrlport_req_has_time;
wire [ 63:0] radio1_m_ctrlport_req_time;
wire [ 0:0] radio1_m_ctrlport_resp_ack;
wire radio1_m_ctrlport_resp_ack;
wire [ 1:0] radio1_m_ctrlport_resp_status;
wire [ 31:0] radio1_m_ctrlport_resp_data;
// time
wire [ 63:0] radio1_radio_time;
// radio
wire [1023:0] radio1_radio_rx_data;
wire [ 31:0] radio1_radio_rx_stb;
wire [ 31:0] radio1_radio_rx_running;
wire [1023:0] radio1_radio_tx_data;
wire [ 31:0] radio1_radio_tx_stb;
wire [ 31:0] radio1_radio_tx_running;
wire [32*1*1-1:0] radio1_radio_rx_data;
wire radio1_radio_rx_stb;
wire radio1_radio_rx_running;
wire [32*1*1-1:0] radio1_radio_tx_data;
wire radio1_radio_tx_stb;
wire radio1_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (3),
@@ -784,12 +792,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_radio1_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio1_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio1_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_radio1_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio1_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_radio1_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio1_ctrl_tready)
);
@@ -809,7 +817,7 @@ module rfnoc_image_core #(
wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready;
// axi_ram
wire [ 0:0] fifo0_axi_rst;
wire fifo0_axi_rst;
wire [ 7:0] fifo0_m_axi_awid;
wire [ 383:0] fifo0_m_axi_awaddr;
wire [ 63:0] fifo0_m_axi_awlen;
@@ -926,12 +934,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_fifo0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_fifo0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_fifo0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_fifo0_ctrl_tready)
);
@@ -996,7 +1004,7 @@ module rfnoc_image_core #(
//---------------------------------------------------------------------------
// Clock Domains
// Clock Domains and Resets
//---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk;
top/n3xx/n320_bist_static_router.hex
-9
View File
@@ -1,9 +0,0 @@
00000008
00400140
01400040
00800180
01800080
00c001c0
01c000c0
010001c1
01c10100
top/n3xx/n320_rfnoc_image_core.v
+89 -73
View File
@@ -42,45 +42,45 @@ module rfnoc_image_core #(
// IO ports /////////////////////////
// ctrlport_radio0
output wire [ 0:0] m_ctrlport_radio0_req_wr,
output wire [ 0:0] m_ctrlport_radio0_req_rd,
output wire m_ctrlport_radio0_req_wr,
output wire m_ctrlport_radio0_req_rd,
output wire [ 19:0] m_ctrlport_radio0_req_addr,
output wire [ 31:0] m_ctrlport_radio0_req_data,
output wire [ 3:0] m_ctrlport_radio0_req_byte_en,
output wire [ 0:0] m_ctrlport_radio0_req_has_time,
output wire m_ctrlport_radio0_req_has_time,
output wire [ 63:0] m_ctrlport_radio0_req_time,
input wire [ 0:0] m_ctrlport_radio0_resp_ack,
input wire m_ctrlport_radio0_resp_ack,
input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 31:0] m_ctrlport_radio0_resp_data,
// ctrlport_radio1
output wire [ 0:0] m_ctrlport_radio1_req_wr,
output wire [ 0:0] m_ctrlport_radio1_req_rd,
output wire m_ctrlport_radio1_req_wr,
output wire m_ctrlport_radio1_req_rd,
output wire [ 19:0] m_ctrlport_radio1_req_addr,
output wire [ 31:0] m_ctrlport_radio1_req_data,
output wire [ 3:0] m_ctrlport_radio1_req_byte_en,
output wire [ 0:0] m_ctrlport_radio1_req_has_time,
output wire m_ctrlport_radio1_req_has_time,
output wire [ 63:0] m_ctrlport_radio1_req_time,
input wire [ 0:0] m_ctrlport_radio1_resp_ack,
input wire m_ctrlport_radio1_resp_ack,
input wire [ 1:0] m_ctrlport_radio1_resp_status,
input wire [ 31:0] m_ctrlport_radio1_resp_data,
// time
input wire [ 63:0] radio_time,
// radio0
input wire [1023:0] radio_rx_data_radio0,
input wire [ 31:0] radio_rx_stb_radio0,
output wire [ 31:0] radio_rx_running_radio0,
output wire [1023:0] radio_tx_data_radio0,
input wire [ 31:0] radio_tx_stb_radio0,
output wire [ 31:0] radio_tx_running_radio0,
input wire [ 63:0] radio_rx_data_radio0,
input wire [ 1:0] radio_rx_stb_radio0,
output wire [ 1:0] radio_rx_running_radio0,
output wire [ 63:0] radio_tx_data_radio0,
input wire [ 1:0] radio_tx_stb_radio0,
output wire [ 1:0] radio_tx_running_radio0,
// radio1
input wire [1023:0] radio_rx_data_radio1,
input wire [ 31:0] radio_rx_stb_radio1,
output wire [ 31:0] radio_rx_running_radio1,
output wire [1023:0] radio_tx_data_radio1,
input wire [ 31:0] radio_tx_stb_radio1,
output wire [ 31:0] radio_tx_running_radio1,
input wire [ 63:0] radio_rx_data_radio1,
input wire [ 1:0] radio_rx_stb_radio1,
output wire [ 1:0] radio_rx_running_radio1,
output wire [ 63:0] radio_tx_data_radio1,
input wire [ 1:0] radio_tx_stb_radio1,
output wire [ 1:0] radio_tx_running_radio1,
// dram
input wire [ 0:0] axi_rst,
input wire axi_rst,
output wire [ 7:0] m_axi_awid,
output wire [ 383:0] m_axi_awaddr,
output wire [ 63:0] m_axi_awlen,
@@ -157,7 +157,6 @@ module rfnoc_image_core #(
input wire m_dma_tready
);
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
localparam BLOCK_CHDR_W = 64;
localparam BYTE_MTU = MTU + $clog2(CHDR_W/8);
localparam BLOCK_MTU = BYTE_MTU - $clog2(BLOCK_CHDR_W/8);
@@ -615,7 +614,20 @@ module rfnoc_image_core #(
.NUM_TRANSPORTS (3),
.NUM_EDGES (12),
.CHDR_XBAR_PRESENT (1),
.EDGE_TBL_FILE (EDGE_TBL_FILE)
.EDGE_TBL ({
{10'd11, 6'd01, 10'd04, 6'd00},
{10'd04, 6'd00, 10'd11, 6'd01},
{10'd11, 6'd00, 10'd03, 6'd00},
{10'd03, 6'd00, 10'd11, 6'd00},
{10'd09, 6'd00, 10'd02, 6'd00},
{10'd10, 6'd00, 10'd09, 6'd00},
{10'd08, 6'd00, 10'd10, 6'd00},
{10'd02, 6'd00, 10'd08, 6'd00},
{10'd06, 6'd00, 10'd01, 6'd00},
{10'd07, 6'd00, 10'd06, 6'd00},
{10'd05, 6'd00, 10'd07, 6'd00},
{10'd01, 6'd00, 10'd05, 6'd00}
})
) core_kernel_i (
.chdr_aclk (chdr_aclk),
.chdr_aclk_locked (1'b1),
@@ -658,6 +670,7 @@ module rfnoc_image_core #(
wire m_duc0_out_0_tvalid;
wire m_duc0_out_0_tready;
rfnoc_block_duc #(
.THIS_PORTID (2),
.CHDR_W (BLOCK_CHDR_W),
@@ -679,12 +692,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_duc0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_duc0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_duc0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_duc0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_duc0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_duc0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_duc0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_duc0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_duc0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_duc0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_duc0_ctrl_tready)
);
@@ -703,6 +716,7 @@ module rfnoc_image_core #(
wire m_ddc0_out_0_tvalid;
wire m_ddc0_out_0_tready;
rfnoc_block_ddc #(
.THIS_PORTID (3),
.CHDR_W (BLOCK_CHDR_W),
@@ -724,12 +738,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_ddc0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_ddc0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_ddc0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_ddc0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_ddc0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_ddc0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_ddc0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_ddc0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_ddc0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_ddc0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_ddc0_ctrl_tready)
);
@@ -749,25 +763,25 @@ module rfnoc_image_core #(
wire m_radio0_out_0_tready;
// ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire radio0_m_ctrlport_req_wr;
wire radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire radio0_m_ctrlport_req_has_time;
wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
// time
wire [ 63:0] radio0_radio_time;
// radio
wire [1023:0] radio0_radio_rx_data;
wire [ 31:0] radio0_radio_rx_stb;
wire [ 31:0] radio0_radio_rx_running;
wire [1023:0] radio0_radio_tx_data;
wire [ 31:0] radio0_radio_tx_stb;
wire [ 31:0] radio0_radio_tx_running;
wire [32*1*1-1:0] radio0_radio_rx_data;
wire radio0_radio_rx_stb;
wire radio0_radio_rx_running;
wire [32*1*1-1:0] radio0_radio_tx_data;
wire radio0_radio_tx_stb;
wire radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (4),
@@ -807,12 +821,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_radio0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
);
@@ -831,6 +845,7 @@ module rfnoc_image_core #(
wire m_duc1_out_0_tvalid;
wire m_duc1_out_0_tready;
rfnoc_block_duc #(
.THIS_PORTID (5),
.CHDR_W (BLOCK_CHDR_W),
@@ -852,12 +867,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_duc1_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_duc1_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_duc1_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_duc1_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_duc1_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_duc1_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_duc1_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_duc1_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_duc1_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_duc1_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_duc1_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_duc1_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_duc1_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_duc1_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_duc1_ctrl_tready)
);
@@ -876,6 +891,7 @@ module rfnoc_image_core #(
wire m_ddc1_out_0_tvalid;
wire m_ddc1_out_0_tready;
rfnoc_block_ddc #(
.THIS_PORTID (6),
.CHDR_W (BLOCK_CHDR_W),
@@ -897,12 +913,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_ddc1_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_ddc1_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_ddc1_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_ddc1_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_ddc1_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_ddc1_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_ddc1_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_ddc1_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_ddc1_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_ddc1_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_ddc1_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_ddc1_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_ddc1_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_ddc1_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_ddc1_ctrl_tready)
);
@@ -922,25 +938,25 @@ module rfnoc_image_core #(
wire m_radio1_out_0_tready;
// ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr;
wire [ 0:0] radio1_m_ctrlport_req_rd;
wire radio1_m_ctrlport_req_wr;
wire radio1_m_ctrlport_req_rd;
wire [ 19:0] radio1_m_ctrlport_req_addr;
wire [ 31:0] radio1_m_ctrlport_req_data;
wire [ 3:0] radio1_m_ctrlport_req_byte_en;
wire [ 0:0] radio1_m_ctrlport_req_has_time;
wire radio1_m_ctrlport_req_has_time;
wire [ 63:0] radio1_m_ctrlport_req_time;
wire [ 0:0] radio1_m_ctrlport_resp_ack;
wire radio1_m_ctrlport_resp_ack;
wire [ 1:0] radio1_m_ctrlport_resp_status;
wire [ 31:0] radio1_m_ctrlport_resp_data;
// time
wire [ 63:0] radio1_radio_time;
// radio
wire [1023:0] radio1_radio_rx_data;
wire [ 31:0] radio1_radio_rx_stb;
wire [ 31:0] radio1_radio_rx_running;
wire [1023:0] radio1_radio_tx_data;
wire [ 31:0] radio1_radio_tx_stb;
wire [ 31:0] radio1_radio_tx_running;
wire [32*1*1-1:0] radio1_radio_rx_data;
wire radio1_radio_rx_stb;
wire radio1_radio_rx_running;
wire [32*1*1-1:0] radio1_radio_tx_data;
wire radio1_radio_tx_stb;
wire radio1_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (7),
@@ -980,12 +996,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_radio1_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_radio1_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_radio1_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_radio1_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_radio1_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_radio1_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_radio1_ctrl_tready)
);
@@ -1005,7 +1021,7 @@ module rfnoc_image_core #(
wire m_replay0_out_1_tready, m_replay0_out_0_tready;
// axi_ram
wire [ 0:0] replay0_axi_rst;
wire replay0_axi_rst;
wire [ 7:0] replay0_m_axi_awid;
wire [ 383:0] replay0_m_axi_awaddr;
wire [ 63:0] replay0_m_axi_awlen;
@@ -1117,12 +1133,12 @@ module rfnoc_image_core #(
.m_rfnoc_chdr_tlast ({m_replay0_out_1_tlast , m_replay0_out_0_tlast }),
.m_rfnoc_chdr_tvalid ({m_replay0_out_1_tvalid, m_replay0_out_0_tvalid}),
.m_rfnoc_chdr_tready ({m_replay0_out_1_tready, m_replay0_out_0_tready}),
.s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata),
.s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast),
.s_rfnoc_ctrl_tdata (s_replay0_ctrl_tdata ),
.s_rfnoc_ctrl_tlast (s_replay0_ctrl_tlast ),
.s_rfnoc_ctrl_tvalid (s_replay0_ctrl_tvalid),
.s_rfnoc_ctrl_tready (s_replay0_ctrl_tready),
.m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata),
.m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast),
.m_rfnoc_ctrl_tdata (m_replay0_ctrl_tdata ),
.m_rfnoc_ctrl_tlast (m_replay0_ctrl_tlast ),
.m_rfnoc_ctrl_tvalid (m_replay0_ctrl_tvalid),
.m_rfnoc_ctrl_tready (m_replay0_ctrl_tready)
);
@@ -1199,7 +1215,7 @@ module rfnoc_image_core #(
//---------------------------------------------------------------------------
// Clock Domains
// Clock Domains and Resets
//---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk;
top/n3xx/n320_static_router.hex
-13
View File
@@ -1,13 +0,0 @@
0000000C
00400140
014001c0
01c00180
01800040
00800200
02000280
02800240
02400080
00c002c0
02c000c0
010002c1
02c10100