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fpga: x440: fix conditional timing constraints

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Original-commit: f407c1cc11f14fb3cef6975c62b6ba5c380aa9ce
This commit is contained in:
Max Köhler
2024-08-27 17:22:35 -05:00
committed by Wade Fife
parent 31ecc191a3
commit 82545838b2
1 changed files with 2 additions and 2 deletions
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top/x400/Makefile.x4xx.inc
+2 -2
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@@ -106,11 +106,11 @@ constraints/timing/x410_clocks.xdc
endif endif
ifdef X440 ifdef X440
ifeq ($(RF_BW), 400) ifneq (,$(findstring RF_BW=400,$(RFNOC_IMAGE_CORE_DEFS)))
MB_XDC += \ MB_XDC += \
constraints/timing/x440_clocks_400.xdc constraints/timing/x440_clocks_400.xdc
endif endif
ifeq ($(RF_BW), 1600) ifneq (,$(findstring RF_BW=1600,$(RFNOC_IMAGE_CORE_DEFS)))
MB_XDC += \ MB_XDC += \
constraints/timing/x440_clocks_1600.xdc constraints/timing/x440_clocks_1600.xdc
endif endif