From 82545838b29aeedd87f97174a4f23f831879aafe Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Max=20K=C3=B6hler?= <max.koehler@ni.com>
Date: Tue, 27 Aug 2024 17:11:23 +0200
Subject: [PATCH] fpga: x440: fix conditional timing constraints

Original-commit: f407c1cc11f14fb3cef6975c62b6ba5c380aa9ce
---
 top/x400/Makefile.x4xx.inc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/top/x400/Makefile.x4xx.inc b/top/x400/Makefile.x4xx.inc
index 8e8c0f3..539fc86 100644
--- a/top/x400/Makefile.x4xx.inc
+++ b/top/x400/Makefile.x4xx.inc
@@ -106,11 +106,11 @@ constraints/timing/x410_clocks.xdc
 endif
 
 ifdef X440
-ifeq ($(RF_BW), 400)
+ifneq (,$(findstring RF_BW=400,$(RFNOC_IMAGE_CORE_DEFS)))
 MB_XDC += \
 constraints/timing/x440_clocks_400.xdc
 endif
-ifeq ($(RF_BW), 1600)
+ifneq (,$(findstring RF_BW=1600,$(RFNOC_IMAGE_CORE_DEFS)))
 MB_XDC += \
 constraints/timing/x440_clocks_1600.xdc
 endif