fpga: x440: fix conditional timing constraints

Original-commit: f407c1cc11f14fb3cef6975c62b6ba5c380aa9ce
2024-08-27 17:22:35 -05:00
parent 31ecc191a3
commit 82545838b2
1 changed files with 2 additions and 2 deletions
@@ -106,11 +106,11 @@ constraints/timing/x410_clocks.xdc
 endif

 ifdef X440
-ifeq ($(RF_BW), 400)
+ifneq (,$(findstring RF_BW=400,$(RFNOC_IMAGE_CORE_DEFS)))
 MB_XDC += \
 constraints/timing/x440_clocks_400.xdc
 endif
-ifeq ($(RF_BW), 1600)
+ifneq (,$(findstring RF_BW=1600,$(RFNOC_IMAGE_CORE_DEFS)))
 MB_XDC += \
 constraints/timing/x440_clocks_1600.xdc
 endif