Removed copy of FPGA source files.
Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
This commit is contained in:
Martin Braun
@@ -1,6 +0,0 @@
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build*
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isim*
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fuse*
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tmp*
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*.log
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*impact*
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@@ -1,106 +0,0 @@
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#
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# Copyright 2012-2013 Ettus Research LLC
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#
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# Uncomment the following lines to build radio's with no DSP's
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#OPTIONS += DELETE_DSP0=1
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#OPTIONS += DELETE_DSP1=1
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# Uncomment the following line to add a debug UART on GPIO 10 & 11
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#OPTIONS += DEBUG_UART=1
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CREATE_LVBITX=python ../../lib/io_port2/create-lvbitx.py
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GIGE_DEFS=BUILD_1G=1 $(OPTIONS)
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HYBRID_DEFS=ETH10G_PORT1=1 BUILD_1G=1 BUILD_10G=1 $(OPTIONS)
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XGIGE_DEFS=ETH10G_PORT0=1 ETH10G_PORT1=1 BUILD_10G=1 $(OPTIONS)
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HYBRID_SRAM_DEFS=ETH10G_PORT1=1 BUILD_1G=1 BUILD_10G=1 NO_DRAM_FIFOS=1 SRAM_FIFO_SIZE=16 $(OPTIONS)
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XGIGE_SRAM_DEFS=ETH10G_PORT0=1 ETH10G_PORT1=1 BUILD_10G=1 NO_DRAM_FIFOS=1 SRAM_FIFO_SIZE=16 $(OPTIONS)
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X300: X300_HGS X300_HG X300_XGS X300_XG
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X310: X310_HGS X310_HG X310_XGS X310_XG
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all: X300 X310
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clean:
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rm -rf build-*_*
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rm -rf build
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print_report = \
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echo "========================================================================"; \
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cat $(1)/x300.syr | grep "Device utilization summary:" -A 30; \
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echo "========================================================================"; \
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echo "Timing Summary:\n"; \
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cat $(1)/x300.twr | grep constraint | grep met | grep -v "*"; \
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echo "========================================================================";
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# ise_build($1=Device, $2=Definitions)
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ifndef EXPORT_ONLY
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ise_build = make -f Makefile.x300.inc bin NAME=$@ DEVICE=$1 $2 EXTRA_DEFS="$2"
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else
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ise_build = @echo "Skipping ISE build and exporting pre-built files.";
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endif
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# post_build($1=Device, $2=Flavor)
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post_build = \
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@$(call print_report,build-$(1)_$(2)) \
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mkdir -p build; \
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echo "Exporting bitstream files..."; \
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cp build-$(1)_$(2)/x300.bin build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bin; \
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cp build-$(1)_$(2)/x300.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
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echo "Generating LVBITX..."; \
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$(CREATE_LVBITX) --input-bin=build-$(1)_$(2)/x300.bin --output-lvbitx=build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).lvbitx --device="USRP $(1)" x3x0_base.lvbitx; \
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cp -f x3x0_base.lvbitx build/`echo $(1) | tr A-Z a-z`.lvbitx_base; \
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echo "Exporting logs..."; \
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cp build-$(1)_$(2)/x300.syr build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).syr; \
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cp build-$(1)_$(2)/x300.twr build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).twr; \
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echo "\nDONE ... $(1)_$(2)\n";
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#1Gig on both ports
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X310_1G:
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$(call ise_build,XC7K410T,$(GIGE_DEFS))
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$(call post_build,X310,1G)
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X300_1G:
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$(call ise_build,XC7K325T,$(GIGE_DEFS))
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$(call post_build,X300,1G)
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#1Gig on port0, 10Gig on port1
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X310_HG:
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$(call ise_build,XC7K410T,$(HYBRID_DEFS))
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$(call post_build,X310,HG)
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X300_HG:
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$(call ise_build,XC7K325T,$(HYBRID_DEFS))
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$(call post_build,X300,HG)
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#10Gig on both ports
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X310_XG:
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$(call ise_build,XC7K410T,$(XGIGE_DEFS))
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$(call post_build,X310,XG)
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X300_XG:
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$(call ise_build,XC7K325T,$(XGIGE_DEFS))
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$(call post_build,X300,XG)
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# 1Gig on port0, 10Gig on port1, SRAM Tx FIFO's
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X310_HGS:
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$(call ise_build,XC7K410T,$(HYBRID_SRAM_DEFS))
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$(call post_build,X310,HGS)
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X300_HGS:
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$(call ise_build,XC7K325T,$(HYBRID_SRAM_DEFS))
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$(call post_build,X300,HGS)
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# 10Gig on both ports, SRAM Tx FIFO's
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X310_XGS:
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$(call ise_build,XC7K410T,$(XGIGE_SRAM_DEFS))
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$(call post_build,X310,XGS)
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X300_XGS:
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$(call ise_build,XC7K325T,$(XGIGE_SRAM_DEFS))
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$(call post_build,X300,XGS)
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.PHONY: all clean
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@@ -1,183 +0,0 @@
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#
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# Copyright 2008-2012 Ettus Research LLC
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#
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##################################################
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# Project Setup
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##################################################
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TOP_MODULE = x300
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BUILD_DIR = build-$(NAME)
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# set me in a custom makefile
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CUSTOM_SRCS =
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CUSTOM_DEFS =
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##################################################
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# Include other makefiles
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##################################################
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include ../Makefile.common
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include coregen/Makefile.srcs
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include coregen_dsp/Makefile.srcs
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include ../../lib/control/Makefile.srcs
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include ../../lib/fifo/Makefile.srcs
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include ../../lib/simple_gemac/Makefile.srcs
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include ../../lib/timing/Makefile.srcs
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include ../../lib/zpu/Makefile.srcs
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include ../../lib/wishbone/Makefile.srcs
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include ../../lib/packet_proc/Makefile.srcs
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include ../../lib/vita/Makefile.srcs
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include ../../lib/xge/Makefile.srcs
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include ../../lib/xge_interface/Makefile.srcs
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include ../../lib/dsp/Makefile.srcs
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include ../../lib/io_port2/Makefile.srcs
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include ../../lib/axi/Makefile.srcs
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promgen: $(BIT_FILE)
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promgen -w -p bin -o $(BIN_FILE) -u 0 $<
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##################################################
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# Project Properties
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##################################################
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export PROJECT_PROPERTIES := \
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family "Kintex7" \
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device $(DEVICE) \
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package ffg900 \
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speed -2 \
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top_level_module_type "HDL" \
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synthesis_tool "XST (VHDL/Verilog)" \
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simulator "ISim (VHDL/Verilog)" \
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"Preferred Language" "Verilog" \
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"Enable Message Filtering" FALSE \
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"Display Incremental Messages" FALSE
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##################################################
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# Sources
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##################################################
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TOP_SRCS = \
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x300.v \
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x300_pcie_int.v \
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x300_core.v \
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x300_zpu_config.vhd \
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soft_ctrl.v \
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dbuf_bootram.v \
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capture_ddrlvds.v \
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gen_ddrlvds.v \
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radio.v \
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bus_int.v \
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x300.ucf \
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stc3.ucf \
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timing.ucf
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ONE_GIG_SRCS = $(COREGEN_ONE_GIG_SRCS) \
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gige_phy/gige_phy_mdio.v \
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gige_phy/gige_sfp_mdio_block.v \
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gige_phy/gige_sfp_mdio_reset_sync.v \
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gige_phy/gige_sfp_mdio_sync_block.v \
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gige_phy/transceiver/gige_sfp_mdio_transceiver.v \
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gige_phy/transceiver/gige_sfp_mdio_gtwizard.v \
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gige_phy/transceiver/gige_sfp_mdio_gtwizard_gt.v \
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gige_phy/transceiver/gige_sfp_mdio_gtwizard_init.v \
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gige_phy/transceiver/gige_sfp_mdio_tx_startup_fsm.v \
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gige_phy/transceiver/gige_sfp_mdio_rx_startup_fsm.v \
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gige_phy/transceiver/gige_sfp_mdio_recclk_monitor.v \
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TEN_GIG_SRCS = $(COREGEN_TEN_GIG_SRCS) \
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ten_gige_phy/ten_gig_eth_pcs_pma_x300_top.v \
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ten_gige_phy/ten_gig_eth_pcs_pma_x300_top.ucf \
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ten_gige_phy/ten_gig_eth_pcs_pma_block.v \
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ten_gige_phy/ten_gig_eth_pcs_pma_mod.v \
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ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gt_usrclk_source.v \
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ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v \
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ten_gige_phy/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser.v \
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ifeq ($(FLOORPLAN), 1)
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ifeq ($(DEVICE), XC7K325T)
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TOP_SRCS+=floorplan_X300.ucf
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endif
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ifeq ($(DEVICE), XC7K410T)
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TOP_SRCS+=floorplan_X310.ucf
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endif
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endif
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ifdef BUILD_10G
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ETH_SRCS+=$(abspath $(TEN_GIG_SRCS)) $(XGE_SRCS) $(XGE_INTERFACE_SRCS) $(abspath x300_10ge.ucf)
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endif
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ifdef BUILD_1G
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ETH_SRCS+=$(abspath $(ONE_GIG_SRCS)) $(abspath x300_1ge.ucf)
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endif
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ifdef ETH10G_PORT0
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ETH_SRCS+=$(abspath x300_10ge_port0.ucf)
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endif
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ifdef ETH10G_PORT1
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ETH_SRCS+=$(abspath x300_10ge_port1.ucf)
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endif
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ifndef NO_DRAM_FIFOS
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DRAM_SRCS= \
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$(abspath ddr3.ucf) \
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$(COREGEN_DRAM_SRCS)
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else
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DRAM_SRCS=
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endif
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SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
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$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
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$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(COREGEN_DSP_SRCS) \
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$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
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$(ZPU_CORE_SRCS) $(WISHBONE_SRCS) \
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$(ETH_SRCS) $(IOPORT2_SRCS) $(COREGEN_CHIPSCOPE_SRCS) \
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$(PACKET_PROC_SRCS) $(VITA_SRCS) $(DSP_SRCS) $(DRAM_SRCS) $(AXI_SRCS)
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##################################################
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# Process Properties
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##################################################
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SYNTHESIZE_PROPERTIES = \
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"Number of Clock Buffers" 8 \
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"Pack I/O Registers into IOBs" Yes \
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"Optimization Effort" High \
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"Optimize Instantiated Primitives" TRUE \
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"Register Balancing" Yes \
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"Use Clock Enable" Auto \
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"Use Synchronous Reset" Auto \
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"Use Synchronous Set" Auto \
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"Verilog Macros" "$(EXTRA_DEFS) $(CUSTOM_DEFS)"
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TRANSLATE_PROPERTIES = \
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"Macro Search Path" "$(shell pwd)/coregen"
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MAP_PROPERTIES = \
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"Generate Detailed MAP Report" TRUE \
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"Allow Logic Optimization Across Hierarchy" TRUE \
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"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
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"Combinatorial Logic Optimization" TRUE \
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"Register Duplication" On \
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"Placer Effort Level" High \
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"Placer Extra Effort" Normal \
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"Enable Multi-Threading" 2 \
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"Starting Placer Cost Table (1-100)" $(shell awk 'BEGIN{srand();printf("%d", (100*rand()%100)+1)}')
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PLACE_ROUTE_PROPERTIES = \
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"Place & Route Effort Level (Overall)" High \
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"Extra Effort (Highest PAR level only)" Normal \
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"Enable Multi-Threading" 4
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STATIC_TIMING_PROPERTIES = \
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"Number of Paths in Error/Verbose Report" 10 \
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"Report Type" "Error Report"
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GEN_PROG_FILE_PROPERTIES = \
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"Configuration Rate" 6 \
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"Create Binary Configuration File" TRUE \
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"Done (Output Events)" 5 \
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"Enable Bitstream Compression" FALSE \
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"Enable Outputs (Output Events)" 6 \
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"Wait for DCI Match (Output Events)" NoWait
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SIM_MODEL_PROPERTIES = ""
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@@ -1,623 +0,0 @@
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//
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// Copyright 2013 Ettus Research LLC
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//
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`define LOG2(N) (\
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N < 2 ? 0 : \
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N < 4 ? 1 : \
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N < 8 ? 2 : \
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N < 16 ? 3 : \
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N < 32 ? 4 : \
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N < 64 ? 5 : \
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N < 128 ? 6 : \
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N < 256 ? 7 : \
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N < 512 ? 8 : \
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N < 1024 ? 9 : \
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10)
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module bus_int
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#(
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parameter dw = 32, // Data bus width
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parameter aw = 16, // Address bus width, for byte addressibility, 16 = 64K byte memory space
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parameter sw = 4 // Select width -- 32-bit data bus with 8-bit granularity.
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)
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(input clk, input reset,
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output sen, output sclk, output mosi, input miso,
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inout scl0, inout sda0,
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inout scl1, inout sda1,
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inout scl2, inout sda2,
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output gps_txd, input gps_rxd,
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output debug_txd, input debug_rxd,
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output [7:0] leds,
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output [3:0] sw_rst,
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// SFP+ 0
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input SFPP0_ModAbs,
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input SFPP0_TxFault, // Current 10G PMA/PCS apparently ignores this signal.
|
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input SFPP0_RxLOS,
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inout SFPP0_RS0,
|
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inout SFPP0_RS1,
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// SFP+ 1
|
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input SFPP1_ModAbs,
|
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input SFPP1_TxFault, // Current 10G PMA/PCS apparently ignores this signal.
|
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input SFPP1_RxLOS,
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inout SFPP1_RS0,
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inout SFPP1_RS1,
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//
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input [4:0] clock_status,
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output [6:0] clock_control,
|
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// ETH0
|
||||
output [63:0] eth0_tx_tdata, output [3:0] eth0_tx_tuser, output eth0_tx_tlast, output eth0_tx_tvalid, input eth0_tx_tready,
|
||||
input [63:0] eth0_rx_tdata, input [3:0] eth0_rx_tuser, input eth0_rx_tlast, input eth0_rx_tvalid, output eth0_rx_tready,
|
||||
// ETH1
|
||||
output [63:0] eth1_tx_tdata, output [3:0] eth1_tx_tuser, output eth1_tx_tlast, output eth1_tx_tvalid, input eth1_tx_tready,
|
||||
input [63:0] eth1_rx_tdata, input [3:0] eth1_rx_tuser, input eth1_rx_tlast, input eth1_rx_tvalid, output eth1_rx_tready,
|
||||
// Radio0
|
||||
output [63:0] r0o_tdata, output r0o_tlast, output r0o_tvalid, input r0o_tready,
|
||||
input [63:0] r0i_tdata, input r0i_tlast, input r0i_tvalid, output r0i_tready,
|
||||
// Radio1
|
||||
output [63:0] r1o_tdata, output r1o_tlast, output r1o_tvalid, input r1o_tready,
|
||||
input [63:0] r1i_tdata, input r1i_tlast, input r1i_tvalid, output r1i_tready,
|
||||
// CE0
|
||||
output [63:0] ce0o_tdata, output ce0o_tlast, output ce0o_tvalid, input ce0o_tready,
|
||||
input [63:0] ce0i_tdata, input ce0i_tlast, input ce0i_tvalid, output ce0i_tready,
|
||||
// CE1
|
||||
output [63:0] ce1o_tdata, output ce1o_tlast, output ce1o_tvalid, input ce1o_tready,
|
||||
input [63:0] ce1i_tdata, input ce1i_tlast, input ce1i_tvalid, output ce1i_tready,
|
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// CE2
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||||
output [63:0] ce2o_tdata, output ce2o_tlast, output ce2o_tvalid, input ce2o_tready,
|
||||
input [63:0] ce2i_tdata, input ce2i_tlast, input ce2i_tvalid, output ce2i_tready,
|
||||
//iop2 message fifos
|
||||
output [63:0] o_iop2_msg_tdata, output o_iop2_msg_tvalid, output o_iop2_msg_tlast, input o_iop2_msg_tready,
|
||||
input [63:0] i_iop2_msg_tdata, input i_iop2_msg_tvalid, input i_iop2_msg_tlast, output i_iop2_msg_tready,
|
||||
// PCIe
|
||||
output [63:0] pcio_tdata, output pcio_tlast, output pcio_tvalid, input pcio_tready,
|
||||
input [63:0] pcii_tdata, input pcii_tlast, input pcii_tvalid, output pcii_tready,
|
||||
//------------------------------------------------------------------
|
||||
// Wishbone Slave Interface(s)
|
||||
//------------------------------------------------------------------
|
||||
input [dw-1:0] s4_dat_i,
|
||||
output [dw-1:0] s4_dat_o,
|
||||
output [aw-1:0] s4_adr,
|
||||
output [sw-1:0] s4_sel,
|
||||
input s4_ack,
|
||||
output s4_stb,
|
||||
output s4_cyc,
|
||||
output s4_we,
|
||||
input s4_int, // IJB. Nothing to connect this too!! No IRQ controller on x300.
|
||||
|
||||
input [dw-1:0] s5_dat_i,
|
||||
output [dw-1:0] s5_dat_o,
|
||||
output [aw-1:0] s5_adr,
|
||||
output [sw-1:0] s5_sel,
|
||||
input s5_ack,
|
||||
output s5_stb,
|
||||
output s5_cyc,
|
||||
output s5_we,
|
||||
input s5_int, // IJB. Nothing to connect this too!! No IRQ controller on x300.
|
||||
|
||||
// AXI_DRAM_FIFO BIST. Not for production.
|
||||
output bist_start,
|
||||
output [15:0] bist_control,
|
||||
input bist_done,
|
||||
input bist_fail,
|
||||
|
||||
|
||||
// Debug
|
||||
input [3:0] fifo_flags,
|
||||
output [31:0] debug0,
|
||||
output [31:0] debug1,
|
||||
output [127:0] debug2);
|
||||
|
||||
localparam SR_AWIDTH = 8;
|
||||
localparam RB_AWIDTH = 8;
|
||||
|
||||
localparam SR_LEDS = 8'd00;
|
||||
localparam SR_SW_RST = 8'd01;
|
||||
localparam SR_CLOCK_CTRL = 8'd02;
|
||||
localparam SR_XB_LOCAL = 8'd03;
|
||||
localparam SR_SFPP_CTRL0 = 8'd08;
|
||||
localparam SR_SFPP_CTRL1 = 8'd09;
|
||||
localparam SR_FIFOFLAGS = 8'd10;
|
||||
localparam SR_SPI = 8'd32;
|
||||
localparam SR_ETHINT0 = 8'd40;
|
||||
localparam SR_ETHINT1 = 8'd56;
|
||||
// For AXI_DRAM_FIFO debug, not production
|
||||
localparam SR_BIST = 8'd128;
|
||||
|
||||
|
||||
localparam RB_COUNTER = 8'd00;
|
||||
localparam RB_SPI_RDY = 8'd01;
|
||||
localparam RB_SPI_DATA = 8'd02;
|
||||
localparam RB_CLK_STATUS = 8'd03;
|
||||
localparam RB_ETH_TYPE0 = 8'd04;
|
||||
localparam RB_ETH_TYPE1 = 8'd05;
|
||||
localparam RB_COMPAT_NUM = 8'd06;
|
||||
|
||||
localparam RB_SFPP_STATUS0 = 8'd08;
|
||||
localparam RB_SFPP_STATUS1 = 8'd09;
|
||||
localparam RB_FIFOFLAGS = 8'd10;
|
||||
localparam RB_CROSSBAR = 8'd64; // Block of 64 addresses start here.
|
||||
// For AXI_DRAM_FIFO debug, not production
|
||||
localparam RB_BIST = 8'd128;
|
||||
|
||||
|
||||
localparam COMPAT_MAJOR = 16'h0007;
|
||||
localparam COMPAT_MINOR = 16'h0000;
|
||||
|
||||
wire [31:0] set_data;
|
||||
wire [7:0] set_addr;
|
||||
reg [31:0] rb_data;
|
||||
wire [RB_AWIDTH-1:0] rb_addr;
|
||||
wire rb_rd_stb;
|
||||
wire set_stb;
|
||||
wire spi_ready;
|
||||
wire [31:0] rb_spi_data;
|
||||
wire [17:0] eth_debug_flags;
|
||||
|
||||
|
||||
// ZPU in and ZPU out axi streams
|
||||
wire [63:0] zpui_tdata, zpuo_tdata;
|
||||
wire [3:0] zpui_tuser, zpuo_tuser;
|
||||
wire zpui_tlast, zpuo_tlast, zpui_tvalid, zpuo_tvalid, zpui_tready, zpuo_tready;
|
||||
wire [63:0] zpui0_tdata, zpuo0_tdata;
|
||||
wire [3:0] zpui0_tuser, zpuo0_tuser;
|
||||
wire zpui0_tlast, zpuo0_tlast, zpui0_tvalid, zpuo0_tvalid, zpui0_tready, zpuo0_tready;
|
||||
wire [63:0] zpui1_tdata, zpuo1_tdata;
|
||||
wire [3:0] zpui1_tuser, zpuo1_tuser;
|
||||
wire zpui1_tlast, zpuo1_tlast, zpui1_tvalid, zpuo1_tvalid, zpui1_tready, zpuo1_tready;
|
||||
|
||||
// v2e (vita to ethernet) and e2v (eth to vita)
|
||||
wire [63:0] v2e0_tdata, v2e1_tdata, e2v0_tdata, e2v1_tdata;
|
||||
wire v2e0_tlast, v2e1_tlast, v2e0_tvalid, v2e1_tvalid, v2e0_tready, v2e1_tready;
|
||||
wire e2v0_tlast, e2v1_tlast, e2v0_tvalid, e2v1_tvalid, e2v0_tready, e2v1_tready;
|
||||
|
||||
//settings bus for crossbar router
|
||||
wire [31:0] set_data_xb;
|
||||
wire [8:0] set_addr_xb;
|
||||
wire set_stb_xb;
|
||||
|
||||
// SFP+ logic
|
||||
reg SFPP0_ModAbs_reg, SFPP0_TxFault_reg,SFPP0_RxLOS_reg;
|
||||
reg SFPP0_ModAbs_reg2, SFPP0_TxFault_reg2,SFPP0_RxLOS_reg2;
|
||||
reg SFPP0_ModAbs_chgd, SFPP0_TxFault_chgd, SFPP0_RxLOS_chgd;
|
||||
|
||||
reg SFPP1_ModAbs_reg, SFPP1_TxFault_reg,SFPP1_RxLOS_reg;
|
||||
reg SFPP1_ModAbs_reg2, SFPP1_TxFault_reg2,SFPP1_RxLOS_reg2;
|
||||
reg SFPP1_ModAbs_chgd, SFPP1_TxFault_chgd, SFPP1_RxLOS_chgd;
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
// Soft CPU - drives network setup, soft reset, ICMP, ...
|
||||
////////////////////////////////////////////////////////////////////
|
||||
soft_ctrl #(.SB_ADDRW(SR_AWIDTH), .RB_ADDRW(RB_AWIDTH)) sc
|
||||
(
|
||||
.clk(clk), .rst(reset),
|
||||
//------------------------------------------------------------------
|
||||
// I2C interfaces
|
||||
//------------------------------------------------------------------
|
||||
.scl0(scl0), .sda0(sda0),
|
||||
.scl1(scl1), .sda1(sda1),
|
||||
.scl2(scl2), .sda2(sda2),
|
||||
//------------------------------------------------------------------
|
||||
// UARTs for CPU comms
|
||||
//------------------------------------------------------------------
|
||||
.gps_rxd(gps_rxd), .gps_txd(gps_txd),
|
||||
.debug_rxd(debug_rxd), .debug_txd(debug_txd),
|
||||
//------------------------------------------------------------------
|
||||
// settings bus interface
|
||||
//------------------------------------------------------------------
|
||||
.set_stb(set_stb),
|
||||
.set_addr(set_addr),
|
||||
.set_data(set_data),
|
||||
//------------------------------------------------------------------
|
||||
// settings bus interface for crossbar router
|
||||
//------------------------------------------------------------------
|
||||
.set_stb_xb(set_stb_xb),
|
||||
.set_addr_xb(set_addr_xb),
|
||||
.set_data_xb(set_data_xb),
|
||||
//------------------------------------------------------------------
|
||||
// readback bus interface
|
||||
//------------------------------------------------------------------
|
||||
.rb_addr(rb_addr),
|
||||
.rb_data(rb_data),
|
||||
.rb_rd_stb(rb_rd_stb),
|
||||
//------------------------------------------------------------------
|
||||
// packet interface in
|
||||
//------------------------------------------------------------------
|
||||
.rx_tdata(zpui_tdata),
|
||||
.rx_tuser(zpui_tuser),
|
||||
.rx_tlast(zpui_tlast),
|
||||
.rx_tvalid(zpui_tvalid),
|
||||
.rx_tready(zpui_tready),
|
||||
//------------------------------------------------------------------
|
||||
// packet interface out
|
||||
//------------------------------------------------------------------
|
||||
.tx_tdata(zpuo_tdata),
|
||||
.tx_tuser(zpuo_tuser),
|
||||
.tx_tlast(zpuo_tlast),
|
||||
.tx_tvalid(zpuo_tvalid),
|
||||
.tx_tready(zpuo_tready),
|
||||
//------------------------------------------------------------------
|
||||
// Wishbone Slave Interface(s)
|
||||
//------------------------------------------------------------------
|
||||
.s4_dat_i(s4_dat_i),
|
||||
.s4_dat_o(s4_dat_o),
|
||||
.s4_adr(s4_adr),
|
||||
.s4_sel(s4_sel),
|
||||
.s4_ack(s4_ack),
|
||||
.s4_stb(s4_stb),
|
||||
.s4_cyc(s4_cyc),
|
||||
.s4_we(s4_we),
|
||||
.s4_int(s4_int),
|
||||
//------------------------------------------------------------------
|
||||
// IoPort2 Msg Interface
|
||||
//------------------------------------------------------------------
|
||||
.o_iop2_msg_tdata(o_iop2_msg_tdata),
|
||||
.o_iop2_msg_tvalid(o_iop2_msg_tvalid),
|
||||
.o_iop2_msg_tlast(o_iop2_msg_tlast),
|
||||
.o_iop2_msg_tready(o_iop2_msg_tready),
|
||||
.i_iop2_msg_tdata(i_iop2_msg_tdata),
|
||||
.i_iop2_msg_tvalid(i_iop2_msg_tvalid),
|
||||
.i_iop2_msg_tlast(i_iop2_msg_tlast),
|
||||
.i_iop2_msg_tready(i_iop2_msg_tready),
|
||||
|
||||
.s5_dat_i(s5_dat_i),
|
||||
.s5_dat_o(s5_dat_o),
|
||||
.s5_adr(s5_adr),
|
||||
.s5_sel(s5_sel),
|
||||
.s5_ack(s5_ack),
|
||||
.s5_stb(s5_stb),
|
||||
.s5_cyc(s5_cyc),
|
||||
.s5_we(s5_we),
|
||||
.s5_int(s5_int),
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// Debug
|
||||
//------------------------------------------------------------------
|
||||
.debug0(debug2),
|
||||
.debug1()
|
||||
);
|
||||
|
||||
setting_reg #(.my_addr(SR_LEDS), .awidth(SR_AWIDTH), .width(8)) set_leds
|
||||
(.clk(clk), .rst(reset),
|
||||
.strobe(set_stb), .addr(set_addr), .in(set_data),
|
||||
.out(leds));
|
||||
|
||||
//
|
||||
// SW_RST - Bit allocation:
|
||||
// [0] - PHY reset
|
||||
// [1] - Radio clk domain reset
|
||||
// [2] - Radio Clk PLL reset.
|
||||
// [3] - Usused.
|
||||
//
|
||||
setting_reg #(.my_addr(SR_SW_RST), .awidth(SR_AWIDTH), .width(4)) set_sw_rst
|
||||
(.clk(clk), .rst(reset),
|
||||
.strobe(set_stb), .addr(set_addr), .in(set_data),
|
||||
.out(sw_rst));
|
||||
|
||||
setting_reg #(.my_addr(SR_CLOCK_CTRL), .awidth(SR_AWIDTH), .width(7),
|
||||
.at_reset(7'b1000000) //bit 6 high means GPSDO on by default
|
||||
) set_clk_ctrl
|
||||
(.clk(clk), .rst(reset),
|
||||
.strobe(set_stb), .addr(set_addr), .in(set_data),
|
||||
.out(clock_control));
|
||||
|
||||
simple_spi_core #(.BASE(SR_SPI), .WIDTH(1), .CLK_IDLE(0), .SEN_IDLE(1'b1)) misc_spi
|
||||
(.clock(clk), .reset(reset),
|
||||
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
|
||||
.readback(rb_spi_data), .ready(spi_ready),
|
||||
.sen(sen), .sclk(sclk), .mosi(mosi), .miso(miso),
|
||||
.debug());
|
||||
|
||||
//
|
||||
// Provide instrumentation so that abnormal FIFO conditions can be identifed.
|
||||
//
|
||||
wire clear_debug_flags;
|
||||
reg [31:0] debug_flags;
|
||||
|
||||
setting_reg #(.my_addr(SR_FIFOFLAGS), .awidth(16), .width(1)) sr_reset_fifo_debug
|
||||
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
|
||||
.in(set_data),.out(),.changed(clear_debug_flags));
|
||||
|
||||
always @(posedge clk)
|
||||
if (reset)
|
||||
debug_flags <= 0;
|
||||
else if (clear_debug_flags)
|
||||
debug_flags <= 0;
|
||||
else
|
||||
debug_flags <= debug_flags | {
|
||||
10'h0,
|
||||
~fifo_flags[3:0],
|
||||
eth_debug_flags};
|
||||
|
||||
reg [31:0] counter;
|
||||
wire [31:0] rb_data_crossbar;
|
||||
|
||||
always @(posedge clk) counter <= counter + 1;
|
||||
|
||||
always @*
|
||||
casex (rb_addr)
|
||||
RB_COMPAT_NUM: rb_data = {COMPAT_MAJOR, COMPAT_MINOR};
|
||||
RB_COUNTER: rb_data = counter;
|
||||
RB_SPI_RDY: rb_data = {31'b0, spi_ready};
|
||||
RB_SPI_DATA: rb_data = rb_spi_data;
|
||||
RB_CLK_STATUS: rb_data = {27'b0, clock_status};
|
||||
// SFPP Interface pins.
|
||||
RB_SFPP_STATUS0: rb_data = {26'b0,SFPP0_ModAbs_chgd,SFPP0_TxFault_chgd,SFPP0_RxLOS_chgd,
|
||||
SFPP0_ModAbs_reg2,SFPP0_TxFault_reg2,SFPP0_RxLOS_reg2};
|
||||
RB_SFPP_STATUS1: rb_data = {26'b0,SFPP1_ModAbs_chgd,SFPP1_TxFault_chgd,SFPP1_RxLOS_chgd,
|
||||
SFPP1_ModAbs_reg2,SFPP1_TxFault_reg2,SFPP1_RxLOS_reg2};
|
||||
// Allow readback of configured ethernet interfaces.
|
||||
`ifdef ETH10G_PORT0
|
||||
RB_ETH_TYPE0: rb_data = {32'h1};
|
||||
`else
|
||||
RB_ETH_TYPE0: rb_data = {32'h0};
|
||||
`endif
|
||||
`ifdef ETH10G_PORT1
|
||||
RB_ETH_TYPE1: rb_data = {32'h1};
|
||||
`else
|
||||
RB_ETH_TYPE1: rb_data = {32'h0};
|
||||
`endif
|
||||
// Read FIFO status from Ethernet Interfaces
|
||||
RB_FIFOFLAGS: rb_data = debug_flags;
|
||||
|
||||
(RB_CROSSBAR | 6'bxxxxxx): rb_data = rb_data_crossbar;
|
||||
// AXI_DRAM_FIFO BIST. Not for production.
|
||||
RB_BIST: rb_data = {29'h0,bist_done,bist_fail,bist_start};
|
||||
|
||||
|
||||
default: rb_data = 32'h0;
|
||||
endcase // case (rb_addr)
|
||||
|
||||
// AXI_DRAM_FIFO BIST. Not for production.
|
||||
setting_reg #(.my_addr(SR_BIST), .awidth(SR_AWIDTH), .width(17)) set_bist_start
|
||||
(.clk(clk), .rst(reset),
|
||||
.strobe(set_stb), .addr(set_addr), .in(set_data),
|
||||
.out({bist_start,bist_control}));
|
||||
|
||||
// Latch state changes to SFP+ pins.
|
||||
always @(posedge clk)
|
||||
begin
|
||||
SFPP0_ModAbs_reg <= SFPP0_ModAbs;
|
||||
SFPP0_TxFault_reg <= SFPP0_TxFault;
|
||||
SFPP0_RxLOS_reg <= SFPP0_RxLOS;
|
||||
SFPP0_ModAbs_reg2 <= SFPP0_ModAbs_reg;
|
||||
SFPP0_TxFault_reg2 <= SFPP0_TxFault_reg;
|
||||
SFPP0_RxLOS_reg2 <= SFPP0_RxLOS_reg;
|
||||
if (rb_rd_stb && (rb_addr == RB_SFPP_STATUS0) ) begin
|
||||
SFPP0_ModAbs_chgd <= 1'b0;
|
||||
SFPP0_TxFault_chgd <= 1'b0;
|
||||
SFPP0_RxLOS_chgd <= 1'b0;
|
||||
end else begin
|
||||
if (SFPP0_ModAbs_reg2 != SFPP0_ModAbs_reg)
|
||||
SFPP0_ModAbs_chgd <= 1'b1;
|
||||
if (SFPP0_TxFault_reg2 != SFPP0_TxFault_reg)
|
||||
SFPP0_TxFault_chgd <= 1'b1;
|
||||
if (SFPP0_RxLOS_reg2 != SFPP0_RxLOS_reg)
|
||||
SFPP0_RxLOS_chgd <= 1'b1;
|
||||
end // else: !if(rb_rd_stb && (rb_addr == RB_SFPP_STATUS0) )
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
SFPP1_ModAbs_reg <= SFPP1_ModAbs;
|
||||
SFPP1_TxFault_reg <= SFPP1_TxFault;
|
||||
SFPP1_RxLOS_reg <= SFPP1_RxLOS;
|
||||
SFPP1_ModAbs_reg2 <= SFPP1_ModAbs_reg;
|
||||
SFPP1_TxFault_reg2 <= SFPP1_TxFault_reg;
|
||||
SFPP1_RxLOS_reg2 <= SFPP1_RxLOS_reg;
|
||||
if (rb_rd_stb && (rb_addr == RB_SFPP_STATUS1) ) begin
|
||||
SFPP1_ModAbs_chgd <= 1'b0;
|
||||
SFPP1_TxFault_chgd <= 1'b0;
|
||||
SFPP1_RxLOS_chgd <= 1'b0;
|
||||
end else begin
|
||||
if (SFPP1_ModAbs_reg2 != SFPP1_ModAbs_reg)
|
||||
SFPP1_ModAbs_chgd <= 1'b1;
|
||||
if (SFPP1_TxFault_reg2 != SFPP1_TxFault_reg)
|
||||
SFPP1_TxFault_chgd <= 1'b1;
|
||||
if (SFPP1_RxLOS_reg2 != SFPP1_RxLOS_reg)
|
||||
SFPP1_RxLOS_chgd <= 1'b1;
|
||||
end // else: !if(rb_rd_stb && (rb_addr == RB_SFPP_STATUS1) )
|
||||
end
|
||||
|
||||
wire [1:0] sfpp0_ctrl;
|
||||
|
||||
// SFPP_RS0/1 pins are open drain.
|
||||
setting_reg #(.my_addr(SR_SFPP_CTRL0), .awidth(SR_AWIDTH), .width(2), .at_reset(2'b00)) set_sfpp0_ctrl
|
||||
(.clk(clk), .rst(reset),
|
||||
.strobe(set_stb), .addr(set_addr), .in(set_data),
|
||||
.out(sfpp0_ctrl));
|
||||
|
||||
assign SFPP0_RS0 = sfpp0_ctrl[0] ? 1'b0 : 1'bz;
|
||||
assign SFPP0_RS1 = sfpp0_ctrl[1] ? 1'b0 : 1'bz;
|
||||
|
||||
wire [1:0] sfpp1_ctrl;
|
||||
|
||||
// SFPP1_RS0/1 pins are open drain.
|
||||
setting_reg #(.my_addr(SR_SFPP_CTRL1), .awidth(SR_AWIDTH), .width(2), .at_reset(2'b00)) set_sfpp1_ctrl
|
||||
(.clk(clk), .rst(reset),
|
||||
.strobe(set_stb), .addr(set_addr), .in(set_data),
|
||||
.out(sfpp1_ctrl));
|
||||
|
||||
assign SFPP1_RS0 = sfpp1_ctrl[0] ? 1'b0 : 1'bz;
|
||||
assign SFPP1_RS1 = sfpp1_ctrl[1] ? 1'b0 : 1'bz;
|
||||
|
||||
|
||||
//assign debug = { 9'b0, set_stb, spi_ready, i2c_ready, sen, sclk, mosi, miso, set_addr[7:0], state[7:0]};
|
||||
|
||||
// ////////////////////////////////////////////////////////////////
|
||||
// ETH interfaces
|
||||
|
||||
wire [63:0] e01_tdata, e10_tdata;
|
||||
wire [3:0] e01_tuser, e10_tuser;
|
||||
wire e01_tlast, e01_tvalid, e01_tready;
|
||||
wire e10_tlast, e10_tvalid, e10_tready;
|
||||
|
||||
eth_interface #(.BASE(SR_ETHINT0)) eth_interface0
|
||||
(.clk(clk), .reset(reset), .clear(clear),
|
||||
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
|
||||
.eth_tx_tdata(eth0_tx_tdata), .eth_tx_tuser(eth0_tx_tuser), .eth_tx_tlast(eth0_tx_tlast),
|
||||
.eth_tx_tvalid(eth0_tx_tvalid), .eth_tx_tready(eth0_tx_tready),
|
||||
.eth_rx_tdata(eth0_rx_tdata), .eth_rx_tuser(eth0_rx_tuser), .eth_rx_tlast(eth0_rx_tlast),
|
||||
.eth_rx_tvalid(eth0_rx_tvalid), .eth_rx_tready(eth0_rx_tready),
|
||||
.e2v_tdata(e2v0_tdata), .e2v_tlast(e2v0_tlast), .e2v_tvalid(e2v0_tvalid), .e2v_tready(e2v0_tready),
|
||||
.v2e_tdata(v2e0_tdata), .v2e_tlast(v2e0_tlast), .v2e_tvalid(v2e0_tvalid), .v2e_tready(v2e0_tready),
|
||||
.xo_tdata(e01_tdata), .xo_tuser(e01_tuser), .xo_tlast(e01_tlast), .xo_tvalid(e01_tvalid), .xo_tready(e01_tready),
|
||||
.xi_tdata(e10_tdata), .xi_tuser(e10_tuser), .xi_tlast(e10_tlast), .xi_tvalid(e10_tvalid), .xi_tready(e10_tready),
|
||||
.e2z_tdata(zpui0_tdata), .e2z_tuser(zpui0_tuser), .e2z_tlast(zpui0_tlast), .e2z_tvalid(zpui0_tvalid), .e2z_tready(zpui0_tready),
|
||||
.z2e_tdata(zpuo0_tdata), .z2e_tuser(zpuo0_tuser), .z2e_tlast(zpuo0_tlast), .z2e_tvalid(zpuo0_tvalid), .z2e_tready(zpuo0_tready),
|
||||
.debug_flags(eth_debug_flags[8:0]),.debug(/*debug2*/));
|
||||
|
||||
eth_interface #(.BASE(SR_ETHINT1)) eth_interface1
|
||||
(.clk(clk), .reset(reset), .clear(clear),
|
||||
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
|
||||
.eth_tx_tdata(eth1_tx_tdata), .eth_tx_tuser(eth1_tx_tuser), .eth_tx_tlast(eth1_tx_tlast),
|
||||
.eth_tx_tvalid(eth1_tx_tvalid), .eth_tx_tready(eth1_tx_tready),
|
||||
.eth_rx_tdata(eth1_rx_tdata), .eth_rx_tuser(eth1_rx_tuser), .eth_rx_tlast(eth1_rx_tlast),
|
||||
.eth_rx_tvalid(eth1_rx_tvalid), .eth_rx_tready(eth1_rx_tready),
|
||||
.e2v_tdata(e2v1_tdata), .e2v_tlast(e2v1_tlast), .e2v_tvalid(e2v1_tvalid), .e2v_tready(e2v1_tready),
|
||||
.v2e_tdata(v2e1_tdata), .v2e_tlast(v2e1_tlast), .v2e_tvalid(v2e1_tvalid), .v2e_tready(v2e1_tready),
|
||||
.xo_tdata(e10_tdata), .xo_tuser(e10_tuser), .xo_tlast(e10_tlast), .xo_tvalid(e10_tvalid), .xo_tready(e10_tready),
|
||||
.xi_tdata(e01_tdata), .xi_tuser(e01_tuser), .xi_tlast(e01_tlast), .xi_tvalid(e01_tvalid), .xi_tready(e01_tready),
|
||||
.e2z_tdata(zpui1_tdata), .e2z_tuser(zpui1_tuser), .e2z_tlast(zpui1_tlast), .e2z_tvalid(zpui1_tvalid), .e2z_tready(zpui1_tready),
|
||||
.z2e_tdata(zpuo1_tdata), .z2e_tuser(zpuo1_tuser), .z2e_tlast(zpuo1_tlast), .z2e_tvalid(zpuo1_tvalid), .z2e_tready(zpuo1_tready),
|
||||
.debug_flags(eth_debug_flags[17:9]),.debug());
|
||||
|
||||
axi_mux4 #(.PRIO(0), .WIDTH(68)) zpui_mux
|
||||
(.clk(clk), .reset(reset), .clear(clear),
|
||||
.i0_tdata({zpui0_tuser,zpui0_tdata}), .i0_tlast(zpui0_tlast), .i0_tvalid(zpui0_tvalid), .i0_tready(zpui0_tready),
|
||||
.i1_tdata({zpui1_tuser,zpui1_tdata}), .i1_tlast(zpui1_tlast), .i1_tvalid(zpui1_tvalid), .i1_tready(zpui1_tready),
|
||||
.i2_tdata(68'h0), .i2_tlast(1'b0), .i2_tvalid(1'b0), .i2_tready(),
|
||||
.i3_tdata(68'h0), .i3_tlast(1'b0), .i3_tvalid(1'b0), .i3_tready(),
|
||||
.o_tdata({zpui_tuser,zpui_tdata}), .o_tlast(zpui_tlast), .o_tvalid(zpui_tvalid), .o_tready(zpui_tready));
|
||||
|
||||
// Demux ZPU to Eth output by the port number in top 8 bits of data on first line
|
||||
wire [67:0] zpuo_eth_header;
|
||||
wire [1:0] zpuo_eth_dest = (zpuo_eth_header[63:56] == 8'd0) ? 2'b00 : 2'b01;
|
||||
|
||||
axi_demux4 #(.ACTIVE_CHAN(4'b0011), .WIDTH(68)) zpuo_demux
|
||||
(.clk(clk), .reset(reset), .clear(clear),
|
||||
.header(zpuo_eth_header), .dest(zpuo_eth_dest),
|
||||
.i_tdata({zpuo_tuser,zpuo_tdata}), .i_tlast(zpuo_tlast), .i_tvalid(zpuo_tvalid), .i_tready(zpuo_tready),
|
||||
.o0_tdata({zpuo0_tuser,zpuo0_tdata}), .o0_tlast(zpuo0_tlast), .o0_tvalid(zpuo0_tvalid), .o0_tready(zpuo0_tready),
|
||||
.o1_tdata({zpuo1_tuser,zpuo1_tdata}), .o1_tlast(zpuo1_tlast), .o1_tvalid(zpuo1_tvalid), .o1_tready(zpuo1_tready),
|
||||
.o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b1),
|
||||
.o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b1));
|
||||
|
||||
// //////////////////////////////////////////////////////////////////////
|
||||
// axi_crossbar ports
|
||||
// 0 - ETH0
|
||||
// 1 - ETH1
|
||||
// 2 - Radio0
|
||||
// 3 - Radio1
|
||||
// 4 - CE0
|
||||
// 5 - CE1
|
||||
// 6 - CE2
|
||||
// 7 - PCIe
|
||||
|
||||
wire [7:0] local_addr;
|
||||
|
||||
setting_reg #(.my_addr(SR_XB_LOCAL), .awidth(SR_AWIDTH), .width(8)) sr_local_addr
|
||||
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
|
||||
.in(set_data),.out(local_addr),.changed());
|
||||
|
||||
|
||||
localparam CROSSBAR_IN = 8;
|
||||
localparam CROSSBAR_OUT = 8;
|
||||
|
||||
axi_crossbar #(.FIFO_WIDTH(64), .DST_WIDTH(16), .NUM_INPUTS(CROSSBAR_IN), .NUM_OUTPUTS(CROSSBAR_OUT)) axi_crossbar
|
||||
(.clk(clk), .reset(reset), .clear(0),
|
||||
.local_addr(local_addr),
|
||||
.set_stb(set_stb_xb), .set_addr(set_addr_xb), .set_data(set_data_xb),
|
||||
.i_tdata({pcii_tdata,ce2i_tdata,ce1i_tdata,ce0i_tdata,r1i_tdata,r0i_tdata,e2v1_tdata,e2v0_tdata}),
|
||||
.i_tlast({pcii_tlast,ce2i_tlast,ce1i_tlast,ce0i_tlast,r1i_tlast,r0i_tlast,e2v1_tlast,e2v0_tlast}),
|
||||
.i_tvalid({pcii_tvalid,ce2i_tvalid,ce1i_tvalid,ce0i_tvalid,r1i_tvalid,r0i_tvalid,e2v1_tvalid,e2v0_tvalid}),
|
||||
.i_tready({pcii_tready,ce2i_tready,ce1i_tready,ce0i_tready,r1i_tready,r0i_tready,e2v1_tready,e2v0_tready}),
|
||||
.o_tdata({pcio_tdata,ce2o_tdata,ce1o_tdata,ce0o_tdata,r1o_tdata,r0o_tdata,v2e1_tdata,v2e0_tdata}),
|
||||
.o_tlast({pcio_tlast,ce2o_tlast,ce1o_tlast,ce0o_tlast,r1o_tlast,r0o_tlast,v2e1_tlast,v2e0_tlast}),
|
||||
.o_tvalid({pcio_tvalid,ce2o_tvalid,ce1o_tvalid,ce0o_tvalid,r1o_tvalid,r0o_tvalid,v2e1_tvalid,v2e0_tvalid}),
|
||||
.o_tready({pcio_tready,ce2o_tready,ce1o_tready,ce0o_tready,r1o_tready,r0o_tready,v2e1_tready,v2e0_tready}),
|
||||
.pkt_present({pcii_tvalid,ce2i_tvalid,ce1i_tvalid,ce0i_tvalid,r1i_tvalid,r0i_tvalid,e2v1_tvalid,e2v0_tvalid}),
|
||||
.rb_rd_stb(rb_rd_stb && ((rb_addr >> (`LOG2(NUM_OUTPUTS)+`LOG2(NUM_INPUTS))) == RB_CROSSBAR >> (`LOG2(NUM_OUTPUTS)+`LOG2(NUM_INPUTS)))),
|
||||
.rb_addr(rb_addr[`LOG2(CROSSBAR_IN)+`LOG2(CROSSBAR_OUT)-1:0]), .rb_data(rb_data_crossbar)
|
||||
);
|
||||
|
||||
/*
|
||||
assign debug2 = {
|
||||
pcii_tdata[31:0], //[127:92]
|
||||
pcio_tdata[31:0], //[91:64]
|
||||
local_addr[5:0], //[63:58]
|
||||
set_stb_xb, //[57]
|
||||
set_addr_xb, //[56:48]
|
||||
pcii_tvalid,ce2i_tvalid,ce1i_tvalid,ce0i_tvalid,r1i_tvalid,r0i_tvalid,e2v1_tvalid,e2v0_tvalid, //[47:40]
|
||||
pcii_tready,ce2i_tready,ce1i_tready,ce0i_tready,r1i_tready,r0i_tready,e2v1_tready,e2v0_tready, //[39:32]
|
||||
pcii_tlast,ce2i_tlast,ce1i_tlast,ce0i_tlast,r1i_tlast,r0i_tlast,e2v1_tlast,e2v0_tlast, //[31:24]
|
||||
pcio_tvalid,ce2o_tvalid,ce1o_tvalid,ce0o_tvalid,r1o_tvalid,r0o_tvalid,v2e1_tvalid,v2e0_tvalid, //[23:16]
|
||||
pcio_tready,ce2o_tready,ce1o_tready,ce0o_tready,r1o_tready,r0o_tready,v2e1_tready,v2e0_tready, //[15:8]
|
||||
pcio_tlast,ce2o_tlast,ce1o_tlast,ce0o_tlast,r1o_tlast,r0o_tlast,v2e1_tlast,v2e0_tlast //[7:0]
|
||||
};
|
||||
*/
|
||||
//
|
||||
// This next section adds the ability to send messages and data via chipscope and the setting bus.
|
||||
// If chipscope is used elsewhere in the hierarchy then this must be commented.
|
||||
//
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
wire [35:0] CONTROL0;
|
||||
(* keep = "true", max_fanout = 10 *) reg [31:0] set_data_debug;
|
||||
(* keep = "true", max_fanout = 10 *) reg [7:0] set_addr_debug;
|
||||
(* keep = "true", max_fanout = 10 *) reg set_stb_debug;
|
||||
|
||||
always @(posedge clk) begin
|
||||
set_data_debug = set_data;
|
||||
set_addr_debug = set_addr;
|
||||
set_stb_debug = set_stb;
|
||||
end
|
||||
|
||||
chipscope_icon chipscope_icon_i0
|
||||
(
|
||||
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
|
||||
);
|
||||
|
||||
chipscope_ila_64 chipscope_ila_i0
|
||||
(
|
||||
.CONTROL(CONTROL0), // INOUT BUS [35:0]
|
||||
.CLK(clk), // IN
|
||||
.TRIG0(
|
||||
{
|
||||
set_stb_debug, // [40]
|
||||
set_addr_debug[7:0], // [39:32]
|
||||
set_data_debug[31:0] // [31:0]
|
||||
})
|
||||
);
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
|
||||
|
||||
// Fixed connections
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
assign { r0o_tvalid, r0o_tlast, r0o_tdata } = { e2v0_tvalid, e2v0_tlast, e2v0_tdata };
|
||||
assign e2v0_tready = r0o_tready;
|
||||
|
||||
assign { v2e0_tvalid, v2e0_tlast, v2e0_tdata } = { r0i_tvalid, r0i_tlast, r0i_tdata };
|
||||
assign r0i_tready = v2e0_tready;
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
|
||||
/*
|
||||
assign debug2 = {
|
||||
eth0_tx_tvalid, eth0_tx_tready,
|
||||
eth0_rx_tvalid, eth0_rx_tready,
|
||||
e2v0_tvalid, e2v0_tready,
|
||||
v2e0_tvalid, v2e0_tready,
|
||||
|
||||
e01_tvalid, e01_tready,
|
||||
e10_tvalid, e10_tready,
|
||||
zpui0_tvalid, zpui0_tready,
|
||||
zpuo0_tvalid, zpuo0_tready,
|
||||
|
||||
zpuo_tvalid, zpuo_tready,
|
||||
zpui_tvalid, zpui_tready,
|
||||
4'b0,
|
||||
|
||||
8'b0
|
||||
};
|
||||
*/
|
||||
endmodule // bus_int
|
||||
@@ -1,32 +0,0 @@
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module bus_int_tb();
|
||||
|
||||
wire GSR, GTS;
|
||||
xlnx_glbl glbl( );
|
||||
|
||||
reg clk = 0;
|
||||
reg reset = 1;
|
||||
|
||||
always #10 clk = ~clk;
|
||||
|
||||
initial $dumpfile("bus_int_tb.vcd");
|
||||
initial $dumpvars(0,bus_int_tb);
|
||||
|
||||
initial
|
||||
begin
|
||||
#1000 reset = 0;
|
||||
#2000000;
|
||||
$finish;
|
||||
end
|
||||
|
||||
wire sen, sclk, mosi, miso;
|
||||
wire scl, sda;
|
||||
|
||||
bus_int bus_int
|
||||
(.clk(clk), .reset(reset),
|
||||
.sen(sen), .sclk(sclk), .mosi(mosi), .miso(miso),
|
||||
.scl(scl), .sda(sda)
|
||||
);
|
||||
|
||||
endmodule // bus_int_tb
|
||||
@@ -1,67 +0,0 @@
|
||||
//
|
||||
// Copyright 2011-2014 Ettus Research LLC
|
||||
//
|
||||
|
||||
// The two clocks are aligned externally in order to eliminate the need for a FIFO.
|
||||
// A FIFO cannot be used to transition between clock domains because it can cause
|
||||
// alignment issues between the output of multiple modules.
|
||||
|
||||
module capture_ddrlvds
|
||||
#(parameter WIDTH=7,
|
||||
parameter X300=0)
|
||||
(input clk,
|
||||
input ssclk_p,
|
||||
input ssclk_n,
|
||||
input [WIDTH-1:0] in_p,
|
||||
input [WIDTH-1:0] in_n,
|
||||
output reg [(2*WIDTH)-1:0] out);
|
||||
|
||||
wire [WIDTH-1:0] ddr_dat;
|
||||
wire ssclk;
|
||||
wire [(2*WIDTH)-1:0] out_pre1;
|
||||
reg [(2*WIDTH)-1:0] out_pre2;
|
||||
wire ssclk_bufio1, ssclk_bufio2, ssclk_bufmr;
|
||||
|
||||
IBUFGDS #(.DIFF_TERM("TRUE"))
|
||||
clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n));
|
||||
|
||||
BUFMR clkbufmr (
|
||||
.I(ssclk),
|
||||
.O(ssclk_bufmr)
|
||||
);
|
||||
|
||||
BUFIO clkbufio1 (
|
||||
.I(ssclk_bufmr),
|
||||
.O(ssclk_bufio1)
|
||||
);
|
||||
|
||||
BUFIO clkbufio2 (
|
||||
.I(ssclk_bufmr),
|
||||
.O(ssclk_bufio2)
|
||||
);
|
||||
|
||||
genvar i;
|
||||
|
||||
generate
|
||||
for(i = 0; i < WIDTH; i = i + 1)
|
||||
begin : gen_lvds_pins
|
||||
if ((i == 10) && (X300 == 1)) begin
|
||||
IBUFDS #(.DIFF_TERM("FALSE")) ibufds
|
||||
(.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) );
|
||||
IDDR #(.DDR_CLK_EDGE("SAME_EDGE_PIPELINED")) iddr
|
||||
(.Q1(out_pre1[2*i]), .Q2(out_pre1[(2*i)+1]), .C(ssclk_bufio2),
|
||||
.CE(1'b1), .D(ddr_dat[i]), .R(1'b0), .S(1'b0));
|
||||
end else begin
|
||||
IBUFDS #(.DIFF_TERM("TRUE")) ibufds
|
||||
(.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) );
|
||||
IDDR #(.DDR_CLK_EDGE("SAME_EDGE_PIPELINED")) iddr
|
||||
(.Q1(out_pre1[2*i]), .Q2(out_pre1[(2*i)+1]), .C(ssclk_bufio1),
|
||||
.CE(1'b1), .D(ddr_dat[i]), .R(1'b0), .S(1'b0));
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
always @(posedge clk)
|
||||
{out, out_pre2} <= {out_pre2, out_pre1};
|
||||
|
||||
endmodule // capture_ddrlvds
|
||||
@@ -1,5 +0,0 @@
|
||||
_xmsgs
|
||||
*.log
|
||||
*.ncf
|
||||
/bootram.ncf
|
||||
/bootram.xise
|
||||
@@ -1,67 +0,0 @@
|
||||
#
|
||||
# Copyright 2012 Ettus Research LLC
|
||||
#
|
||||
|
||||
##################################################
|
||||
# Coregen Sources
|
||||
##################################################
|
||||
CG_TMP_DIR = $(HOME)/.tmp/$(NAME)_coregen
|
||||
CG_SOURCE_DIR = $(BASE_DIR)/x300/coregen
|
||||
CG_BUILD_DIR = $(BUILD_DIR)/coregen
|
||||
|
||||
COREGEN_SRCS = $(abspath $(addprefix $(CG_BUILD_DIR)/, \
|
||||
input_sample_fifo.v \
|
||||
input_sample_fifo.xco \
|
||||
axi64_4k_2clk_fifo.v \
|
||||
axi64_8k_2clk_fifo.v \
|
||||
fifo_4k_2clk.v \
|
||||
fifo_short_2clk.v \
|
||||
fifo_short_2clk.xco \
|
||||
radio_clk_gen.v \
|
||||
radio_clk_gen.xco \
|
||||
bus_clk_gen.v \
|
||||
bus_clk_gen.xco \
|
||||
pcie_clk_gen.v \
|
||||
pcie_clk_gen.xco \
|
||||
bootram.xco \
|
||||
))
|
||||
|
||||
COREGEN_DRAM_SRCS = $(abspath $(addprefix $(CG_SOURCE_DIR)/, \
|
||||
axi_intercon_2x64_128.xco \
|
||||
ddr3_32bit/user_design/rtl/ddr3_32bit.v \
|
||||
ddr3_32bit/user_design/constraints/ddr3_32bit.ucf \
|
||||
ddr3_32bit.xco \
|
||||
))
|
||||
|
||||
COREGEN_CHIPSCOPE_SRCS = $(abspath $(addprefix $(CG_SOURCE_DIR)/, \
|
||||
chipscope_ila.v \
|
||||
chipscope_ila.xco \
|
||||
chipscope_ila_64.v \
|
||||
chipscope_ila_64.xco \
|
||||
chipscope_icon.v \
|
||||
chipscope_icon.xco \
|
||||
chipscope_icon_2port.v \
|
||||
chipscope_icon_2port.xco \
|
||||
))
|
||||
|
||||
COREGEN_ONE_GIG_SRCS = $(abspath $(addprefix $(CG_SOURCE_DIR)/, \
|
||||
gige_sfp_mdio.v \
|
||||
))
|
||||
|
||||
COREGEN_TEN_GIG_SRCS = $(abspath $(addprefix $(CG_SOURCE_DIR)/, \
|
||||
ten_gig_eth_pcs_pma.v \
|
||||
))
|
||||
|
||||
#make rule to regenerate bootram when the coe file is changed
|
||||
#this takes place out of tree to make the coregen tool happy
|
||||
$(CG_TMP_DIR)/bootram.coe: $(CG_SOURCE_DIR)/bootram.coe
|
||||
mkdir -p $(CG_TMP_DIR)
|
||||
cp -r $(CG_SOURCE_DIR)/* $(CG_TMP_DIR)/
|
||||
coregen -b $(CG_TMP_DIR)/bootram.xco -p $(CG_TMP_DIR) -r
|
||||
|
||||
#copy all coregen products into the build dir
|
||||
#these products will be deleted with make clean
|
||||
$(COREGEN_SRCS): $(CG_TMP_DIR)/bootram.coe
|
||||
mkdir -p $(CG_BUILD_DIR)
|
||||
cp -r $(CG_SOURCE_DIR)/* $(CG_BUILD_DIR)/
|
||||
cp -r $(CG_TMP_DIR)/bootram.* $(CG_BUILD_DIR)/
|
||||
@@ -1,129 +0,0 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 axi4_bram_1kx64
|
||||
RECTANGLE Normal 32 32 544 1376
|
||||
LINE Normal 0 656 32 656
|
||||
PIN 0 656 LEFT 36
|
||||
PINATTR PinName s_aresetn
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 688 32 688
|
||||
PIN 0 688 LEFT 36
|
||||
PINATTR PinName s_aclk
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 720 32 720
|
||||
PIN 0 720 LEFT 36
|
||||
PINATTR PinName s_axi_awid[0:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 752 32 752
|
||||
PIN 0 752 LEFT 36
|
||||
PINATTR PinName s_axi_awaddr[31:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 784 32 784
|
||||
PIN 0 784 LEFT 36
|
||||
PINATTR PinName s_axi_awlen[7:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 816 32 816
|
||||
PIN 0 816 LEFT 36
|
||||
PINATTR PinName s_axi_awsize[2:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 848 32 848
|
||||
PIN 0 848 LEFT 36
|
||||
PINATTR PinName s_axi_awburst[1:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 880 32 880
|
||||
PIN 0 880 LEFT 36
|
||||
PINATTR PinName s_axi_awvalid
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 912 32 912
|
||||
PIN 0 912 LEFT 36
|
||||
PINATTR PinName s_axi_awready
|
||||
PINATTR Polarity OUT
|
||||
LINE Wide 0 976 32 976
|
||||
PIN 0 976 LEFT 36
|
||||
PINATTR PinName s_axi_wdata[63:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 1008 32 1008
|
||||
PIN 0 1008 LEFT 36
|
||||
PINATTR PinName s_axi_wstrb[7:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 1040 32 1040
|
||||
PIN 0 1040 LEFT 36
|
||||
PINATTR PinName s_axi_wlast
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 1072 32 1072
|
||||
PIN 0 1072 LEFT 36
|
||||
PINATTR PinName s_axi_wvalid
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 1104 32 1104
|
||||
PIN 0 1104 LEFT 36
|
||||
PINATTR PinName s_axi_wready
|
||||
PINATTR Polarity OUT
|
||||
LINE Wide 0 1168 32 1168
|
||||
PIN 0 1168 LEFT 36
|
||||
PINATTR PinName s_axi_bid[0:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Wide 0 1200 32 1200
|
||||
PIN 0 1200 LEFT 36
|
||||
PINATTR PinName s_axi_bresp[1:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 0 1232 32 1232
|
||||
PIN 0 1232 LEFT 36
|
||||
PINATTR PinName s_axi_bvalid
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 0 1264 32 1264
|
||||
PIN 0 1264 LEFT 36
|
||||
PINATTR PinName s_axi_bready
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 576 720 544 720
|
||||
PIN 576 720 RIGHT 36
|
||||
PINATTR PinName s_axi_arid[0:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 576 752 544 752
|
||||
PIN 576 752 RIGHT 36
|
||||
PINATTR PinName s_axi_araddr[31:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 576 784 544 784
|
||||
PIN 576 784 RIGHT 36
|
||||
PINATTR PinName s_axi_arlen[7:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 576 816 544 816
|
||||
PIN 576 816 RIGHT 36
|
||||
PINATTR PinName s_axi_arsize[2:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 576 848 544 848
|
||||
PIN 576 848 RIGHT 36
|
||||
PINATTR PinName s_axi_arburst[1:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 576 880 544 880
|
||||
PIN 576 880 RIGHT 36
|
||||
PINATTR PinName s_axi_arvalid
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 576 912 544 912
|
||||
PIN 576 912 RIGHT 36
|
||||
PINATTR PinName s_axi_arready
|
||||
PINATTR Polarity OUT
|
||||
LINE Wide 576 976 544 976
|
||||
PIN 576 976 RIGHT 36
|
||||
PINATTR PinName s_axi_rid[0:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Wide 576 1008 544 1008
|
||||
PIN 576 1008 RIGHT 36
|
||||
PINATTR PinName s_axi_rresp[1:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Wide 576 1040 544 1040
|
||||
PIN 576 1040 RIGHT 36
|
||||
PINATTR PinName s_axi_rdata[63:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 576 1072 544 1072
|
||||
PIN 576 1072 RIGHT 36
|
||||
PINATTR PinName s_axi_rlast
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 576 1104 544 1104
|
||||
PIN 576 1104 RIGHT 36
|
||||
PINATTR PinName s_axi_rvalid
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 576 1136 544 1136
|
||||
PIN 576 1136 RIGHT 36
|
||||
PINATTR PinName s_axi_rready
|
||||
PINATTR Polarity IN
|
||||
|
||||
@@ -1,31 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="axi4_bram_1kx64.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="axi4_bram_1kx64.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VEO" xil_pn:name="axi4_bram_1kx64.veo" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
|
||||
</generated_project>
|
||||
File diff suppressed because one or more lines are too long
@@ -1,232 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* This file is owned and controlled by Xilinx and must be used solely *
|
||||
* for design, simulation, implementation and creation of design files *
|
||||
* limited to Xilinx devices or technologies. Use with non-Xilinx *
|
||||
* devices or technologies is expressly prohibited and immediately *
|
||||
* terminates your license. *
|
||||
* *
|
||||
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
|
||||
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
|
||||
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
|
||||
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
|
||||
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
|
||||
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
|
||||
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
|
||||
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
|
||||
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
|
||||
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
|
||||
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
|
||||
* PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* Xilinx products are not intended for use in life support appliances, *
|
||||
* devices, or systems. Use in such applications are expressly *
|
||||
* prohibited. *
|
||||
* *
|
||||
* (c) Copyright 1995-2013 Xilinx, Inc. *
|
||||
* All rights reserved. *
|
||||
*******************************************************************************/
|
||||
// You must compile the wrapper file axi4_bram_1kx64.v when simulating
|
||||
// the core, axi4_bram_1kx64. When compiling the wrapper file, be sure to
|
||||
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
||||
// instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
// The synthesis directives "translate_off/translate_on" specified below are
|
||||
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
|
||||
// tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module axi4_bram_1kx64(
|
||||
s_aclk,
|
||||
s_aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready
|
||||
);
|
||||
|
||||
input s_aclk;
|
||||
input s_aresetn;
|
||||
input [0 : 0] s_axi_awid;
|
||||
input [31 : 0] s_axi_awaddr;
|
||||
input [7 : 0] s_axi_awlen;
|
||||
input [2 : 0] s_axi_awsize;
|
||||
input [1 : 0] s_axi_awburst;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [63 : 0] s_axi_wdata;
|
||||
input [7 : 0] s_axi_wstrb;
|
||||
input s_axi_wlast;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [0 : 0] s_axi_bid;
|
||||
output [1 : 0] s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [0 : 0] s_axi_arid;
|
||||
input [31 : 0] s_axi_araddr;
|
||||
input [7 : 0] s_axi_arlen;
|
||||
input [2 : 0] s_axi_arsize;
|
||||
input [1 : 0] s_axi_arburst;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [0 : 0] s_axi_rid;
|
||||
output [63 : 0] s_axi_rdata;
|
||||
output [1 : 0] s_axi_rresp;
|
||||
output s_axi_rlast;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
|
||||
// synthesis translate_off
|
||||
|
||||
BLK_MEM_GEN_V7_3 #(
|
||||
.C_ADDRA_WIDTH(10),
|
||||
.C_ADDRB_WIDTH(10),
|
||||
.C_ALGORITHM(1),
|
||||
.C_AXI_ID_WIDTH(1),
|
||||
.C_AXI_SLAVE_TYPE(0),
|
||||
.C_AXI_TYPE(1),
|
||||
.C_BYTE_SIZE(8),
|
||||
.C_COMMON_CLK(1),
|
||||
.C_DEFAULT_DATA("0"),
|
||||
.C_DISABLE_WARN_BHV_COLL(0),
|
||||
.C_DISABLE_WARN_BHV_RANGE(0),
|
||||
.C_ENABLE_32BIT_ADDRESS(0),
|
||||
.C_FAMILY("kintex7"),
|
||||
.C_HAS_AXI_ID(1),
|
||||
.C_HAS_ENA(1),
|
||||
.C_HAS_ENB(1),
|
||||
.C_HAS_INJECTERR(0),
|
||||
.C_HAS_MEM_OUTPUT_REGS_A(0),
|
||||
.C_HAS_MEM_OUTPUT_REGS_B(0),
|
||||
.C_HAS_MUX_OUTPUT_REGS_A(0),
|
||||
.C_HAS_MUX_OUTPUT_REGS_B(0),
|
||||
.C_HAS_REGCEA(0),
|
||||
.C_HAS_REGCEB(0),
|
||||
.C_HAS_RSTA(0),
|
||||
.C_HAS_RSTB(1),
|
||||
.C_HAS_SOFTECC_INPUT_REGS_A(0),
|
||||
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
|
||||
.C_INIT_FILE("BlankString"),
|
||||
.C_INIT_FILE_NAME("no_coe_file_loaded"),
|
||||
.C_INITA_VAL("0"),
|
||||
.C_INITB_VAL("0"),
|
||||
.C_INTERFACE_TYPE(1),
|
||||
.C_LOAD_INIT_FILE(0),
|
||||
.C_MEM_TYPE(1),
|
||||
.C_MUX_PIPELINE_STAGES(0),
|
||||
.C_PRIM_TYPE(1),
|
||||
.C_READ_DEPTH_A(1024),
|
||||
.C_READ_DEPTH_B(1024),
|
||||
.C_READ_WIDTH_A(64),
|
||||
.C_READ_WIDTH_B(64),
|
||||
.C_RST_PRIORITY_A("CE"),
|
||||
.C_RST_PRIORITY_B("CE"),
|
||||
.C_RST_TYPE("ASYNC"),
|
||||
.C_RSTRAM_A(0),
|
||||
.C_RSTRAM_B(0),
|
||||
.C_SIM_COLLISION_CHECK("ALL"),
|
||||
.C_USE_BRAM_BLOCK(0),
|
||||
.C_USE_BYTE_WEA(1),
|
||||
.C_USE_BYTE_WEB(1),
|
||||
.C_USE_DEFAULT_DATA(0),
|
||||
.C_USE_ECC(0),
|
||||
.C_USE_SOFTECC(0),
|
||||
.C_WEA_WIDTH(8),
|
||||
.C_WEB_WIDTH(8),
|
||||
.C_WRITE_DEPTH_A(1024),
|
||||
.C_WRITE_DEPTH_B(1024),
|
||||
.C_WRITE_MODE_A("READ_FIRST"),
|
||||
.C_WRITE_MODE_B("READ_FIRST"),
|
||||
.C_WRITE_WIDTH_A(64),
|
||||
.C_WRITE_WIDTH_B(64),
|
||||
.C_XDEVICEFAMILY("kintex7")
|
||||
)
|
||||
inst (
|
||||
.S_ACLK(s_aclk),
|
||||
.S_ARESETN(s_aresetn),
|
||||
.S_AXI_AWID(s_axi_awid),
|
||||
.S_AXI_AWADDR(s_axi_awaddr),
|
||||
.S_AXI_AWLEN(s_axi_awlen),
|
||||
.S_AXI_AWSIZE(s_axi_awsize),
|
||||
.S_AXI_AWBURST(s_axi_awburst),
|
||||
.S_AXI_AWVALID(s_axi_awvalid),
|
||||
.S_AXI_AWREADY(s_axi_awready),
|
||||
.S_AXI_WDATA(s_axi_wdata),
|
||||
.S_AXI_WSTRB(s_axi_wstrb),
|
||||
.S_AXI_WLAST(s_axi_wlast),
|
||||
.S_AXI_WVALID(s_axi_wvalid),
|
||||
.S_AXI_WREADY(s_axi_wready),
|
||||
.S_AXI_BID(s_axi_bid),
|
||||
.S_AXI_BRESP(s_axi_bresp),
|
||||
.S_AXI_BVALID(s_axi_bvalid),
|
||||
.S_AXI_BREADY(s_axi_bready),
|
||||
.S_AXI_ARID(s_axi_arid),
|
||||
.S_AXI_ARADDR(s_axi_araddr),
|
||||
.S_AXI_ARLEN(s_axi_arlen),
|
||||
.S_AXI_ARSIZE(s_axi_arsize),
|
||||
.S_AXI_ARBURST(s_axi_arburst),
|
||||
.S_AXI_ARVALID(s_axi_arvalid),
|
||||
.S_AXI_ARREADY(s_axi_arready),
|
||||
.S_AXI_RID(s_axi_rid),
|
||||
.S_AXI_RDATA(s_axi_rdata),
|
||||
.S_AXI_RRESP(s_axi_rresp),
|
||||
.S_AXI_RLAST(s_axi_rlast),
|
||||
.S_AXI_RVALID(s_axi_rvalid),
|
||||
.S_AXI_RREADY(s_axi_rready),
|
||||
.CLKA(),
|
||||
.RSTA(),
|
||||
.ENA(),
|
||||
.REGCEA(),
|
||||
.WEA(),
|
||||
.ADDRA(),
|
||||
.DINA(),
|
||||
.DOUTA(),
|
||||
.CLKB(),
|
||||
.RSTB(),
|
||||
.ENB(),
|
||||
.REGCEB(),
|
||||
.WEB(),
|
||||
.ADDRB(),
|
||||
.DINB(),
|
||||
.DOUTB(),
|
||||
.INJECTSBITERR(),
|
||||
.INJECTDBITERR(),
|
||||
.SBITERR(),
|
||||
.DBITERR(),
|
||||
.RDADDRECC(),
|
||||
.S_AXI_INJECTSBITERR(),
|
||||
.S_AXI_INJECTDBITERR(),
|
||||
.S_AXI_SBITERR(),
|
||||
.S_AXI_DBITERR(),
|
||||
.S_AXI_RDADDRECC()
|
||||
);
|
||||
|
||||
// synthesis translate_on
|
||||
|
||||
endmodule
|
||||
@@ -1,89 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* This file is owned and controlled by Xilinx and must be used solely *
|
||||
* for design, simulation, implementation and creation of design files *
|
||||
* limited to Xilinx devices or technologies. Use with non-Xilinx *
|
||||
* devices or technologies is expressly prohibited and immediately *
|
||||
* terminates your license. *
|
||||
* *
|
||||
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
|
||||
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
|
||||
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
|
||||
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
|
||||
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
|
||||
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
|
||||
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
|
||||
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
|
||||
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
|
||||
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
|
||||
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
|
||||
* PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* Xilinx products are not intended for use in life support appliances, *
|
||||
* devices, or systems. Use in such applications are expressly *
|
||||
* prohibited. *
|
||||
* *
|
||||
* (c) Copyright 1995-2013 Xilinx, Inc. *
|
||||
* All rights reserved. *
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.3 *
|
||||
* *
|
||||
* The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port *
|
||||
* Block Memory and Single Port Block Memory LogiCOREs, but is not a *
|
||||
* direct drop-in replacement. It should be used in all new Xilinx *
|
||||
* designs. The core supports RAM and ROM functions over a wide range of *
|
||||
* widths and depths. Use this core to generate block memories with *
|
||||
* symmetric or asymmetric read and write port widths, as well as cores *
|
||||
* which can perform simultaneous write operations to separate *
|
||||
* locations, and simultaneous read operations from the same location. *
|
||||
* For more information on differences in interface and feature support *
|
||||
* between this core and the Dual Port Block Memory and Single Port *
|
||||
* Block Memory LogiCOREs, please consult the data sheet. *
|
||||
*******************************************************************************/
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
axi4_bram_1kx64 your_instance_name (
|
||||
.s_aclk(s_aclk), // input s_aclk
|
||||
.s_aresetn(s_aresetn), // input s_aresetn
|
||||
.s_axi_awid(s_axi_awid), // input [0 : 0] s_axi_awid
|
||||
.s_axi_awaddr(s_axi_awaddr), // input [31 : 0] s_axi_awaddr
|
||||
.s_axi_awlen(s_axi_awlen), // input [7 : 0] s_axi_awlen
|
||||
.s_axi_awsize(s_axi_awsize), // input [2 : 0] s_axi_awsize
|
||||
.s_axi_awburst(s_axi_awburst), // input [1 : 0] s_axi_awburst
|
||||
.s_axi_awvalid(s_axi_awvalid), // input s_axi_awvalid
|
||||
.s_axi_awready(s_axi_awready), // output s_axi_awready
|
||||
.s_axi_wdata(s_axi_wdata), // input [63 : 0] s_axi_wdata
|
||||
.s_axi_wstrb(s_axi_wstrb), // input [7 : 0] s_axi_wstrb
|
||||
.s_axi_wlast(s_axi_wlast), // input s_axi_wlast
|
||||
.s_axi_wvalid(s_axi_wvalid), // input s_axi_wvalid
|
||||
.s_axi_wready(s_axi_wready), // output s_axi_wready
|
||||
.s_axi_bid(s_axi_bid), // output [0 : 0] s_axi_bid
|
||||
.s_axi_bresp(s_axi_bresp), // output [1 : 0] s_axi_bresp
|
||||
.s_axi_bvalid(s_axi_bvalid), // output s_axi_bvalid
|
||||
.s_axi_bready(s_axi_bready), // input s_axi_bready
|
||||
.s_axi_arid(s_axi_arid), // input [0 : 0] s_axi_arid
|
||||
.s_axi_araddr(s_axi_araddr), // input [31 : 0] s_axi_araddr
|
||||
.s_axi_arlen(s_axi_arlen), // input [7 : 0] s_axi_arlen
|
||||
.s_axi_arsize(s_axi_arsize), // input [2 : 0] s_axi_arsize
|
||||
.s_axi_arburst(s_axi_arburst), // input [1 : 0] s_axi_arburst
|
||||
.s_axi_arvalid(s_axi_arvalid), // input s_axi_arvalid
|
||||
.s_axi_arready(s_axi_arready), // output s_axi_arready
|
||||
.s_axi_rid(s_axi_rid), // output [0 : 0] s_axi_rid
|
||||
.s_axi_rdata(s_axi_rdata), // output [63 : 0] s_axi_rdata
|
||||
.s_axi_rresp(s_axi_rresp), // output [1 : 0] s_axi_rresp
|
||||
.s_axi_rlast(s_axi_rlast), // output s_axi_rlast
|
||||
.s_axi_rvalid(s_axi_rvalid), // output s_axi_rvalid
|
||||
.s_axi_rready(s_axi_rready) // input s_axi_rready
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file axi4_bram_1kx64.v when simulating
|
||||
// the core, axi4_bram_1kx64. When compiling the wrapper file, be sure to
|
||||
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
||||
// instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
@@ -1,108 +0,0 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.4
|
||||
# Date: Mon Jun 10 04:37:23 2013
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:blk_mem_gen:7.3
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Verilog
|
||||
SET device = xc7k410t
|
||||
SET devicefamily = kintex7
|
||||
SET flowvendor = Foundation_ISE
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = ffg900
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -2
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = false
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET additional_inputs_for_power_estimation=false
|
||||
CSET algorithm=Minimum_Area
|
||||
CSET assume_synchronous_clk=true
|
||||
CSET axi_id_width=1
|
||||
CSET axi_slave_type=Memory_Slave
|
||||
CSET axi_type=AXI4_Full
|
||||
CSET byte_size=8
|
||||
CSET coe_file=no_coe_file_loaded
|
||||
CSET collision_warnings=ALL
|
||||
CSET component_name=axi4_bram_1kx64
|
||||
CSET disable_collision_warnings=false
|
||||
CSET disable_out_of_range_warnings=false
|
||||
CSET ecc=false
|
||||
CSET ecctype=No_ECC
|
||||
CSET enable_32bit_address=false
|
||||
CSET enable_a=Use_ENA_Pin
|
||||
CSET enable_b=Use_ENB_Pin
|
||||
CSET error_injection_type=Single_Bit_Error_Injection
|
||||
CSET fill_remaining_memory_locations=false
|
||||
CSET interface_type=AXI4
|
||||
CSET load_init_file=false
|
||||
CSET mem_file=no_Mem_file_loaded
|
||||
CSET memory_type=Simple_Dual_Port_RAM
|
||||
CSET operating_mode_a=READ_FIRST
|
||||
CSET operating_mode_b=READ_FIRST
|
||||
CSET output_reset_value_a=0
|
||||
CSET output_reset_value_b=0
|
||||
CSET pipeline_stages=0
|
||||
CSET port_a_clock=100
|
||||
CSET port_a_enable_rate=100
|
||||
CSET port_a_write_rate=50
|
||||
CSET port_b_clock=100
|
||||
CSET port_b_enable_rate=100
|
||||
CSET port_b_write_rate=0
|
||||
CSET primitive=8kx2
|
||||
CSET read_width_a=64
|
||||
CSET read_width_b=64
|
||||
CSET register_porta_input_of_softecc=false
|
||||
CSET register_porta_output_of_memory_core=false
|
||||
CSET register_porta_output_of_memory_primitives=false
|
||||
CSET register_portb_output_of_memory_core=false
|
||||
CSET register_portb_output_of_memory_primitives=false
|
||||
CSET register_portb_output_of_softecc=false
|
||||
CSET remaining_memory_locations=0
|
||||
CSET reset_memory_latch_a=false
|
||||
CSET reset_memory_latch_b=false
|
||||
CSET reset_priority_a=CE
|
||||
CSET reset_priority_b=CE
|
||||
CSET reset_type=ASYNC
|
||||
CSET softecc=false
|
||||
CSET use_axi_id=true
|
||||
CSET use_bram_block=Stand_Alone
|
||||
CSET use_byte_write_enable=true
|
||||
CSET use_error_injection_pins=false
|
||||
CSET use_regcea_pin=false
|
||||
CSET use_regceb_pin=false
|
||||
CSET use_rsta_pin=false
|
||||
CSET use_rstb_pin=true
|
||||
CSET write_depth_a=1024
|
||||
CSET write_width_a=64
|
||||
CSET write_width_b=64
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-11-19T16:22:25Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: 543484ef
|
||||
@@ -1,361 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="axi4_bram_1kx64.ngc" xil_pn:type="FILE_NGC">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="axi4_bram_1kx64.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc7k410t" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Kintex7" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|axi4_bram_1kx64" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="axi4_bram_1kx64.ngc" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/axi4_bram_1kx64" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="axi4_bram_1kx64" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="ffg900" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="axi4_bram_1kx64_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="axi4_bram_1kx64_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="axi4_bram_1kx64_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="axi4_bram_1kx64_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
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||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="axi4_bram_1kx64" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="kintex7" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-06-09T21:38:09" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="E14BDB77EDB0A1180DA0781C996BE3BF" xil_pn:valueState="non-default"/>
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||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
@@ -1,213 +0,0 @@
|
||||
Core name: Xilinx LogiCORE Block Memory Generator
|
||||
Version: 7.3 Rev 1
|
||||
Release: ISE 14.4 / Vivado 2012.4
|
||||
Release Date: October 16, 2012
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURES HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
|
||||
|
||||
For system requirements:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.3
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
All Virtex-6 devices
|
||||
All Spartan-6 devices
|
||||
All Virtex-5 devices
|
||||
All Spartan-3 devices
|
||||
All Virtex-4 devices
|
||||
|
||||
|
||||
2.2 Vivado
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
|
||||
................................................................................
|
||||
|
||||
3. NEW FEATURES HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- ISE 14.4 software support
|
||||
|
||||
|
||||
3.2 Vivado
|
||||
|
||||
- 2012.4 software support
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
The following issues are resolved in Block Memory Generator v7.3:
|
||||
|
||||
4.1 ISE
|
||||
|
||||
|
||||
4.2 Vivado
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
The following are known issues for v7.3 of this core at time of release:
|
||||
|
||||
1. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
|
||||
|
||||
3. Core does not generate for large memories. Depending on the
|
||||
machine the ISE CORE Generator software runs on, the maximum size of the memory that
|
||||
can be generated will vary. For example, a Dual Pentium-4 server
|
||||
with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
|
||||
- CR 415768
|
||||
- AR 24034
|
||||
|
||||
|
||||
5.2 Vivado
|
||||
|
||||
The following are known issues for v7.3 of this core at time of release:
|
||||
|
||||
The most recent information, including known issues, workarounds, and resolutions for
|
||||
this version is provided in the IP Release Notes User Guide located at
|
||||
|
||||
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
To obtain technical support, create a WebCase at www.xilinx.com/support.
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
12/16/2012 Xilinx, Inc. 7.3 Rev 1 ISE 14.4 and Vivado 2012.4 support;
|
||||
10/16/2012 Xilinx, Inc. 7.3 ISE 14.3 and Vivado 2012.3 support;
|
||||
07/25/2012 Xilinx, Inc. 7.2 ISE 14.2 and Vivado 2012.2 support;
|
||||
04/24/2012 Xilinx, Inc. 7.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
|
||||
01/18/2011 Xilinx, Inc. 6.3 ISE 13.4 support;Artix7L*, AArtix-7* device support
|
||||
06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;
|
||||
03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support
|
||||
09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support
|
||||
07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support
|
||||
03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue
|
||||
12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power
|
||||
Device support; Automotive Spartan 3A
|
||||
DSP device support
|
||||
09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3
|
||||
06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2
|
||||
04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1
|
||||
09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8
|
||||
03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7
|
||||
10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6
|
||||
07/2007 Xilinx, Inc. 2.5 Revised to v2.5
|
||||
04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1
|
||||
02/2007 Xilinx, Inc. 2.4 Revised to v2.4
|
||||
11/2006 Xilinx, Inc. 2.3 Revised to v2.3
|
||||
09/2006 Xilinx, Inc. 2.2 Revised to v2.2
|
||||
06/2006 Xilinx, Inc. 2.1 Revised to v2.1
|
||||
01/2006 Xilinx, Inc. 1.1 Initial release
|
||||
================================================================================
|
||||
|
||||
8. Legal Disclaimer
|
||||
|
||||
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
@@ -1,224 +0,0 @@
|
||||
<HTML>
|
||||
<HEAD>
|
||||
<TITLE>blk_mem_gen_v7_3_vinfo</TITLE>
|
||||
<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
|
||||
</HEAD>
|
||||
<BODY>
|
||||
<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
|
||||
Core name: Xilinx LogiCORE Block Memory Generator
|
||||
Version: 7.3 Rev 1
|
||||
Release: ISE 14.4 / Vivado 2012.4
|
||||
Release Date: October 16, 2012
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURES HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
|
||||
|
||||
For system requirements:
|
||||
|
||||
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.3
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
<A HREF="http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm">www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm</A>
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
All Virtex-6 devices
|
||||
All Spartan-6 devices
|
||||
All Virtex-5 devices
|
||||
All Spartan-3 devices
|
||||
All Virtex-4 devices
|
||||
|
||||
|
||||
2.2 Vivado
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
|
||||
................................................................................
|
||||
|
||||
3. NEW FEATURES HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- ISE 14.4 software support
|
||||
|
||||
|
||||
3.2 Vivado
|
||||
|
||||
- 2012.4 software support
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
The following issues are resolved in Block Memory Generator v7.3:
|
||||
|
||||
4.1 ISE
|
||||
|
||||
|
||||
4.2 Vivado
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
The following are known issues for v7.3 of this core at time of release:
|
||||
|
||||
1. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
|
||||
|
||||
3. Core does not generate for large memories. Depending on the
|
||||
machine the ISE CORE Generator software runs on, the maximum size of the memory that
|
||||
can be generated will vary. For example, a Dual Pentium-4 server
|
||||
with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
|
||||
- CR 415768
|
||||
- AR 24034
|
||||
|
||||
|
||||
5.2 Vivado
|
||||
|
||||
The following are known issues for v7.3 of this core at time of release:
|
||||
|
||||
The most recent information, including known issues, workarounds, and resolutions for
|
||||
this version is provided in the IP Release Notes User Guide located at
|
||||
|
||||
<A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
12/16/2012 Xilinx, Inc. 7.3 Rev 1 ISE 14.4 and Vivado 2012.4 support;
|
||||
10/16/2012 Xilinx, Inc. 7.3 ISE 14.3 and Vivado 2012.3 support;
|
||||
07/25/2012 Xilinx, Inc. 7.2 ISE 14.2 and Vivado 2012.2 support;
|
||||
04/24/2012 Xilinx, Inc. 7.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
|
||||
01/18/2011 Xilinx, Inc. 6.3 ISE 13.4 support;Artix7L*, AArtix-7* device support
|
||||
06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;
|
||||
03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support
|
||||
09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support
|
||||
07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support
|
||||
03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue
|
||||
12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power
|
||||
Device support; Automotive Spartan 3A
|
||||
DSP device support
|
||||
09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3
|
||||
06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2
|
||||
04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1
|
||||
09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8
|
||||
03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7
|
||||
10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6
|
||||
07/2007 Xilinx, Inc. 2.5 Revised to v2.5
|
||||
04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1
|
||||
02/2007 Xilinx, Inc. 2.4 Revised to v2.4
|
||||
11/2006 Xilinx, Inc. 2.3 Revised to v2.3
|
||||
09/2006 Xilinx, Inc. 2.2 Revised to v2.2
|
||||
06/2006 Xilinx, Inc. 2.1 Revised to v2.1
|
||||
01/2006 Xilinx, Inc. 1.1 Initial release
|
||||
================================================================================
|
||||
|
||||
8. Legal Disclaimer
|
||||
|
||||
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
</FONT>
|
||||
</PRE>
|
||||
</BODY>
|
||||
</HTML>
|
||||
Binary file not shown.
@@ -1,57 +0,0 @@
|
||||
################################################################################
|
||||
#
|
||||
# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
# Tx Core Period Constraint. This constraint can be modified, and is
|
||||
# valid as long as it is met after place and route.
|
||||
NET "S_ACLK" TNM_NET = "S_ACLK";
|
||||
TIMESPEC "TS_S_ACLK" = PERIOD "S_ACLK" 25 MHZ;
|
||||
|
||||
|
||||
################################################################################
|
||||
@@ -1,253 +0,0 @@
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: axi4_bram_1kx64_exdes.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- This is the actual BMG core wrapper.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: August 31, 2005 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
LIBRARY UNISIM;
|
||||
USE UNISIM.VCOMPONENTS.ALL;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Entity Declaration
|
||||
--------------------------------------------------------------------------------
|
||||
ENTITY axi4_bram_1kx64_exdes IS
|
||||
PORT (
|
||||
-- AXI BMG Input and Output Port Declarations
|
||||
|
||||
-- AXI Global Signals
|
||||
S_ACLK : IN STD_LOGIC;
|
||||
|
||||
-- AXI Full/Lite Slave Write (write side)
|
||||
S_AXI_AWID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_AWVALID : IN STD_LOGIC;
|
||||
S_AXI_AWREADY : OUT STD_LOGIC;
|
||||
S_AXI_WDATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_WLAST : IN STD_LOGIC;
|
||||
S_AXI_WVALID : IN STD_LOGIC;
|
||||
S_AXI_WREADY : OUT STD_LOGIC;
|
||||
S_AXI_BID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_BVALID : OUT STD_LOGIC;
|
||||
S_AXI_BREADY : IN STD_LOGIC;
|
||||
|
||||
-- AXI Full/Lite Slave Read (Write side)
|
||||
S_AXI_ARID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_ARVALID : IN STD_LOGIC;
|
||||
S_AXI_ARREADY : OUT STD_LOGIC;
|
||||
S_AXI_RID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_RLAST : OUT STD_LOGIC;
|
||||
S_AXI_RVALID : OUT STD_LOGIC;
|
||||
S_AXI_RREADY : IN STD_LOGIC;
|
||||
|
||||
-- AXI Full/Lite Sideband Signals
|
||||
S_ARESETN : IN STD_LOGIC
|
||||
|
||||
);
|
||||
|
||||
END axi4_bram_1kx64_exdes;
|
||||
|
||||
|
||||
ARCHITECTURE xilinx OF axi4_bram_1kx64_exdes IS
|
||||
|
||||
COMPONENT BUFG IS
|
||||
PORT (
|
||||
I : IN STD_ULOGIC;
|
||||
O : OUT STD_ULOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT axi4_bram_1kx64 IS
|
||||
PORT (
|
||||
|
||||
-- AXI BMG Input and Output Port Declarations
|
||||
|
||||
-- AXI Global Signals
|
||||
S_ACLK : IN STD_LOGIC;
|
||||
|
||||
-- AXI Full/Lite Slave Write (write side)
|
||||
S_AXI_AWID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_AWVALID : IN STD_LOGIC;
|
||||
S_AXI_AWREADY : OUT STD_LOGIC;
|
||||
S_AXI_WDATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_WLAST : IN STD_LOGIC;
|
||||
S_AXI_WVALID : IN STD_LOGIC;
|
||||
S_AXI_WREADY : OUT STD_LOGIC;
|
||||
S_AXI_BID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_BVALID : OUT STD_LOGIC;
|
||||
S_AXI_BREADY : IN STD_LOGIC;
|
||||
|
||||
-- AXI Full/Lite Slave Read (Write side)
|
||||
S_AXI_ARID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_ARVALID : IN STD_LOGIC;
|
||||
S_AXI_ARREADY : OUT STD_LOGIC;
|
||||
S_AXI_RID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_RLAST : OUT STD_LOGIC;
|
||||
S_AXI_RVALID : OUT STD_LOGIC;
|
||||
S_AXI_RREADY : IN STD_LOGIC;
|
||||
|
||||
-- AXI Full/Lite Sideband Signals
|
||||
S_ARESETN : IN STD_LOGIC
|
||||
|
||||
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
SIGNAL CLKA_buf : STD_LOGIC;
|
||||
SIGNAL CLKB_buf : STD_LOGIC;
|
||||
SIGNAL S_ACLK_buf : STD_LOGIC;
|
||||
|
||||
BEGIN
|
||||
|
||||
|
||||
bufg_A : BUFG
|
||||
PORT MAP (
|
||||
I => S_ACLK,
|
||||
O => S_ACLK_buf
|
||||
);
|
||||
|
||||
|
||||
bmg0 : axi4_bram_1kx64
|
||||
PORT MAP (
|
||||
-- AXI BMG Input and Output Port Declarations
|
||||
--Global Signals
|
||||
S_AClk => S_ACLK_buf,
|
||||
|
||||
--AXI Full/Lite Slav=>
|
||||
S_AXI_AWID => S_AXI_AWID,
|
||||
S_AXI_AWADDR =>S_AXI_AWADDR,
|
||||
S_AXI_AWLEN =>S_AXI_AWLEN,
|
||||
S_AXI_AWSIZE => S_AXI_AWSIZE,
|
||||
S_AXI_AWBURST => S_AXI_AWBURST,
|
||||
S_AXI_AWVALID =>S_AXI_AWVALID,
|
||||
S_AXI_AWREADY =>S_AXI_AWREADY,
|
||||
S_AXI_WDATA =>S_AXI_WDATA,
|
||||
S_AXI_WSTRB =>S_AXI_WSTRB,
|
||||
S_AXI_WLAST =>S_AXI_WLAST,
|
||||
S_AXI_WVALID =>S_AXI_WVALID,
|
||||
S_AXI_WREADY =>S_AXI_WREADY,
|
||||
S_AXI_BID =>S_AXI_BID,
|
||||
S_AXI_BRESP =>S_AXI_BRESP,
|
||||
S_AXI_BVALID =>S_AXI_BVALID,
|
||||
S_AXI_BREADY =>S_AXI_BREADY,
|
||||
|
||||
-- AXI Full/Lite Slave Read (Write side)
|
||||
S_AXI_ARID =>S_AXI_ARID,
|
||||
S_AXI_ARADDR =>S_AXI_ARADDR,
|
||||
S_AXI_ARLEN =>S_AXI_ARLEN,
|
||||
S_AXI_ARSIZE =>S_AXI_ARSIZE,
|
||||
S_AXI_ARBURST =>S_AXI_ARBURST,
|
||||
S_AXI_ARVALID =>S_AXI_ARVALID,
|
||||
S_AXI_ARREADY =>S_AXI_ARREADY,
|
||||
S_AXI_RID =>S_AXI_RID,
|
||||
S_AXI_RDATA =>S_AXI_RDATA,
|
||||
S_AXI_RRESP =>S_AXI_RRESP,
|
||||
S_AXI_RLAST => S_AXI_RLAST,
|
||||
S_AXI_RVALID => S_AXI_RVALID,
|
||||
S_AXI_RREADY =>S_AXI_RREADY,
|
||||
|
||||
-- AXI Full/Lite Sid=>
|
||||
S_ARESETN => S_ARESETN
|
||||
|
||||
|
||||
);
|
||||
|
||||
END xilinx;
|
||||
@@ -1,54 +0,0 @@
|
||||
################################################################################
|
||||
#
|
||||
# (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
# Core Period Constraint. This constraint can be modified, and is
|
||||
# valid as long as it is met after place and route.
|
||||
create_clock -name "TS_S_CLKA" -period 20.0 [ get_ports S_ACLK ]
|
||||
################################################################################
|
||||
@@ -1,325 +0,0 @@
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7.1 Core - Top-level wrapper
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: axi4_bram_1kx64_prod.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- This is the top-level BMG wrapper (over BMG core).
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: August 31, 2005 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Configured Core Parameter Values:
|
||||
-- (Refer to the SIM Parameters table in the datasheet for more information on
|
||||
-- the these parameters.)
|
||||
-- C_FAMILY : kintex7
|
||||
-- C_XDEVICEFAMILY : kintex7
|
||||
-- C_INTERFACE_TYPE : 1
|
||||
-- C_ENABLE_32BIT_ADDRESS : 0
|
||||
-- C_AXI_TYPE : 1
|
||||
-- C_AXI_SLAVE_TYPE : 0
|
||||
-- C_AXI_ID_WIDTH : 1
|
||||
-- C_MEM_TYPE : 1
|
||||
-- C_BYTE_SIZE : 8
|
||||
-- C_ALGORITHM : 1
|
||||
-- C_PRIM_TYPE : 1
|
||||
-- C_LOAD_INIT_FILE : 0
|
||||
-- C_INIT_FILE_NAME : no_coe_file_loaded
|
||||
-- C_USE_DEFAULT_DATA : 0
|
||||
-- C_DEFAULT_DATA : 0
|
||||
-- C_RST_TYPE : ASYNC
|
||||
-- C_HAS_RSTA : 0
|
||||
-- C_RST_PRIORITY_A : CE
|
||||
-- C_RSTRAM_A : 0
|
||||
-- C_INITA_VAL : 0
|
||||
-- C_HAS_ENA : 1
|
||||
-- C_HAS_REGCEA : 0
|
||||
-- C_USE_BYTE_WEA : 1
|
||||
-- C_WEA_WIDTH : 8
|
||||
-- C_WRITE_MODE_A : READ_FIRST
|
||||
-- C_WRITE_WIDTH_A : 64
|
||||
-- C_READ_WIDTH_A : 64
|
||||
-- C_WRITE_DEPTH_A : 1024
|
||||
-- C_READ_DEPTH_A : 1024
|
||||
-- C_ADDRA_WIDTH : 10
|
||||
-- C_HAS_RSTB : 1
|
||||
-- C_RST_PRIORITY_B : CE
|
||||
-- C_RSTRAM_B : 0
|
||||
-- C_INITB_VAL : 0
|
||||
-- C_HAS_ENB : 1
|
||||
-- C_HAS_REGCEB : 0
|
||||
-- C_USE_BYTE_WEB : 1
|
||||
-- C_WEB_WIDTH : 8
|
||||
-- C_WRITE_MODE_B : READ_FIRST
|
||||
-- C_WRITE_WIDTH_B : 64
|
||||
-- C_READ_WIDTH_B : 64
|
||||
-- C_WRITE_DEPTH_B : 1024
|
||||
-- C_READ_DEPTH_B : 1024
|
||||
-- C_ADDRB_WIDTH : 10
|
||||
-- C_HAS_MEM_OUTPUT_REGS_A : 0
|
||||
-- C_HAS_MEM_OUTPUT_REGS_B : 0
|
||||
-- C_HAS_MUX_OUTPUT_REGS_A : 0
|
||||
-- C_HAS_MUX_OUTPUT_REGS_B : 0
|
||||
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
|
||||
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
|
||||
-- C_MUX_PIPELINE_STAGES : 0
|
||||
-- C_USE_ECC : 0
|
||||
-- C_USE_SOFTECC : 0
|
||||
-- C_HAS_INJECTERR : 0
|
||||
-- C_SIM_COLLISION_CHECK : ALL
|
||||
-- C_COMMON_CLK : 1
|
||||
-- C_DISABLE_WARN_BHV_COLL : 0
|
||||
-- C_DISABLE_WARN_BHV_RANGE : 0
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
LIBRARY UNISIM;
|
||||
USE UNISIM.VCOMPONENTS.ALL;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Entity Declaration
|
||||
--------------------------------------------------------------------------------
|
||||
ENTITY axi4_bram_1kx64_prod IS
|
||||
PORT (
|
||||
--Port A
|
||||
CLKA : IN STD_LOGIC;
|
||||
RSTA : IN STD_LOGIC; --opt port
|
||||
ENA : IN STD_LOGIC; --optional port
|
||||
REGCEA : IN STD_LOGIC; --optional port
|
||||
WEA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
|
||||
--Port B
|
||||
CLKB : IN STD_LOGIC;
|
||||
RSTB : IN STD_LOGIC; --opt port
|
||||
ENB : IN STD_LOGIC; --optional port
|
||||
REGCEB : IN STD_LOGIC; --optional port
|
||||
WEB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
DINB : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
DOUTB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
|
||||
--ECC
|
||||
INJECTSBITERR : IN STD_LOGIC; --optional port
|
||||
INJECTDBITERR : IN STD_LOGIC; --optional port
|
||||
SBITERR : OUT STD_LOGIC; --optional port
|
||||
DBITERR : OUT STD_LOGIC; --optional port
|
||||
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
|
||||
-- AXI BMG Input and Output Port Declarations
|
||||
|
||||
-- AXI Global Signals
|
||||
S_ACLK : IN STD_LOGIC;
|
||||
S_AXI_AWID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_AWVALID : IN STD_LOGIC;
|
||||
S_AXI_AWREADY : OUT STD_LOGIC;
|
||||
S_AXI_WDATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_WLAST : IN STD_LOGIC;
|
||||
S_AXI_WVALID : IN STD_LOGIC;
|
||||
S_AXI_WREADY : OUT STD_LOGIC;
|
||||
S_AXI_BID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0):= (OTHERS => '0');
|
||||
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_BVALID : OUT STD_LOGIC;
|
||||
S_AXI_BREADY : IN STD_LOGIC;
|
||||
|
||||
-- AXI Full/Lite Slave Read (Write side)
|
||||
S_AXI_ARID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_ARVALID : IN STD_LOGIC;
|
||||
S_AXI_ARREADY : OUT STD_LOGIC;
|
||||
S_AXI_RID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0):= (OTHERS => '0');
|
||||
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_RLAST : OUT STD_LOGIC;
|
||||
S_AXI_RVALID : OUT STD_LOGIC;
|
||||
S_AXI_RREADY : IN STD_LOGIC;
|
||||
|
||||
-- AXI Full/Lite Sideband Signals
|
||||
S_AXI_INJECTSBITERR : IN STD_LOGIC;
|
||||
S_AXI_INJECTDBITERR : IN STD_LOGIC;
|
||||
S_AXI_SBITERR : OUT STD_LOGIC;
|
||||
S_AXI_DBITERR : OUT STD_LOGIC;
|
||||
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
S_ARESETN : IN STD_LOGIC
|
||||
|
||||
|
||||
);
|
||||
|
||||
END axi4_bram_1kx64_prod;
|
||||
|
||||
|
||||
ARCHITECTURE xilinx OF axi4_bram_1kx64_prod IS
|
||||
|
||||
COMPONENT axi4_bram_1kx64_exdes IS
|
||||
PORT (
|
||||
|
||||
|
||||
-- AXI BMG Input and Output Port Declarations
|
||||
|
||||
-- AXI Global Signals
|
||||
S_ACLK : IN STD_LOGIC;
|
||||
S_AXI_AWID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_AWVALID : IN STD_LOGIC;
|
||||
S_AXI_AWREADY : OUT STD_LOGIC;
|
||||
S_AXI_WDATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_WLAST : IN STD_LOGIC;
|
||||
S_AXI_WVALID : IN STD_LOGIC;
|
||||
S_AXI_WREADY : OUT STD_LOGIC;
|
||||
S_AXI_BID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_BVALID : OUT STD_LOGIC;
|
||||
S_AXI_BREADY : IN STD_LOGIC;
|
||||
|
||||
-- AXI Full/Lite Slave Read (Write side)
|
||||
S_AXI_ARID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_ARVALID : IN STD_LOGIC;
|
||||
S_AXI_ARREADY : OUT STD_LOGIC;
|
||||
S_AXI_RID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_RLAST : OUT STD_LOGIC;
|
||||
S_AXI_RVALID : OUT STD_LOGIC;
|
||||
S_AXI_RREADY : IN STD_LOGIC;
|
||||
|
||||
-- AXI Full/Lite Sideband Signals
|
||||
S_ARESETN : IN STD_LOGIC
|
||||
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
|
||||
bmg0 : axi4_bram_1kx64_exdes
|
||||
PORT MAP (
|
||||
|
||||
|
||||
-- AXI BMG Input and Output Port Declarations
|
||||
--Global Signals
|
||||
S_AClk => S_AClk,
|
||||
|
||||
--AXI Full/Lite Slav=>
|
||||
S_AXI_AWID => S_AXI_AWID,
|
||||
S_AXI_AWADDR =>S_AXI_AWADDR,
|
||||
S_AXI_AWLEN =>S_AXI_AWLEN,
|
||||
S_AXI_AWSIZE => S_AXI_AWSIZE,
|
||||
S_AXI_AWBURST => S_AXI_AWBURST,
|
||||
S_AXI_AWVALID =>S_AXI_AWVALID,
|
||||
S_AXI_AWREADY =>S_AXI_AWREADY,
|
||||
S_AXI_WDATA =>S_AXI_WDATA,
|
||||
S_AXI_WSTRB =>S_AXI_WSTRB,
|
||||
S_AXI_WLAST =>S_AXI_WLAST,
|
||||
S_AXI_WVALID =>S_AXI_WVALID,
|
||||
S_AXI_WREADY =>S_AXI_WREADY,
|
||||
S_AXI_BID =>S_AXI_BID,
|
||||
S_AXI_BRESP =>S_AXI_BRESP,
|
||||
S_AXI_BVALID =>S_AXI_BVALID,
|
||||
S_AXI_BREADY =>S_AXI_BREADY,
|
||||
|
||||
-- AXI Full/Lite Slave Read (Write side)
|
||||
S_AXI_ARID =>S_AXI_ARID,
|
||||
S_AXI_ARADDR =>S_AXI_ARADDR,
|
||||
S_AXI_ARLEN =>S_AXI_ARLEN,
|
||||
S_AXI_ARSIZE =>S_AXI_ARSIZE,
|
||||
S_AXI_ARBURST =>S_AXI_ARBURST,
|
||||
S_AXI_ARVALID =>S_AXI_ARVALID,
|
||||
S_AXI_ARREADY =>S_AXI_ARREADY,
|
||||
S_AXI_RID =>S_AXI_RID,
|
||||
S_AXI_RDATA =>S_AXI_RDATA,
|
||||
S_AXI_RRESP =>S_AXI_RRESP,
|
||||
S_AXI_RLAST => S_AXI_RLAST,
|
||||
S_AXI_RVALID => S_AXI_RVALID,
|
||||
S_AXI_RREADY =>S_AXI_RREADY,
|
||||
|
||||
-- AXI Full/Lite Sid=>
|
||||
S_ARESETN => S_ARESETN
|
||||
|
||||
);
|
||||
END xilinx;
|
||||
@@ -1,49 +0,0 @@
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
rem Clean up the results directory
|
||||
rmdir /S /Q results
|
||||
mkdir results
|
||||
|
||||
rem Synthesize the VHDL Wrapper Files
|
||||
|
||||
|
||||
echo 'Synthesizing example design with XST';
|
||||
xst -ifn xst.scr
|
||||
copy axi4_bram_1kx64_exdes.ngc .\results\
|
||||
|
||||
|
||||
rem Copy the netlist generated by Coregen
|
||||
echo 'Copying files from the netlist directory to the results directory'
|
||||
copy ..\..\axi4_bram_1kx64.ngc results\
|
||||
|
||||
|
||||
rem Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
copy ..\example_design\axi4_bram_1kx64_exdes.ucf results\
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
ngdbuild -p xc7k410t-ffg900-2 axi4_bram_1kx64_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map axi4_bram_1kx64_exdes -o mapped.ncd -pr i
|
||||
|
||||
echo 'Running par'
|
||||
par mapped.ncd routed.ncd
|
||||
|
||||
echo 'Running trce'
|
||||
trce -e 10 routed.ncd mapped.pcf -o routed
|
||||
|
||||
echo 'Running design through bitgen'
|
||||
bitgen -w routed -g UnconstrainedPins:Allow
|
||||
|
||||
echo 'Running netgen to create gate level Verilog model'
|
||||
netgen -ofmt verilog -sim -tm axi4_bram_1kx64_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
|
||||
@@ -1,49 +0,0 @@
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#!/bin/sh
|
||||
|
||||
# Clean up the results directory
|
||||
rm -rf results
|
||||
mkdir results
|
||||
|
||||
#Synthesize the Wrapper Files
|
||||
|
||||
echo 'Synthesizing example design with XST';
|
||||
xst -ifn xst.scr
|
||||
cp axi4_bram_1kx64_exdes.ngc ./results/
|
||||
|
||||
|
||||
# Copy the netlist generated by Coregen
|
||||
echo 'Copying files from the netlist directory to the results directory'
|
||||
cp ../../axi4_bram_1kx64.ngc results/
|
||||
|
||||
# Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
cp ../example_design/axi4_bram_1kx64_exdes.ucf results/
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
ngdbuild -p xc7k410t-ffg900-2 axi4_bram_1kx64_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map axi4_bram_1kx64_exdes -o mapped.ncd -pr i
|
||||
|
||||
echo 'Running par'
|
||||
par mapped.ncd routed.ncd
|
||||
|
||||
echo 'Running trce'
|
||||
trce -e 10 routed.ncd mapped.pcf -o routed
|
||||
|
||||
echo 'Running design through bitgen'
|
||||
bitgen -w routed -g UnconstrainedPins:Allow
|
||||
|
||||
echo 'Running netgen to create gate level Verilog model'
|
||||
netgen -ofmt verilog -sim -tm axi4_bram_1kx64_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
|
||||
@@ -1,55 +0,0 @@
|
||||
#!/bin/sh
|
||||
rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
rem
|
||||
rem This file contains confidential and proprietary information
|
||||
rem of Xilinx, Inc. and is protected under U.S. and
|
||||
rem international copyright and other intellectual property
|
||||
rem laws.
|
||||
rem
|
||||
rem DISCLAIMER
|
||||
rem This disclaimer is not a license and does not grant any
|
||||
rem rights to the materials distributed herewith. Except as
|
||||
rem otherwise provided in a valid license issued to you by
|
||||
rem Xilinx, and to the maximum extent permitted by applicable
|
||||
rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
rem (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
rem including negligence, or under any other theory of
|
||||
rem liability) for any loss or damage of any kind or nature
|
||||
rem related to, arising under or in connection with these
|
||||
rem materials, including for any direct, or any indirect,
|
||||
rem special, incidental, or consequential loss or damage
|
||||
rem (including loss of data, profits, goodwill, or any type of
|
||||
rem loss or damage suffered as a result of any action brought
|
||||
rem by a third party) even if such damage or loss was
|
||||
rem reasonably foreseeable or Xilinx had been advised of the
|
||||
rem possibility of the same.
|
||||
rem
|
||||
rem CRITICAL APPLICATIONS
|
||||
rem Xilinx products are not designed or intended to be fail-
|
||||
rem safe, or for use in any application requiring fail-safe
|
||||
rem performance, such as life-support or safety devices or
|
||||
rem systems, Class III medical devices, nuclear facilities,
|
||||
rem applications related to the deployment of airbags, or any
|
||||
rem other applications that could lead to death, personal
|
||||
rem injury, or severe property or environmental damage
|
||||
rem (individually and collectively, "Critical
|
||||
rem Applications"). Customer assumes the sole risk and
|
||||
rem liability of any use of Xilinx products in Critical
|
||||
rem Applications, subject only to applicable laws and
|
||||
rem regulations governing limitations on product liability.
|
||||
rem
|
||||
rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
rem PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
rem -----------------------------------------------------------------------------
|
||||
rem Script to synthesize and implement the Coregen FIFO Generator
|
||||
rem -----------------------------------------------------------------------------
|
||||
rmdir /S /Q results
|
||||
mkdir results
|
||||
cd results
|
||||
copy ..\..\..\axi4_bram_1kx64.ngc .
|
||||
planAhead -mode batch -source ..\planAhead_ise.tcl
|
||||
@@ -1,55 +0,0 @@
|
||||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
# Script to synthesize and implement the Coregen FIFO Generator
|
||||
#-----------------------------------------------------------------------------
|
||||
rm -rf results
|
||||
mkdir results
|
||||
cd results
|
||||
cp ../../../axi4_bram_1kx64.ngc .
|
||||
planAhead -mode batch -source ../planAhead_ise.tcl
|
||||
@@ -1,67 +0,0 @@
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
|
||||
set device xc7k410tffg900-2
|
||||
set projName axi4_bram_1kx64
|
||||
set design axi4_bram_1kx64
|
||||
set projDir [file dirname [info script]]
|
||||
create_project $projName $projDir/results/$projName -part $device -force
|
||||
set_property design_mode RTL [current_fileset -srcset]
|
||||
set top_module axi4_bram_1kx64_exdes
|
||||
add_files -norecurse {../../example_design/axi4_bram_1kx64_exdes.vhd}
|
||||
add_files -norecurse {./axi4_bram_1kx64.ngc}
|
||||
import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/axi4_bram_1kx64_exdes.xdc}
|
||||
set_property top axi4_bram_1kx64_exdes [get_property srcset [current_run]]
|
||||
synth_design
|
||||
opt_design
|
||||
place_design
|
||||
route_design
|
||||
write_sdf -rename_top_module axi4_bram_1kx64_exdes -file routed.sdf
|
||||
write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module axi4_bram_1kx64_exdes routed.v
|
||||
report_timing -nworst 30 -path_type full -file routed.twr
|
||||
report_drc -file report.drc
|
||||
write_bitstream -bitgen_options {-g UnconstrainedPins:Allow}
|
||||
@@ -1 +0,0 @@
|
||||
work ../example_design/axi4_bram_1kx64_exdes.vhd
|
||||
@@ -1,13 +0,0 @@
|
||||
run
|
||||
-ifmt VHDL
|
||||
-ent axi4_bram_1kx64_exdes
|
||||
-p xc7k410t-ffg900-2
|
||||
-ifn xst.prj
|
||||
-write_timing_constraints No
|
||||
-iobuf YES
|
||||
-max_fanout 100
|
||||
-ofn axi4_bram_1kx64_exdes
|
||||
-ofmt NGC
|
||||
-bus_delimiter ()
|
||||
-hierarchy_separator /
|
||||
-case Maintain
|
||||
@@ -1,117 +0,0 @@
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Address Generator
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: addr_gen.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Address Generator
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.ALL;
|
||||
|
||||
ENTITY ADDR_GEN IS
|
||||
GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
|
||||
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
|
||||
RST_INC : INTEGER := 0);
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RST : IN STD_LOGIC;
|
||||
EN : IN STD_LOGIC;
|
||||
LOAD :IN STD_LOGIC;
|
||||
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
|
||||
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
|
||||
);
|
||||
END ADDR_GEN;
|
||||
|
||||
ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
|
||||
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
|
||||
BEGIN
|
||||
ADDR_OUT <= ADDR_TEMP;
|
||||
PROCESS(CLK)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLK)) THEN
|
||||
IF(RST='1') THEN
|
||||
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
|
||||
ELSE
|
||||
IF(EN='1') THEN
|
||||
IF(LOAD='1') THEN
|
||||
ADDR_TEMP <=LOAD_VALUE;
|
||||
ELSE
|
||||
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
|
||||
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
|
||||
ELSE
|
||||
ADDR_TEMP <= ADDR_TEMP + '1';
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
END ARCHITECTURE;
|
||||
@@ -1,360 +0,0 @@
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: axi4_bram_1kx64_synth.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Synthesizable Testbench
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
USE IEEE.STD_LOGIC_MISC.ALL;
|
||||
|
||||
LIBRARY STD;
|
||||
USE STD.TEXTIO.ALL;
|
||||
|
||||
--LIBRARY unisim;
|
||||
--USE unisim.vcomponents.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.ALL;
|
||||
USE work.BMG_TB_PKG.ALL;
|
||||
|
||||
ENTITY axi4_bram_1kx64_synth IS
|
||||
PORT(
|
||||
CLK_IN : IN STD_LOGIC;
|
||||
RESET_IN : IN STD_LOGIC;
|
||||
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
|
||||
);
|
||||
END ENTITY;
|
||||
|
||||
ARCHITECTURE axi4_bram_1kx64_synth_ARCH OF axi4_bram_1kx64_synth IS
|
||||
|
||||
|
||||
COMPONENT axi4_bram_1kx64_exdes
|
||||
PORT (
|
||||
-- AXI BMG Input and Output Port Declarations
|
||||
|
||||
-- AXI Global Signals
|
||||
S_ACLK : IN STD_LOGIC;
|
||||
|
||||
-- AXI Full/Lite Slave Write (write side)
|
||||
S_AXI_AWID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_AWVALID : IN STD_LOGIC;
|
||||
S_AXI_AWREADY : OUT STD_LOGIC;
|
||||
S_AXI_WDATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_WLAST : IN STD_LOGIC;
|
||||
S_AXI_WVALID : IN STD_LOGIC;
|
||||
S_AXI_WREADY : OUT STD_LOGIC;
|
||||
S_AXI_BID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_BVALID : OUT STD_LOGIC;
|
||||
S_AXI_BREADY : IN STD_LOGIC;
|
||||
|
||||
-- AXI Full/Lite Slave Read (Write side)
|
||||
S_AXI_ARID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_ARVALID : IN STD_LOGIC;
|
||||
S_AXI_ARREADY : OUT STD_LOGIC;
|
||||
S_AXI_RID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_RLAST : OUT STD_LOGIC;
|
||||
S_AXI_RVALID : OUT STD_LOGIC;
|
||||
S_AXI_RREADY : IN STD_LOGIC;
|
||||
|
||||
-- AXI Full/Lite Sideband Signals
|
||||
S_ARESETN : IN STD_LOGIC
|
||||
|
||||
);
|
||||
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
SIGNAL CLKA: STD_LOGIC := '0';
|
||||
SIGNAL RSTA: STD_LOGIC := '0';
|
||||
SIGNAL S_ACLK: STD_LOGIC := '0';
|
||||
SIGNAL S_ARESETN: STD_LOGIC := '0';
|
||||
SIGNAL S_AXI_AWID: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL S_AXI_AWADDR: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL S_AXI_AWLEN: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL S_AXI_AWSIZE: STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL S_AXI_AWBURST: STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL S_AXI_AWVALID: STD_LOGIC := '0';
|
||||
SIGNAL S_AXI_AWREADY: STD_LOGIC;
|
||||
SIGNAL S_AXI_WDATA: STD_LOGIC_VECTOR( 63 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL S_AXI_WSTRB: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL S_AXI_WLAST: STD_LOGIC := '0';
|
||||
SIGNAL S_AXI_WVALID: STD_LOGIC := '0';
|
||||
SIGNAL S_AXI_WREADY: STD_LOGIC;
|
||||
SIGNAL S_AXI_BID: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL S_AXI_ARID: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL S_AXI_RID: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL S_AXI_BRESP: STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
SIGNAL S_AXI_BVALID: STD_LOGIC;
|
||||
SIGNAL S_AXI_BREADY: STD_LOGIC := '0';
|
||||
SIGNAL S_AXI_ARLEN: STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL S_AXI_ARSIZE: STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL S_AXI_ARBURST: STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL S_AXI_RLAST: STD_LOGIC;
|
||||
SIGNAL S_AXI_ARADDR: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL S_AXI_ARVALID: STD_LOGIC := '0';
|
||||
SIGNAL S_AXI_ARREADY: STD_LOGIC;
|
||||
SIGNAL S_AXI_RDATA: STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
SIGNAL S_AXI_RRESP: STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
SIGNAL S_AXI_RVALID: STD_LOGIC;
|
||||
SIGNAL S_AXI_RREADY: STD_LOGIC := '0';
|
||||
SIGNAL CHECKER_EN : STD_LOGIC:='0';
|
||||
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
|
||||
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
|
||||
SIGNAL clk_in_i: STD_LOGIC;
|
||||
SIGNAL RESET_SYNC_R1 : STD_LOGIC;
|
||||
SIGNAL RESET_SYNC_R2 : STD_LOGIC;
|
||||
SIGNAL RESET_SYNC_R3 : STD_LOGIC;
|
||||
|
||||
SIGNAL ITER_R0 : STD_LOGIC := '0';
|
||||
SIGNAL ITER_R1 : STD_LOGIC := '0';
|
||||
SIGNAL ITER_R2 : STD_LOGIC := '0';
|
||||
|
||||
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
|
||||
|
||||
BEGIN
|
||||
|
||||
-- clk_buf: bufg
|
||||
-- PORT map(
|
||||
-- i => CLK_IN,
|
||||
-- o => clk_in_i
|
||||
-- );
|
||||
clk_in_i <= CLK_IN;
|
||||
CLKA <= clk_in_i;
|
||||
|
||||
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
|
||||
|
||||
S_AClk <= clk_in_i;
|
||||
S_ARESETN<=NOT RESET_SYNC_R3 AFTER 50 ns;
|
||||
|
||||
PROCESS(clk_in_i)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(clk_in_i)) THEN
|
||||
RESET_SYNC_R1 <= RESET_IN;
|
||||
RESET_SYNC_R2 <= RESET_SYNC_R1;
|
||||
RESET_SYNC_R3 <= RESET_SYNC_R2;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
PROCESS(CLKA)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLKA)) THEN
|
||||
IF(RESET_SYNC_R3='1') THEN
|
||||
ISSUE_FLAG_STATUS<= (OTHERS => '0');
|
||||
ELSE
|
||||
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
|
||||
|
||||
BMG_DATA_CHECKER_INST: ENTITY work.AXI_CHECKER
|
||||
PORT MAP (
|
||||
CLK => S_AClk,
|
||||
RST => RSTA,
|
||||
EN => CHECKER_EN,
|
||||
DATA_IN => S_AXI_RDATA,
|
||||
STATUS => ISSUE_FLAG(0)
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
BMG_STIM_GEN_INST: ENTITY work.BMG_STIM_GEN
|
||||
PORT MAP (
|
||||
S_AClk => S_AClk,
|
||||
S_ARESETN => S_ARESETN,
|
||||
S_AXI_AWADDR =>S_AXI_AWADDR,
|
||||
S_AXI_AWVALID =>S_AXI_AWVALID,
|
||||
S_AXI_AWREADY =>S_AXI_AWREADY,
|
||||
s_axi_awid => S_AXI_AWID,
|
||||
S_AXI_BID => S_AXI_BID,
|
||||
s_axi_arid => S_AXI_ARID,
|
||||
S_AXI_RID =>S_AXI_RID,
|
||||
S_AXI_AWLEN => S_AXI_AWLEN,
|
||||
S_AXI_AWSIZE => S_AXI_AWSIZE,
|
||||
S_AXI_AWBURST => S_AXI_AWBURST,
|
||||
S_AXI_WDATA =>S_AXI_WDATA,
|
||||
S_AXI_WSTRB =>S_AXI_WSTRB,
|
||||
S_AXI_WLAST => S_AXI_WLAST,
|
||||
S_AXI_WVALID =>S_AXI_WVALID,
|
||||
S_AXI_WREADY =>S_AXI_WREADY,
|
||||
S_AXI_BRESP =>S_AXI_BRESP,
|
||||
S_AXI_BVALID =>S_AXI_BVALID,
|
||||
S_AXI_BREADY =>S_AXI_BREADY,
|
||||
S_AXI_ARADDR =>S_AXI_ARADDR,
|
||||
S_AXI_ARVALID =>S_AXI_ARVALID,
|
||||
S_AXI_ARREADY =>S_AXI_ARREADY,
|
||||
S_AXI_ARLEN => S_AXI_ARLEN,
|
||||
S_AXI_ARSIZE => S_AXI_ARSIZE,
|
||||
S_AXI_ARBURST => S_AXI_ARBURST,
|
||||
S_AXI_RDATA =>S_AXI_RDATA,
|
||||
S_AXI_RRESP =>S_AXI_RRESP,
|
||||
S_AXI_RVALID => S_AXI_RVALID,
|
||||
S_AXI_RREADY =>S_AXI_RREADY,
|
||||
S_AXI_RLAST => S_AXI_RLAST,
|
||||
CHECK_RDATA => CHECKER_EN,
|
||||
ERROR_FLAG => ISSUE_FLAG(7 DOWNTO 1)
|
||||
);
|
||||
|
||||
PROCESS(S_AClk)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(S_AClk)) THEN
|
||||
IF(RESET_SYNC_R3='1') THEN
|
||||
STATUS(8) <= '0';
|
||||
iter_r2 <= '0';
|
||||
iter_r1 <= '0';
|
||||
iter_r0 <= '0';
|
||||
ELSE
|
||||
STATUS(8) <= iter_r2;
|
||||
iter_r2 <= iter_r1;
|
||||
iter_r1 <= iter_r0;
|
||||
iter_r0 <= STIMULUS_FLOW(8);
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
PROCESS(S_AClk)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(S_AClk)) THEN
|
||||
IF(RESET_SYNC_R3='1') THEN
|
||||
STIMULUS_FLOW <= (OTHERS => '0');
|
||||
ELSIF(S_AXI_AWVALID='1') THEN
|
||||
STIMULUS_FLOW <= STIMULUS_FLOW+1;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
|
||||
|
||||
BMG_PORT: axi4_bram_1kx64_exdes PORT MAP (
|
||||
-- AXI BMG Input and Output Port Declarations
|
||||
--Global Signals
|
||||
S_ACLK => S_ACLK,
|
||||
--AXI Full/Lite Slave
|
||||
S_AXI_AWID => S_AXI_AWID,
|
||||
S_AXI_AWADDR =>S_AXI_AWADDR,
|
||||
S_AXI_AWLEN =>S_AXI_AWLEN,
|
||||
S_AXI_AWSIZE => S_AXI_AWSIZE,
|
||||
S_AXI_AWBURST => S_AXI_AWBURST,
|
||||
S_AXI_AWVALID =>S_AXI_AWVALID,
|
||||
S_AXI_AWREADY =>S_AXI_AWREADY,
|
||||
S_AXI_WDATA =>S_AXI_WDATA,
|
||||
S_AXI_WSTRB =>S_AXI_WSTRB,
|
||||
S_AXI_WLAST =>S_AXI_WLAST,
|
||||
S_AXI_WVALID =>S_AXI_WVALID,
|
||||
S_AXI_WREADY =>S_AXI_WREADY,
|
||||
S_AXI_BID =>S_AXI_BID,
|
||||
S_AXI_BRESP =>S_AXI_BRESP,
|
||||
S_AXI_BVALID =>S_AXI_BVALID,
|
||||
S_AXI_BREADY =>S_AXI_BREADY,
|
||||
-- AXI Full/Lite Slave Read (Write side)
|
||||
S_AXI_ARID =>S_AXI_ARID,
|
||||
S_AXI_ARADDR =>S_AXI_ARADDR,
|
||||
S_AXI_ARLEN =>S_AXI_ARLEN,
|
||||
S_AXI_ARSIZE =>S_AXI_ARSIZE,
|
||||
S_AXI_ARBURST =>S_AXI_ARBURST,
|
||||
S_AXI_ARVALID =>S_AXI_ARVALID,
|
||||
S_AXI_ARREADY =>S_AXI_ARREADY,
|
||||
S_AXI_RID =>S_AXI_RID,
|
||||
S_AXI_RDATA =>S_AXI_RDATA,
|
||||
S_AXI_RRESP =>S_AXI_RRESP,
|
||||
S_AXI_RLAST => S_AXI_RLAST,
|
||||
S_AXI_RVALID => S_AXI_RVALID,
|
||||
S_AXI_RREADY =>S_AXI_RREADY,
|
||||
-- AXI Full/Lite Sid=>
|
||||
S_ARESETN => S_ARESETN
|
||||
|
||||
);
|
||||
END ARCHITECTURE;
|
||||
@@ -1,134 +0,0 @@
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Filename: axi4_bram_1kx64_tb.vhd
|
||||
-- Description:
|
||||
-- Testbench Top
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.ALL;
|
||||
|
||||
ENTITY axi4_bram_1kx64_tb IS
|
||||
END ENTITY;
|
||||
|
||||
|
||||
ARCHITECTURE axi4_bram_1kx64_tb_ARCH OF axi4_bram_1kx64_tb IS
|
||||
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||
SIGNAL CLK : STD_LOGIC := '1';
|
||||
SIGNAL RESET : STD_LOGIC;
|
||||
|
||||
BEGIN
|
||||
|
||||
|
||||
CLK_GEN: PROCESS BEGIN
|
||||
CLK <= NOT CLK;
|
||||
WAIT FOR 100 NS;
|
||||
CLK <= NOT CLK;
|
||||
WAIT FOR 100 NS;
|
||||
END PROCESS;
|
||||
|
||||
RST_GEN: PROCESS BEGIN
|
||||
RESET <= '1';
|
||||
WAIT FOR 1000 NS;
|
||||
RESET <= '0';
|
||||
WAIT;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
--STOP_SIM: PROCESS BEGIN
|
||||
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
|
||||
-- ASSERT FALSE
|
||||
-- REPORT "END SIMULATION TIME REACHED"
|
||||
-- SEVERITY FAILURE;
|
||||
--END PROCESS;
|
||||
--
|
||||
PROCESS BEGIN
|
||||
WAIT UNTIL STATUS(8)='1';
|
||||
IF( STATUS(7 downto 0)/="0") THEN
|
||||
ASSERT false
|
||||
REPORT "Test Completed Successfully"
|
||||
SEVERITY NOTE;
|
||||
REPORT "Simulation Failed"
|
||||
SEVERITY FAILURE;
|
||||
ELSE
|
||||
ASSERT false
|
||||
REPORT "TEST PASS"
|
||||
SEVERITY NOTE;
|
||||
REPORT "Test Completed Successfully"
|
||||
SEVERITY FAILURE;
|
||||
END IF;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
axi4_bram_1kx64_synth_inst:ENTITY work.axi4_bram_1kx64_synth
|
||||
PORT MAP(
|
||||
CLK_IN => CLK,
|
||||
RESET_IN => RESET,
|
||||
STATUS => STATUS
|
||||
);
|
||||
|
||||
END ARCHITECTURE;
|
||||
@@ -1,146 +0,0 @@
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Stimulus Generator for AXI FULL
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_2012 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: bmg_axi_full_stim_gen.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Stimulus Generator For AXI FULL Configuration
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
LIBRARY work;
|
||||
USE work.BMG_TB_PKG.ALL;
|
||||
|
||||
ENTITY AXI_CHECKER IS
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RST : IN STD_LOGIC;
|
||||
EN : IN STD_LOGIC;
|
||||
DATA_IN : IN STD_LOGIC_VECTOR (63 DOWNTO 0); --OUTPUT VECTOR
|
||||
STATUS : OUT STD_LOGIC:= '0'
|
||||
);
|
||||
END AXI_CHECKER;
|
||||
|
||||
ARCHITECTURE CHECKER_ARCH OF AXI_CHECKER IS
|
||||
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
SIGNAL DATA_IN_I: STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
SIGNAL EN_R : STD_LOGIC := '0';
|
||||
|
||||
BEGIN
|
||||
|
||||
PROCESS(CLK)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLK)) THEN
|
||||
IF(RST='1') THEN
|
||||
DATA_IN_I<=(OTHERS=>'0');
|
||||
ELSE
|
||||
DATA_IN_I<=DATA_IN;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
PROCESS(CLK)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLK)) THEN
|
||||
IF(RST= '1') THEN
|
||||
EN_R <= '0';
|
||||
ELSE
|
||||
EN_R <= EN;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
|
||||
GENERIC MAP ( DATA_GEN_WIDTH =>64,
|
||||
DOUT_WIDTH => 64 ,
|
||||
DATA_PART_CNT => 1,
|
||||
SEED => 2
|
||||
)
|
||||
|
||||
PORT MAP (
|
||||
CLK =>CLK,
|
||||
RST => RST,
|
||||
EN => EN,
|
||||
DATA_OUT => EXPECTED_DATA
|
||||
);
|
||||
|
||||
|
||||
PROCESS(CLK)
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLK)) THEN
|
||||
IF(EN_R='1') THEN
|
||||
IF(EXPECTED_DATA = DATA_IN_I) THEN
|
||||
STATUS<='0';
|
||||
ELSE
|
||||
STATUS <= '1';
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
|
||||
END ARCHITECTURE;
|
||||
@@ -1,289 +0,0 @@
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Protocol Checker for AXI
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: bmg_axi_protocol_chkr.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Protocol Checker For AXI Configuration
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
USE IEEE.STD_LOGIC_MISC.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.ALL;
|
||||
USE work.BMG_TB_PKG.ALL;
|
||||
|
||||
ENTITY BMG_AXI_FULL_PROTOCOL_CHKR IS
|
||||
PORT (
|
||||
S_ACLK : IN STD_LOGIC := '0';
|
||||
S_ARESETN : IN STD_LOGIC := '0';
|
||||
S_AXI_AWID : IN STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
|
||||
S_AXI_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
|
||||
S_AXI_ARID : IN STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
|
||||
S_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
|
||||
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
|
||||
S_AXI_WLAST : IN STD_LOGIC := '0';
|
||||
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
|
||||
S_AXI_RLAST : IN STD_LOGIC;
|
||||
S_AXI_AWVALID : IN STD_LOGIC := '0';
|
||||
S_AXI_AWREADY : IN STD_LOGIC;
|
||||
S_AXI_WVALID : IN STD_LOGIC := '0';
|
||||
S_AXI_WREADY : IN STD_LOGIC;
|
||||
S_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_BVALID : IN STD_LOGIC;
|
||||
S_AXI_BREADY : IN STD_LOGIC := '0';
|
||||
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
S_AXI_ARVALID : IN STD_LOGIC := '0';
|
||||
S_AXI_ARREADY : IN STD_LOGIC;
|
||||
S_AXI_RRESP : IN STD_LOGIC_VECTOR(2-1 DOWNTO 0);
|
||||
S_AXI_RVALID : IN STD_LOGIC;
|
||||
S_AXI_RREADY : IN STD_LOGIC := '0';
|
||||
ERROR_FLAG : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS=>'0') --Some Signals are kept open intentionally to add logic if the user needs more checks on the AXI Protocol
|
||||
);
|
||||
END BMG_AXI_FULL_PROTOCOL_CHKR;
|
||||
|
||||
|
||||
ARCHITECTURE BEHAVIORAL OF BMG_AXI_FULL_PROTOCOL_CHKR IS
|
||||
SIGNAL axi_wready_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0) :=(OTHERS=>'0');
|
||||
SIGNAL wready_timeout : STD_LOGIC :='0';
|
||||
SIGNAL axi_awready_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0) :=(OTHERS=>'0');
|
||||
SIGNAL awready_timeout : STD_LOGIC :='0';
|
||||
SIGNAL axi_arready_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0) :=(OTHERS=>'0');
|
||||
SIGNAL arready_timeout : STD_LOGIC :='0';
|
||||
type memory_type is array (3 downto 0) of std_logic_vector(0 downto 0);
|
||||
SIGNAL awid_mem : memory_type :=(others=>(others=>'0'));
|
||||
SIGNAL awid_wr_ptr : STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS=>'0');
|
||||
SIGNAL awid_rd_ptr : STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS=>'0');
|
||||
SIGNAL arid_mem : memory_type :=(others=>(others=>'0'));
|
||||
SIGNAL arid_wr_ptr : STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS=>'0');
|
||||
SIGNAL arid_rd_ptr : STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS=>'0');
|
||||
|
||||
BEGIN
|
||||
--------------------------------------------------------------------------
|
||||
------- AWREADY TIMEOUT CHECKER --------------
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
awready_timeout <= AND_REDUCE(axi_awready_cnt);
|
||||
|
||||
AWREADY_ERROR_FLAG:PROCESS(S_ACLK,S_ARESETN)
|
||||
BEGIN
|
||||
IF(S_ARESETN = '0') THEN
|
||||
ERROR_FLAG(0) <='0';
|
||||
ELSIF(RISING_EDGE(S_ACLK)) THEN
|
||||
IF(awready_timeout='1') THEN
|
||||
ERROR_FLAG(0)<='1';
|
||||
ELSIF(S_AXI_AWREADY='1') THEN
|
||||
ERROR_FLAG(0)<='0';
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
AWREADY_CNT_PROCESS: PROCESS(S_ACLK,S_ARESETN)
|
||||
BEGIN
|
||||
IF(S_ARESETN = '0') THEN
|
||||
axi_awready_cnt <= (OTHERS=>'0');
|
||||
ELSIF(RISING_EDGE(S_ACLK)) THEN
|
||||
IF(S_AXI_AWVALID='1' AND S_AXI_AWREADY='0') THEN
|
||||
axi_awready_cnt <= axi_awready_cnt+1;
|
||||
ELSIF(S_AXI_AWVALID='1' AND S_AXI_AWREADY='1') THEN
|
||||
axi_awready_cnt <= (OTHERS=>'0');
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
------- WREADY TIMEOUT CHECKER --------------
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
wready_timeout <= AND_REDUCE(axi_wready_cnt);
|
||||
|
||||
PROCESS(S_ACLK,S_ARESETN)
|
||||
BEGIN
|
||||
IF(S_ARESETN = '0') THEN
|
||||
ERROR_FLAG(1) <='0';
|
||||
ELSIF(RISING_EDGE(S_ACLK)) THEN
|
||||
IF(wready_timeout='1') THEN
|
||||
ERROR_FLAG(1)<='1';
|
||||
ELSIF(S_AXI_WREADY='1') THEN
|
||||
ERROR_FLAG(1)<='0';
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(S_ACLK,S_ARESETN)
|
||||
BEGIN
|
||||
IF(S_ARESETN = '0') THEN
|
||||
axi_wready_cnt <= (OTHERS=>'0');
|
||||
ELSIF(RISING_EDGE(S_ACLK)) THEN
|
||||
IF(S_AXI_WVALID='1' AND S_AXI_WREADY='0') THEN
|
||||
axi_wready_cnt <= axi_wready_cnt+1;
|
||||
ELSIF(S_AXI_WVALID='1' AND S_AXI_WREADY='1') THEN
|
||||
axi_wready_cnt <= (OTHERS=>'0');
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
------- AWID/BID CHECKER --------------
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
AWID_WR_TO_MEM: PROCESS(S_AClk,S_ARESETN)
|
||||
BEGIN
|
||||
IF(S_ARESETN = '0') THEN
|
||||
awid_wr_ptr <=(OTHERS=>'0');
|
||||
ELSIF(RISING_EDGE(S_ACLK)) THEN
|
||||
IF(S_AXI_AWVALID='1' AND S_AXI_AWREADY='1') THEN
|
||||
awid_mem(conv_integer(awid_wr_ptr)) <= S_AXI_AWID(0 downto 0);
|
||||
awid_wr_ptr <= awid_wr_ptr+'1';
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
AWID_WID_CHECK: PROCESS(S_ACLK,S_ARESETN)
|
||||
BEGIN
|
||||
IF(S_ARESETN = '0') THEN
|
||||
ERROR_FLAG(2) <='0';
|
||||
awid_rd_ptr <= (OTHERS=>'0');
|
||||
ELSIF(RISING_EDGE(S_ACLK)) THEN
|
||||
IF(S_AXI_BVALID='1') THEN
|
||||
IF(S_AXI_BID = awid_mem(conv_integer(awid_rd_ptr))) THEN
|
||||
awid_rd_ptr <= awid_rd_ptr+'1';
|
||||
ELSE
|
||||
ERROR_FLAG(2) <='1';
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
ARID_WR_TO_MEM: PROCESS(S_AClk,S_ARESETN)
|
||||
BEGIN
|
||||
IF(S_ARESETN = '0') THEN
|
||||
arid_wr_ptr <=(OTHERS=>'0');
|
||||
ELSIF(RISING_EDGE(S_ACLK)) THEN
|
||||
IF(S_AXI_ARVALID='1' AND S_AXI_ARREADY='1') THEN
|
||||
arid_mem(conv_integer(arid_wr_ptr)) <= S_AXI_ARID(0 downto 0);
|
||||
arid_wr_ptr <= arid_wr_ptr+'1';
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
ARID_RID_CHECK: PROCESS(S_ACLK,S_ARESETN)
|
||||
BEGIN
|
||||
IF(S_ARESETN = '0') THEN
|
||||
ERROR_FLAG(3) <='0';
|
||||
arid_rd_ptr <= (OTHERS=>'0');
|
||||
ELSIF(RISING_EDGE(S_ACLK)) THEN
|
||||
IF(S_AXI_RVALID='1' AND S_AXI_RREADY='1') THEN
|
||||
IF(S_AXI_RID = arid_mem(conv_integer(arid_rd_ptr))) THEN
|
||||
IF(S_AXI_RLAST='1') THEN
|
||||
arid_rd_ptr <= arid_rd_ptr+'1';
|
||||
END IF;
|
||||
ELSE
|
||||
ERROR_FLAG(3) <='1';
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
------- ARREADY TIMEOUT CHECKER --------------
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
arready_timeout <= AND_REDUCE(axi_arready_cnt);
|
||||
|
||||
ARREADY_ERROR_FLAG:PROCESS(S_ACLK,S_ARESETN)
|
||||
BEGIN
|
||||
IF(S_ARESETN = '0') THEN
|
||||
ERROR_FLAG(4) <='0';
|
||||
ELSIF(RISING_EDGE(S_ACLK)) THEN
|
||||
IF(arready_timeout='1') THEN
|
||||
ERROR_FLAG(4)<='1';
|
||||
ELSIF(S_AXI_ARREADY='1') THEN
|
||||
ERROR_FLAG(4)<='0';
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
ARREADY_CNT_PROCESS: PROCESS(S_ACLK,S_ARESETN)
|
||||
BEGIN
|
||||
IF(S_ARESETN = '0') THEN
|
||||
axi_arready_cnt <= (OTHERS=>'0');
|
||||
ELSIF(RISING_EDGE(S_ACLK)) THEN
|
||||
IF(S_AXI_ARVALID='1' AND S_AXI_ARREADY='0') THEN
|
||||
axi_arready_cnt <= axi_arready_cnt+1;
|
||||
ELSIF(S_AXI_ARVALID='1' AND S_AXI_ARREADY='1') THEN
|
||||
axi_arready_cnt <= (OTHERS=>'0');
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
END ARCHITECTURE;
|
||||
@@ -1,536 +0,0 @@
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Stimulus Generator for AXI FULL
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: bmg_stim_gen.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Stimulus Generator For AXI FULL Configuration
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
USE IEEE.STD_LOGIC_MISC.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.ALL;
|
||||
USE work.BMG_TB_PKG.ALL;
|
||||
|
||||
ENTITY BMG_STIM_GEN IS
|
||||
PORT (
|
||||
S_ACLK : IN STD_LOGIC := '0';
|
||||
S_ARESETN : IN STD_LOGIC := '0';
|
||||
S_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
|
||||
S_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
S_AXI_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
|
||||
S_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
|
||||
S_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
|
||||
S_AXI_AWVALID : OUT STD_LOGIC := '0';
|
||||
S_AXI_AWREADY : IN STD_LOGIC;
|
||||
S_AXI_WDATA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
|
||||
S_AXI_WSTRB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
|
||||
S_AXI_WLAST : OUT STD_LOGIC := '0';
|
||||
S_AXI_WVALID : OUT STD_LOGIC := '0';
|
||||
S_AXI_WREADY : IN STD_LOGIC;
|
||||
S_AXI_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
|
||||
S_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_BVALID : IN STD_LOGIC;
|
||||
S_AXI_BREADY : OUT STD_LOGIC := '0';
|
||||
S_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
|
||||
S_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
S_AXI_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
|
||||
S_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
|
||||
S_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
|
||||
S_AXI_ARVALID : OUT STD_LOGIC := '0';
|
||||
S_AXI_ARREADY : IN STD_LOGIC;
|
||||
S_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
|
||||
S_AXI_RDATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
S_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
S_AXI_RLAST : IN STD_LOGIC;
|
||||
S_AXI_RVALID : IN STD_LOGIC;
|
||||
S_AXI_RREADY : OUT STD_LOGIC := '0';
|
||||
CHECK_RDATA : OUT STD_LOGIC := '0';
|
||||
ERROR_FLAG : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS=>'0')
|
||||
);
|
||||
END BMG_STIM_GEN;
|
||||
|
||||
|
||||
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
|
||||
|
||||
CONSTANT WR_RD_DEEP_COUNT : INTEGER:=2;
|
||||
CONSTANT WAIT_ENABLE : STD_LOGIC_VECTOR (1 DOWNTO 0) := "01";
|
||||
CONSTANT SEND_ADDR_CMD : STD_LOGIC_VECTOR (1 DOWNTO 0) := "10";
|
||||
CONSTANT WAIT_BVALID : STD_LOGIC_VECTOR (1 DOWNTO 0) := "11";
|
||||
CONSTANT RD_WAIT_ENABLE : STD_LOGIC_VECTOR (1 DOWNTO 0) := "01";
|
||||
CONSTANT RD_SEND_ADDR_CMD : STD_LOGIC_VECTOR (1 DOWNTO 0) := "10";
|
||||
CONSTANT RD_WAIT_RVALID : STD_LOGIC_VECTOR (1 DOWNTO 0) := "11";
|
||||
CONSTANT CNT_ZERO : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL S_AXI_RREADY_OSC_I : STD_LOGIC:= '0';
|
||||
SIGNAL RD_COUNT : INTEGER:= WR_RD_DEEP_COUNT;
|
||||
SIGNAL WR_COUNT : INTEGER:= WR_RD_DEEP_COUNT;
|
||||
SIGNAL AXI_WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL S_AXI_AWADDR_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL S_AXI_ARADDR_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL AXI_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL AXI_ARID_INT : STD_LOGIC_VECTOR(0 DOWNTO 0):=(OTHERS => '0');
|
||||
SIGNAL AXI_AWID_INT : STD_LOGIC_VECTOR(0 DOWNTO 0):=(OTHERS => '0');
|
||||
SIGNAL WDATA_CNT : STD_LOGIC_VECTOR(7 DOWNTO 0):=(OTHERS=>'0');
|
||||
SIGNAL LEN_COUNT : STD_LOGIC_VECTOR(7 DOWNTO 0):=(OTHERS=>'0');
|
||||
SIGNAL RD_LEN_COUNT : STD_LOGIC_VECTOR(7 DOWNTO 0):=(OTHERS=>'0');
|
||||
SIGNAL S_AXI_AWLEN_I : STD_LOGIC_VECTOR(7 DOWNTO 0):=(OTHERS=>'0');
|
||||
SIGNAL S_AXI_ARLEN_I : STD_LOGIC_VECTOR(7 DOWNTO 0):=(OTHERS=>'0');
|
||||
SIGNAL AXI_WRITE_GEN : STD_LOGIC := '0';
|
||||
SIGNAL AXI_READ_GEN : STD_LOGIC := '0';
|
||||
SIGNAL AXI_WDATA_GEN : STD_LOGIC := '0';
|
||||
SIGNAL DO_WRITE : STD_LOGIC := '0';
|
||||
SIGNAL DO_READ : STD_LOGIC := '0';
|
||||
SIGNAL RD_CURRENT_STATE : STD_LOGIC_VECTOR (1 DOWNTO 0) := RD_WAIT_ENABLE;
|
||||
SIGNAL RD_NEXT_STATE : STD_LOGIC_VECTOR (1 DOWNTO 0) := RD_WAIT_ENABLE;
|
||||
SIGNAL CURRENT_STATE : STD_LOGIC_VECTOR (1 DOWNTO 0) := WAIT_ENABLE;
|
||||
SIGNAL NEXT_STATE : STD_LOGIC_VECTOR (1 DOWNTO 0) := WAIT_ENABLE;
|
||||
SIGNAL AXI_WDATA : STD_LOGIC_VECTOR(63 DOWNTO 0):= (OTHERS => '0');
|
||||
SIGNAL S_AWVALID_I : STD_LOGIC := '0';
|
||||
SIGNAL S_ARVALID_I : STD_LOGIC := '0';
|
||||
SIGNAL S_WVALID_I : STD_LOGIC := '0';
|
||||
SIGNAL RST_INT : STD_LOGIC :='0';
|
||||
SIGNAL S_AXI_AWVALID_I : STD_LOGIC:='0';
|
||||
SIGNAL S_AXI_WVALID_I : STD_LOGIC:='0';
|
||||
SIGNAL S_AXI_RREADY_I : STD_LOGIC:= '0';
|
||||
SIGNAL RREADY_COUNT : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS=>'0');
|
||||
SIGNAL RD_COMPLETE : STD_LOGIC:='0';
|
||||
SIGNAL WR_COMPLETE : STD_LOGIC:='0';
|
||||
SIGNAL S_AXI_WLAST_I : STD_LOGIC:='0';
|
||||
SIGNAL AXI_NEXT_PKT_ADDR : STD_LOGIC :='0';
|
||||
SIGNAL AXI_NEXT_RD_ADDR : STD_LOGIC :='0';
|
||||
SIGNAL S_AXI_BREADY_I : STD_LOGIC:='0';
|
||||
|
||||
|
||||
CONSTANT NUM_OF_BYTES : INTEGER := 8 ;
|
||||
|
||||
CONSTANT C_RANGE : INTEGER := 3;
|
||||
|
||||
CONSTANT AXI_DEPTH: INTEGER:= 8192;
|
||||
|
||||
|
||||
|
||||
BEGIN
|
||||
|
||||
S_AXI_AWID <= AXI_AWID_INT;
|
||||
S_AXI_ARID <= AXI_ARID_INT;
|
||||
|
||||
RST_INT <= NOT S_ARESETN;
|
||||
|
||||
|
||||
|
||||
|
||||
REGISTER_FSM:
|
||||
PROCESS (S_ACLK, S_ARESETN)
|
||||
BEGIN
|
||||
IF(S_ARESETN = '0') THEN
|
||||
CURRENT_STATE <= WAIT_ENABLE;
|
||||
RD_CURRENT_STATE <= RD_WAIT_ENABLE;
|
||||
ELSIF(RISING_EDGE(S_ACLK)) THEN
|
||||
CURRENT_STATE <= NEXT_STATE;
|
||||
RD_CURRENT_STATE <= RD_NEXT_STATE;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (S_ACLK, S_ARESETN)
|
||||
BEGIN
|
||||
IF(S_ARESETN = '0') THEN
|
||||
AXI_AWID_INT <= (OTHERS => '0');
|
||||
AXI_ARID_INT <= (OTHERS => '0');
|
||||
ELSIF(RISING_EDGE(S_ACLK)) THEN
|
||||
IF(AXI_WRITE_GEN='1') THEN
|
||||
AXI_AWID_INT <= AXI_AWID_INT + '1';
|
||||
END IF;
|
||||
IF(AXI_READ_GEN='1') THEN
|
||||
AXI_ARID_INT <= AXI_ARID_INT + '1';
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
WR_COMPLETE <= '1' WHEN (WR_COUNT=WR_RD_DEEP_COUNT AND S_AXI_WLAST_I='1') ELSE '0';
|
||||
|
||||
WR_COUNT_PACKET: PROCESS(S_ACLK, S_ARESETN)
|
||||
BEGIN
|
||||
IF(S_ARESETN = '0') THEN
|
||||
WR_COUNT <= 0;
|
||||
ELSIF(RISING_EDGE(S_ACLK)) THEN
|
||||
IF(S_AXI_AWREADY='1' AND S_AXI_AWVALID_I='1') THEN
|
||||
WR_COUNT <= WR_COUNT+1;
|
||||
END IF;
|
||||
IF(WR_COUNT=WR_RD_DEEP_COUNT AND S_AXI_WLAST_I='1') THEN
|
||||
WR_COUNT<=0;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
RD_COMPLETE <= '1' WHEN (RD_COUNT=WR_RD_DEEP_COUNT AND (S_AXI_RLAST='1' AND S_AXI_RVALID='1' AND S_AXI_RREADY_I='1')) ELSE '0';
|
||||
|
||||
RD_COUNT_PACKET: PROCESS(S_ACLK, S_ARESETN)
|
||||
BEGIN
|
||||
IF(S_ARESETN = '0') THEN
|
||||
RD_COUNT <=0;
|
||||
ELSIF(RISING_EDGE(S_ACLK)) THEN
|
||||
IF(S_AXI_ARREADY='1' AND S_ARVALID_I='1') THEN
|
||||
RD_COUNT <= RD_COUNT+1;
|
||||
END IF;
|
||||
IF(RD_COUNT=WR_RD_DEEP_COUNT AND (S_AXI_RLAST='1' AND S_AXI_RVALID='1' AND S_AXI_RREADY_I='1')) THEN
|
||||
RD_COUNT<=0;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
RD_FSM_EN: PROCESS(S_ACLK)
|
||||
BEGIN
|
||||
IF(S_ARESETN='0') THEN
|
||||
DO_READ <='0';
|
||||
ELSIF(RISING_EDGE(S_ACLK)) THEN
|
||||
DO_READ <= (WR_COMPLETE);
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
WR_FSM_EN: PROCESS(S_ACLK)
|
||||
BEGIN
|
||||
IF(S_ARESETN='0') THEN
|
||||
DO_WRITE <='1';
|
||||
ELSIF(RISING_EDGE(S_ACLK)) THEN
|
||||
DO_WRITE <= (RD_COMPLETE);
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
--AXI_NEXT_PKT_ADDR <='1' WHEN (AXI_WRITE_GEN='1' AND ((AXI_WRITE_ADDR(11 DOWNTO 0)+((LEN_COUNT)*CONV_STD_LOGIC_VECTOR(NUM_OF_BYTES,6)))>=4096)) ELSE '0';
|
||||
AXI_NEXT_PKT_ADDR <='1' WHEN (AXI_WRITE_GEN='1' AND (((AXI_WRITE_ADDR(11 DOWNTO 0)+((LEN_COUNT)*CONV_STD_LOGIC_VECTOR(NUM_OF_BYTES,6)))>=4096) OR ((AXI_WRITE_ADDR(11 DOWNTO 0)+((LEN_COUNT)*CONV_STD_LOGIC_VECTOR(NUM_OF_BYTES,6)))>=AXI_DEPTH))) ELSE '0';
|
||||
|
||||
AXI_WR_ADDR_GEN: PROCESS(S_ACLK,S_ARESETN)
|
||||
BEGIN
|
||||
IF(S_ARESETN='0') THEN
|
||||
AXI_WRITE_ADDR <= (OTHERS=>'0');
|
||||
ELSIF(RISING_EDGE(S_ACLK)) THEN
|
||||
IF((AXI_WRITE_ADDR>=AXI_DEPTH ) ) THEN
|
||||
AXI_WRITE_ADDR <= (OTHERS=>'0');
|
||||
ELSIF(S_AXI_WREADY='1' AND S_AXI_WVALID_I='1') THEN
|
||||
AXI_WRITE_ADDR <= AXI_WRITE_ADDR + NUM_OF_BYTES;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(S_ACLK,S_ARESETN)
|
||||
BEGIN
|
||||
IF(S_ARESETN = '0') THEN
|
||||
S_AXI_AWLEN_I <= (OTHERS=> '0');
|
||||
ELSIF(RISING_EDGE(S_ACLK)) THEN
|
||||
IF(AXI_WRITE_GEN='1') THEN
|
||||
IF(AXI_NEXT_PKT_ADDR='0') THEN
|
||||
S_AXI_AWLEN_I(3 DOWNTO 0) <= AXI_WRITE_ADDR(7 DOWNTO 4);
|
||||
ELSE
|
||||
S_AXI_AWLEN_I(3 DOWNTO 0) <= (OTHERS=> '0');
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
-- AXI_NEXT_RD_ADDR <='1' WHEN (AXI_READ_GEN='1' AND ((AXI_READ_ADDR(11 DOWNTO 0)+((RD_LEN_COUNT)*CONV_STD_LOGIC_VECTOR(NUM_OF_BYTES,6)))>=4096)) ELSE '0';
|
||||
AXI_NEXT_RD_ADDR <='1' WHEN (AXI_READ_GEN='1' AND (((AXI_READ_ADDR(11 DOWNTO 0)+((RD_LEN_COUNT)*CONV_STD_LOGIC_VECTOR(NUM_OF_BYTES,6)))>=4096) OR ((AXI_READ_ADDR(11 DOWNTO 0)+((RD_LEN_COUNT)*CONV_STD_LOGIC_VECTOR(NUM_OF_BYTES,6)))>=AXI_DEPTH))) ELSE '0';
|
||||
|
||||
PROCESS(S_ACLK,S_ARESETN)
|
||||
BEGIN
|
||||
IF(S_ARESETN = '0') THEN
|
||||
S_AXI_ARLEN_I <= (OTHERS=> '0');
|
||||
ELSIF(RISING_EDGE(S_ACLK)) THEN
|
||||
IF(AXI_READ_GEN='1') THEN
|
||||
IF(AXI_NEXT_RD_ADDR='0') THEN
|
||||
S_AXI_ARLEN_I(3 DOWNTO 0) <= AXI_READ_ADDR(7 DOWNTO 4);
|
||||
ELSE
|
||||
S_AXI_ARLEN_I(3 DOWNTO 0) <= (OTHERS=> '0');
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
LEN_COUNT(3 DOWNTO 0) <= AXI_WRITE_ADDR(7 DOWNTO 4);
|
||||
AXI_WDATA_GEN <= S_AWVALID_I OR (S_AXI_WREADY AND S_AXI_WVALID_I AND (NOT (S_AXI_WLAST_I))) ;
|
||||
S_AXI_AWLEN <= (OTHERS => '0') AFTER 50 ns WHEN (S_AWVALID_I ='0') ELSE S_AXI_AWLEN_I AFTER 50 ns;
|
||||
RD_LEN_COUNT(3 DOWNTO 0) <= AXI_READ_ADDR(7 DOWNTO 4);
|
||||
S_AXI_ARLEN <= (OTHERS => '0') AFTER 50 ns WHEN (S_ARVALID_I ='0') ELSE S_AXI_ARLEN_I AFTER 50 ns;
|
||||
S_AXI_AWSIZE <= CONV_STD_LOGIC_VECTOR(C_RANGE,3);
|
||||
S_AXI_ARSIZE <= CONV_STD_LOGIC_VECTOR(C_RANGE,3);
|
||||
S_AXI_AWBURST <= "01";
|
||||
S_AXI_ARBURST <= "01";
|
||||
|
||||
WDATA_COUNT: PROCESS(S_ACLK,S_ARESETN)
|
||||
BEGIN
|
||||
IF(S_ARESETN='0') THEN
|
||||
WDATA_CNT<=(OTHERS=>'0');
|
||||
ELSIF(RISING_EDGE(S_ACLK)) THEN
|
||||
IF(S_AWVALID_I='1') THEN
|
||||
WDATA_CNT<=S_AXI_AWLEN_I;
|
||||
ELSIF((S_AXI_WREADY='1' AND S_AXI_WVALID_I='1')) THEN
|
||||
WDATA_CNT<=WDATA_CNT-1;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
S_AXI_WLAST_I<= '1' WHEN (WDATA_CNT =CNT_ZERO) ELSE '0';
|
||||
S_AXI_WLAST <= S_AXI_WLAST_I AFTER 50 ns;
|
||||
|
||||
|
||||
AXI_WR_DATA_GEN_INST_A:ENTITY work.DATA_GEN
|
||||
GENERIC MAP (
|
||||
DATA_GEN_WIDTH => 64,
|
||||
DOUT_WIDTH => 64 ,
|
||||
DATA_PART_CNT => 1,
|
||||
SEED => 2
|
||||
)
|
||||
PORT MAP (
|
||||
CLK =>S_ACLK,
|
||||
RST => RST_INT,
|
||||
EN => AXI_WDATA_GEN,
|
||||
DATA_OUT => AXI_WDATA
|
||||
);
|
||||
|
||||
|
||||
AWVALID_GEN: PROCESS(S_ACLK,S_ARESETN)
|
||||
BEGIN
|
||||
IF(S_ARESETN ='0') THEN
|
||||
S_AWVALID_I <= '0';
|
||||
ELSIF( RISING_EDGE(S_ACLK)) THEN
|
||||
IF(AXI_WRITE_GEN='1') THEN
|
||||
S_AWVALID_I <= '1';
|
||||
ELSIF(S_AXI_AWVALID_I='1' AND S_AXI_AWREADY='1') THEN
|
||||
S_AWVALID_I <='0';
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
WVALID_GEN: PROCESS(S_ACLK,S_ARESETN)
|
||||
BEGIN
|
||||
IF(S_ARESETN ='0') THEN
|
||||
S_WVALID_I <= '0';
|
||||
ELSIF( RISING_EDGE(S_ACLK)) THEN
|
||||
IF(AXI_WDATA_GEN='1') THEN
|
||||
S_WVALID_I <= '1';
|
||||
ELSIF(S_AXI_WVALID_I='1' AND S_AXI_WREADY='1') THEN
|
||||
S_WVALID_I <='0';
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
|
||||
S_AXI_AWADDR_INT <= (OTHERS=>'0') WHEN ( S_AWVALID_I = '0') ELSE AXI_WRITE_ADDR;
|
||||
S_AXI_AWADDR <= S_AXI_AWADDR_INT AFTER 50 ns;
|
||||
S_AXI_AWVALID_I <= S_AWVALID_I;
|
||||
S_AXI_AWVALID <= S_AXI_AWVALID_I AFTER 50 ns;
|
||||
S_AXI_WVALID_I <= S_WVALID_I;
|
||||
S_AXI_WVALID <= S_AXI_WVALID_I AFTER 50 ns;
|
||||
S_AXI_WDATA <= (OTHERS=>'0') AFTER 50 ns WHEN ( S_WVALID_I ='0') ELSE AXI_WDATA AFTER 50 ns;
|
||||
S_AXI_BREADY_I <= '1';
|
||||
S_AXI_BREADY <= S_AXI_BREADY_I;
|
||||
S_AXI_WSTRB <= (OTHERS => '1');
|
||||
|
||||
WRITE_FSM: PROCESS(CURRENT_STATE,DO_WRITE,S_AXI_BVALID,S_AXI_WREADY,S_AXI_WVALID_I,WR_COUNT,S_AXI_WLAST_I)
|
||||
BEGIN
|
||||
CASE CURRENT_STATE IS
|
||||
WHEN WAIT_ENABLE =>
|
||||
AXI_WRITE_GEN <= '0';
|
||||
IF(DO_WRITE = '1') THEN
|
||||
NEXT_STATE <= SEND_ADDR_CMD;
|
||||
ELSE
|
||||
NEXT_STATE<= WAIT_ENABLE;
|
||||
END IF;
|
||||
|
||||
WHEN SEND_ADDR_CMD =>
|
||||
AXI_WRITE_GEN <= '1';
|
||||
NEXT_STATE <= WAIT_BVALID;
|
||||
|
||||
WHEN WAIT_BVALID =>
|
||||
AXI_WRITE_GEN <= '0';
|
||||
IF(S_AXI_WREADY='1' AND S_AXI_WVALID_I='1' AND S_AXI_WLAST_I='1') THEN
|
||||
IF(WR_COUNT=WR_RD_DEEP_COUNT) THEN
|
||||
NEXT_STATE <= WAIT_ENABLE;
|
||||
ELSE
|
||||
NEXT_STATE <= SEND_ADDR_CMD;
|
||||
END IF;
|
||||
ELSE
|
||||
NEXT_STATE <= WAIT_BVALID;
|
||||
END IF;
|
||||
|
||||
WHEN OTHERS =>
|
||||
NEXT_STATE <= WAIT_ENABLE;
|
||||
AXI_WRITE_GEN <= '0';
|
||||
|
||||
END CASE;
|
||||
END PROCESS;
|
||||
|
||||
AXI_RD_ADDR_GEN: PROCESS(S_ACLK,S_ARESETN)
|
||||
BEGIN
|
||||
IF(S_ARESETN='0') THEN
|
||||
AXI_READ_ADDR <= (OTHERS=>'0');
|
||||
ELSIF(RISING_EDGE(S_ACLK)) THEN
|
||||
IF((AXI_READ_ADDR>=AXI_DEPTH ) ) THEN
|
||||
AXI_READ_ADDR <= (OTHERS=>'0');
|
||||
ELSIF(S_AXI_RREADY_I='1' AND S_AXI_RVALID='1') THEN
|
||||
AXI_READ_ADDR <= AXI_READ_ADDR + NUM_OF_BYTES;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
S_AXI_RREADY <= S_AXI_RREADY_I AFTER 50 ns;
|
||||
S_AXI_RREADY_I<= S_AXI_RREADY_OSC_I;
|
||||
|
||||
PROCESS(S_ACLK,S_ARESETN)
|
||||
BEGIN
|
||||
IF(S_ARESETN = '0') THEN
|
||||
RREADY_COUNT <=(OTHERS=>'0');
|
||||
S_AXI_RREADY_OSC_I <='0';
|
||||
ELSIF(RISING_EDGE(S_ACLK)) THEN
|
||||
S_AXI_RREADY_OSC_I <=RREADY_COUNT(0) AND RREADY_COUNT(1);
|
||||
RREADY_COUNT<= RREADY_COUNT +1;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
CHECK_RDATA <= S_AXI_RREADY_I AND S_AXI_RVALID;
|
||||
|
||||
READ_FSM: PROCESS(RD_CURRENT_STATE,DO_READ,S_AXI_RVALID,S_AXI_RREADY_I,RD_COUNT,S_AXI_RLAST)
|
||||
BEGIN
|
||||
CASE RD_CURRENT_STATE IS
|
||||
|
||||
WHEN RD_WAIT_ENABLE =>
|
||||
AXI_READ_GEN <= '0';
|
||||
IF(DO_READ = '1') THEN
|
||||
RD_NEXT_STATE <= RD_SEND_ADDR_CMD;
|
||||
ELSE
|
||||
RD_NEXT_STATE <= RD_WAIT_ENABLE;
|
||||
END IF;
|
||||
|
||||
WHEN RD_SEND_ADDR_CMD =>
|
||||
AXI_READ_GEN <= '1';
|
||||
RD_NEXT_STATE <= RD_WAIT_RVALID;
|
||||
|
||||
WHEN RD_WAIT_RVALID =>
|
||||
AXI_READ_GEN <= '0';
|
||||
IF(S_AXI_RVALID='1' AND S_AXI_RREADY_I='1' AND S_AXI_RLAST='1') THEN
|
||||
IF(RD_COUNT = WR_RD_DEEP_COUNT ) THEN
|
||||
RD_NEXT_STATE <= RD_WAIT_ENABLE;
|
||||
ELSE
|
||||
RD_NEXT_STATE <= RD_SEND_ADDR_CMD;
|
||||
END IF;
|
||||
ELSE
|
||||
RD_NEXT_STATE <= RD_WAIT_RVALID;
|
||||
END IF;
|
||||
|
||||
WHEN OTHERS =>
|
||||
AXI_READ_GEN <= '0';
|
||||
RD_NEXT_STATE <= RD_WAIT_ENABLE;
|
||||
|
||||
END CASE;
|
||||
END PROCESS;
|
||||
|
||||
S_AXI_ARADDR_INT <= (OTHERS=>'0') WHEN ( S_ARVALID_I = '0') ELSE AXI_READ_ADDR;
|
||||
S_AXI_ARADDR <= S_AXI_ARADDR_INT AFTER 50 ns;
|
||||
S_AXI_ARVALID <= S_ARVALID_I AFTER 50 ns;
|
||||
|
||||
ARVALID_GEN: PROCESS(S_ACLK,S_ARESETN)
|
||||
BEGIN
|
||||
IF(S_ARESETN ='0') THEN
|
||||
S_ARVALID_I <= '0';
|
||||
ELSIF( RISING_EDGE(S_ACLK)) THEN
|
||||
IF(AXI_READ_GEN='1') THEN
|
||||
S_ARVALID_I <= '1';
|
||||
ELSIF(S_ARVALID_I='1' AND S_AXI_ARREADY='1') THEN
|
||||
S_ARVALID_I <='0';
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
BMG_AXI_FULL_PROT_CHKER_INST: ENTITY work.BMG_AXI_FULL_PROTOCOL_CHKR
|
||||
PORT MAP (
|
||||
S_ACLK => S_ACLK,
|
||||
S_ARESETN => S_ARESETN,
|
||||
S_AXI_AWADDR => S_AXI_AWADDR_INT,
|
||||
S_AXI_AWVALID => S_AXI_AWVALID_I,
|
||||
S_AXI_AWREADY => S_AXI_AWREADY,
|
||||
S_AXI_AWID => AXI_AWID_INT,
|
||||
S_AXI_BID => S_AXI_BID,
|
||||
S_AXI_ARID => AXI_ARID_INT,
|
||||
S_AXI_RID => S_AXI_RID,
|
||||
S_AXI_AWLEN => S_AXI_AWLEN_I,
|
||||
S_AXI_WLAST => S_AXI_WLAST_I,
|
||||
S_AXI_WVALID => S_AXI_WVALID_I,
|
||||
S_AXI_WREADY => S_AXI_WREADY,
|
||||
S_AXI_BRESP => S_AXI_BRESP,
|
||||
S_AXI_BVALID => S_AXI_BVALID,
|
||||
S_AXI_BREADY => '1',
|
||||
S_AXI_ARADDR => S_AXI_ARADDR_INT,
|
||||
S_AXI_ARVALID => S_ARVALID_I,
|
||||
S_AXI_ARREADY => S_AXI_ARREADY,
|
||||
S_AXI_ARLEN => S_AXI_ARLEN_I,
|
||||
S_AXI_RRESP => S_AXI_RRESP,
|
||||
S_AXI_RVALID => S_AXI_RVALID,
|
||||
S_AXI_RREADY => S_AXI_RREADY_I,
|
||||
S_AXI_RLAST => S_AXI_RLAST,
|
||||
ERROR_FLAG => ERROR_FLAG
|
||||
);
|
||||
END ARCHITECTURE;
|
||||
@@ -1,200 +0,0 @@
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Testbench Package
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: bmg_tb_pkg.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- BMG Testbench Package files
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
PACKAGE BMG_TB_PKG IS
|
||||
|
||||
FUNCTION DIVROUNDUP (
|
||||
DATA_VALUE : INTEGER;
|
||||
DIVISOR : INTEGER)
|
||||
RETURN INTEGER;
|
||||
------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : STD_LOGIC_VECTOR;
|
||||
FALSE_CASE : STD_LOGIC_VECTOR)
|
||||
RETURN STD_LOGIC_VECTOR;
|
||||
------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : STRING;
|
||||
FALSE_CASE :STRING)
|
||||
RETURN STRING;
|
||||
------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : STD_LOGIC;
|
||||
FALSE_CASE :STD_LOGIC)
|
||||
RETURN STD_LOGIC;
|
||||
------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : INTEGER;
|
||||
FALSE_CASE : INTEGER)
|
||||
RETURN INTEGER;
|
||||
------------------------
|
||||
FUNCTION LOG2ROUNDUP (
|
||||
DATA_VALUE : INTEGER)
|
||||
RETURN INTEGER;
|
||||
|
||||
END BMG_TB_PKG;
|
||||
|
||||
PACKAGE BODY BMG_TB_PKG IS
|
||||
|
||||
FUNCTION DIVROUNDUP (
|
||||
DATA_VALUE : INTEGER;
|
||||
DIVISOR : INTEGER)
|
||||
RETURN INTEGER IS
|
||||
VARIABLE DIV : INTEGER;
|
||||
BEGIN
|
||||
DIV := DATA_VALUE/DIVISOR;
|
||||
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
|
||||
DIV := DIV+1;
|
||||
END IF;
|
||||
RETURN DIV;
|
||||
END DIVROUNDUP;
|
||||
---------------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : STD_LOGIC_VECTOR;
|
||||
FALSE_CASE : STD_LOGIC_VECTOR)
|
||||
RETURN STD_LOGIC_VECTOR IS
|
||||
BEGIN
|
||||
IF NOT CONDITION THEN
|
||||
RETURN FALSE_CASE;
|
||||
ELSE
|
||||
RETURN TRUE_CASE;
|
||||
END IF;
|
||||
END IF_THEN_ELSE;
|
||||
---------------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : STD_LOGIC;
|
||||
FALSE_CASE : STD_LOGIC)
|
||||
RETURN STD_LOGIC IS
|
||||
BEGIN
|
||||
IF NOT CONDITION THEN
|
||||
RETURN FALSE_CASE;
|
||||
ELSE
|
||||
RETURN TRUE_CASE;
|
||||
END IF;
|
||||
END IF_THEN_ELSE;
|
||||
---------------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : INTEGER;
|
||||
FALSE_CASE : INTEGER)
|
||||
RETURN INTEGER IS
|
||||
VARIABLE RETVAL : INTEGER := 0;
|
||||
BEGIN
|
||||
IF CONDITION=FALSE THEN
|
||||
RETVAL:=FALSE_CASE;
|
||||
ELSE
|
||||
RETVAL:=TRUE_CASE;
|
||||
END IF;
|
||||
RETURN RETVAL;
|
||||
END IF_THEN_ELSE;
|
||||
---------------------------------
|
||||
FUNCTION IF_THEN_ELSE (
|
||||
CONDITION : BOOLEAN;
|
||||
TRUE_CASE : STRING;
|
||||
FALSE_CASE : STRING)
|
||||
RETURN STRING IS
|
||||
BEGIN
|
||||
IF NOT CONDITION THEN
|
||||
RETURN FALSE_CASE;
|
||||
ELSE
|
||||
RETURN TRUE_CASE;
|
||||
END IF;
|
||||
END IF_THEN_ELSE;
|
||||
-------------------------------
|
||||
FUNCTION LOG2ROUNDUP (
|
||||
DATA_VALUE : INTEGER)
|
||||
RETURN INTEGER IS
|
||||
VARIABLE WIDTH : INTEGER := 0;
|
||||
VARIABLE CNT : INTEGER := 1;
|
||||
BEGIN
|
||||
IF (DATA_VALUE <= 1) THEN
|
||||
WIDTH := 1;
|
||||
ELSE
|
||||
WHILE (CNT < DATA_VALUE) LOOP
|
||||
WIDTH := WIDTH + 1;
|
||||
CNT := CNT *2;
|
||||
END LOOP;
|
||||
END IF;
|
||||
RETURN WIDTH;
|
||||
END LOG2ROUNDUP;
|
||||
|
||||
END BMG_TB_PKG;
|
||||
@@ -1,140 +0,0 @@
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Data Generator
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: data_gen.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Data Generator
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.BMG_TB_PKG.ALL;
|
||||
|
||||
ENTITY DATA_GEN IS
|
||||
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
|
||||
DOUT_WIDTH : INTEGER := 32;
|
||||
DATA_PART_CNT : INTEGER := 1;
|
||||
SEED : INTEGER := 2
|
||||
);
|
||||
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RST : IN STD_LOGIC;
|
||||
EN : IN STD_LOGIC;
|
||||
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
|
||||
);
|
||||
END DATA_GEN;
|
||||
|
||||
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
|
||||
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
|
||||
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
|
||||
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
|
||||
SIGNAL LOCAL_CNT : INTEGER :=1;
|
||||
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
|
||||
BEGIN
|
||||
|
||||
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
|
||||
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
|
||||
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
|
||||
|
||||
PROCESS(CLK)
|
||||
BEGIN
|
||||
IF(RISING_EDGE (CLK)) THEN
|
||||
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
|
||||
LOCAL_CNT <=1;
|
||||
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
|
||||
IF(LOCAL_CNT = 1) THEN
|
||||
LOCAL_CNT <= LOCAL_CNT+1;
|
||||
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
|
||||
LOCAL_CNT <= LOCAL_CNT+1;
|
||||
ELSE
|
||||
LOCAL_CNT <= 1;
|
||||
END IF;
|
||||
ELSE
|
||||
LOCAL_CNT <= 1;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
|
||||
RAND_GEN_INST:ENTITY work.RANDOM
|
||||
GENERIC MAP(
|
||||
WIDTH => 8,
|
||||
SEED => (SEED+N)
|
||||
)
|
||||
PORT MAP(
|
||||
CLK => CLK,
|
||||
RST => RST,
|
||||
EN => DATA_GEN_I,
|
||||
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
|
||||
);
|
||||
END GENERATE RAND_GEN;
|
||||
|
||||
END ARCHITECTURE;
|
||||
|
||||
@@ -1,89 +0,0 @@
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
wcfg new
|
||||
isim set radix hex
|
||||
wave add /axi4_bram_1kx64_tb/status
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_ACLK
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWADDR
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWVALID
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWREADY
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWLEN
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWSIZE
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWBURST
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWID
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_WDATA
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_WSTRB
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_WVALID
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_WREADY
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_WLAST
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_BID
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_BRESP
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_BVALID
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_BREADY
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARID
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARADDR
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARLEN
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARSIZE
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARBURST
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARVALID
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARREADY
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_RID
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_RDATA
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_RRESP
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_RLAST
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_RVALID
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_RREADY
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_ARESETN
|
||||
run all
|
||||
quit
|
||||
@@ -1,71 +0,0 @@
|
||||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
echo "Compiling Core Verilog UNISIM/Behavioral model"
|
||||
vlogcomp -work work ../../../axi4_bram_1kx64.v
|
||||
vhpcomp -work work ../../example_design/axi4_bram_1kx64_exdes.vhd
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
|
||||
vhpcomp -work work ../bmg_tb_pkg.vhd
|
||||
vhpcomp -work work ../random.vhd
|
||||
vhpcomp -work work ../data_gen.vhd
|
||||
vhpcomp -work work ../addr_gen.vhd
|
||||
vhpcomp -work work ../bmg_axi_protocol_chkr.vhd
|
||||
vhpcomp -work work ../axi_checker.vhd
|
||||
vhpcomp -work work ../bmg_stim_gen.vhd
|
||||
vhpcomp -work work ../axi4_bram_1kx64_synth.vhd
|
||||
vhpcomp -work work ../axi4_bram_1kx64_tb.vhd
|
||||
|
||||
|
||||
vlogcomp -work work $XILINX/verilog/src/glbl.v
|
||||
fuse work.axi4_bram_1kx64_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi4_bram_1kx64_tb.exe
|
||||
|
||||
./axi4_bram_1kx64_tb.exe -gui -tclbatch simcmds.tcl
|
||||
@@ -1,3 +0,0 @@
|
||||
#--------------------------------------------------------------------------------
|
||||
|
||||
vsim -c -do simulate_mti.do
|
||||
@@ -1,77 +0,0 @@
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#--------------------------------------------------------------------------------
|
||||
vlib work
|
||||
vmap work work
|
||||
|
||||
echo "Compiling Core Verilog UNISIM/Behavioral model"
|
||||
vlog -work work ../../../axi4_bram_1kx64.v
|
||||
vcom -work work ../../example_design/axi4_bram_1kx64_exdes.vhd
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
|
||||
vcom -work work ../bmg_tb_pkg.vhd
|
||||
vcom -work work ../random.vhd
|
||||
vcom -work work ../data_gen.vhd
|
||||
vcom -work work ../addr_gen.vhd
|
||||
vcom -work work ../bmg_axi_protocol_chkr.vhd
|
||||
vcom -work work ../axi_checker.vhd
|
||||
vcom -work work ../bmg_stim_gen.vhd
|
||||
vcom -work work ../axi4_bram_1kx64_synth.vhd
|
||||
vcom -work work ../axi4_bram_1kx64_tb.vhd
|
||||
|
||||
|
||||
vlog -work work $env(XILINX)/verilog/src/glbl.v
|
||||
vsim -novopt -t ps -L XilinxCoreLib_ver -L unisims_ver glbl work.axi4_bram_1kx64_tb
|
||||
|
||||
#Disabled waveform to save the disk space
|
||||
add log -r /*
|
||||
#Ignore integer warnings at time 0
|
||||
set StdArithNoWarnings 1
|
||||
run 0
|
||||
set StdArithNoWarnings 0
|
||||
|
||||
run -all
|
||||
@@ -1,3 +0,0 @@
|
||||
#--------------------------------------------------------------------------------
|
||||
|
||||
vsim -c -do simulate_mti.do
|
||||
@@ -1,72 +0,0 @@
|
||||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
mkdir work
|
||||
echo "Compiling Core Verilog UNISIM/Behavioral model"
|
||||
ncvlog -work work ../../../axi4_bram_1kx64.v
|
||||
ncvhdl -v93 -work work ../../example_design/axi4_bram_1kx64_exdes.vhd
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
|
||||
ncvhdl -v93 -work work ../bmg_tb_pkg.vhd
|
||||
ncvhdl -v93 -work work ../random.vhd
|
||||
ncvhdl -v93 -work work ../data_gen.vhd
|
||||
ncvhdl -v93 -work work ../addr_gen.vhd
|
||||
ncvhdl -v93 -work work ../bmg_axi_protocol_chkr.vhd
|
||||
ncvhdl -v93 -work work ../axi_checker.vhd
|
||||
ncvhdl -v93 -work work ../bmg_stim_gen.vhd
|
||||
ncvhdl -v93 -work work ../axi4_bram_1kx64_synth.vhd
|
||||
ncvhdl -v93 -work work ../axi4_bram_1kx64_tb.vhd
|
||||
|
||||
echo "Elaborating Design"
|
||||
ncvlog -work work $XILINX/verilog/src/glbl.v
|
||||
ncelab -access +rwc glbl work.axi4_bram_1kx64_tb
|
||||
|
||||
echo "Simulating Design"
|
||||
ncsim -gui -input @"simvision -input wave_ncsim.sv" work.axi4_bram_1kx64_tb
|
||||
@@ -1,71 +0,0 @@
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#--------------------------------------------------------------------------------
|
||||
#!/bin/sh
|
||||
rm -rf simv* csrc DVEfiles AN.DB
|
||||
|
||||
echo "Compiling Core Verilog UNISIM/Behavioral model"
|
||||
vlogan +v2k ../../../axi4_bram_1kx64.v
|
||||
vhdlan ../../example_design/axi4_bram_1kx64_exdes.vhd
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
vhdlan ../bmg_tb_pkg.vhd
|
||||
vhdlan ../random.vhd
|
||||
vhdlan ../data_gen.vhd
|
||||
vhdlan ../addr_gen.vhd
|
||||
vhdlan ../bmg_axi_protocol_chkr.vhd
|
||||
vhdlan ../axi_checker.vhd
|
||||
vhdlan ../bmg_stim_gen.vhd
|
||||
vhdlan ../axi4_bram_1kx64_synth.vhd
|
||||
vhdlan ../axi4_bram_1kx64_tb.vhd
|
||||
|
||||
echo "Elaborating Design"
|
||||
vlogan +v2k $XILINX/verilog/src/glbl.v
|
||||
vcs +vcs+lic+wait -debug axi4_bram_1kx64_tb glbl
|
||||
|
||||
echo "Simulating Design"
|
||||
./simv -ucli -i ucli_commands.key
|
||||
dve -session vcs_session.tcl
|
||||
@@ -1,4 +0,0 @@
|
||||
dump -file bmg_vcs.vpd -type VPD
|
||||
dump -add axi4_bram_1kx64_tb
|
||||
run
|
||||
quit
|
||||
@@ -1,109 +0,0 @@
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#--------------------------------------------------------------------------------
|
||||
#--
|
||||
#-- BMG core Demo Testbench
|
||||
#--
|
||||
#--------------------------------------------------------------------------------
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
# Filename: vcs_session.tcl
|
||||
#
|
||||
# Description:
|
||||
# This is the VCS wave form file.
|
||||
#
|
||||
#--------------------------------------------------------------------------------
|
||||
if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } {
|
||||
gui_open_db -design V1 -file bmg_vcs.vpd -nosource
|
||||
}
|
||||
gui_set_precision 1ps
|
||||
gui_set_time_units 1ps
|
||||
|
||||
gui_open_window Wave
|
||||
gui_sg_create axi4_bram_1kx64_Group
|
||||
gui_list_add_group -id Wave.1 {axi4_bram_1kx64_Group}
|
||||
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/status
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_ACLK
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWADDR
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWVALID
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWREADY
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWLEN
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWSIZE
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWBURST
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWID
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WDATA
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WSTRB
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WVALID
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WREADY
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WLAST
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BID
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BRESP
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BVALID
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BREADY
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARID
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARADDR
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARLEN
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARSIZE
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARBURST
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARVALID
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARREADY
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RID
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RDATA
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RRESP
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RLAST
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RVALID
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RREADY
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_ARESETN
|
||||
|
||||
gui_zoom -window Wave.1 -full
|
||||
@@ -1,62 +0,0 @@
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/status
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_ACLK
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWADDR
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWVALID
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWREADY
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWLEN
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWSIZE
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWBURST
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWID
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WDATA
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WSTRB
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WVALID
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WREADY
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WLAST
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BID
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BRESP
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BVALID
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BREADY
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARID
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARADDR
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARLEN
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARSIZE
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARBURST
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARVALID
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARREADY
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RID
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RDATA
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RRESP
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RLAST
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RVALID
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RREADY
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_ARESETN
|
||||
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
|
||||
configure wave -namecolwidth 197
|
||||
configure wave -valuecolwidth 106
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ps
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {9464063 ps}
|
||||
@@ -1,47 +0,0 @@
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
window new WaveWindow -name "Waves for BMG Example Design"
|
||||
waveform using "Waves for BMG Example Design"
|
||||
|
||||
waveform add -signals /axi4_bram_1kx64_tb/status
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_ACLK
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWADDR
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWVALID
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWREADY
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWLEN
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWSIZE
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWBURST
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWID
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WDATA
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WSTRB
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WVALID
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WREADY
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WLAST
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BID
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BRESP
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BVALID
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BREADY
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARID
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARADDR
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARLEN
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARSIZE
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARBURST
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARVALID
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARREADY
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RID
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RDATA
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RRESP
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RLAST
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RVALID
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RREADY
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_ARESETN
|
||||
|
||||
console submit -using simulator -wait no "run"
|
||||
@@ -1,112 +0,0 @@
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- BLK MEM GEN v7_3 Core - Random Number Generator
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: random.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Random Generator
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Author: IP Solutions Division
|
||||
--
|
||||
-- History: Sep 12, 2011 - First Release
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.STD_LOGIC_ARITH.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
|
||||
ENTITY RANDOM IS
|
||||
GENERIC ( WIDTH : INTEGER := 32;
|
||||
SEED : INTEGER :=2
|
||||
);
|
||||
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RST : IN STD_LOGIC;
|
||||
EN : IN STD_LOGIC;
|
||||
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
|
||||
);
|
||||
END RANDOM;
|
||||
|
||||
ARCHITECTURE BEHAVIORAL OF RANDOM IS
|
||||
BEGIN
|
||||
PROCESS(CLK)
|
||||
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
|
||||
VARIABLE TEMP : STD_LOGIC := '0';
|
||||
BEGIN
|
||||
IF(RISING_EDGE(CLK)) THEN
|
||||
IF(RST='1') THEN
|
||||
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
|
||||
ELSE
|
||||
IF(EN = '1') THEN
|
||||
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
|
||||
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
|
||||
RAND_TEMP(0) := TEMP;
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
RANDOM_NUM <= RAND_TEMP;
|
||||
END PROCESS;
|
||||
END ARCHITECTURE;
|
||||
@@ -1,89 +0,0 @@
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
wcfg new
|
||||
isim set radix hex
|
||||
wave add /axi4_bram_1kx64_tb/status
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_ACLK
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWADDR
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWVALID
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWREADY
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWLEN
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWSIZE
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWBURST
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_AWID
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_WDATA
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_WSTRB
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_WVALID
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_WREADY
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_WLAST
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_BID
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_BRESP
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_BVALID
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_BREADY
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARID
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARADDR
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARLEN
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARSIZE
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARBURST
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARVALID
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_ARREADY
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_RID
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_RDATA
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_RRESP
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_RLAST
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_RVALID
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_AXI_RREADY
|
||||
wave add /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/BMG_PORT/S_ARESETN
|
||||
run all
|
||||
quit
|
||||
@@ -1,67 +0,0 @@
|
||||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
vlogcomp -work work ../../implement/results/routed.v
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
|
||||
vhpcomp -work work ../bmg_tb_pkg.vhd
|
||||
vhpcomp -work work ../random.vhd
|
||||
vhpcomp -work work ../data_gen.vhd
|
||||
vhpcomp -work work ../addr_gen.vhd
|
||||
vhpcomp -work work ../bmg_axi_protocol_chkr.vhd
|
||||
vhpcomp -work work ../axi_checker.vhd
|
||||
vhpcomp -work work ../bmg_stim_gen.vhd
|
||||
vhpcomp -work work ../axi4_bram_1kx64_synth.vhd
|
||||
vhpcomp -work work ../axi4_bram_1kx64_tb.vhd
|
||||
|
||||
fuse -L simprims_ver work.axi4_bram_1kx64_tb work.glbl -o axi4_bram_1kx64_tb.exe
|
||||
|
||||
./axi4_bram_1kx64_tb.exe -sdftyp /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port=../../implement/results/routed.sdf -gui -tclbatch simcmds.tcl
|
||||
@@ -1,3 +0,0 @@
|
||||
#--------------------------------------------------------------------------------
|
||||
|
||||
vsim -c -do simulate_mti.do
|
||||
@@ -1,76 +0,0 @@
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
set work work
|
||||
#--------------------------------------------------------------------------------
|
||||
|
||||
vlib work
|
||||
vmap work work
|
||||
|
||||
echo "Compiling Core Verilog UNISIM/Behavioral model"
|
||||
vlog -work work ../../implement/results/routed.v
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
|
||||
vcom -work work ../bmg_tb_pkg.vhd
|
||||
vcom -work work ../random.vhd
|
||||
vcom -work work ../data_gen.vhd
|
||||
vcom -work work ../addr_gen.vhd
|
||||
vcom -work work ../bmg_axi_protocol_chkr.vhd
|
||||
vcom -work work ../axi_checker.vhd
|
||||
vcom -work work ../bmg_stim_gen.vhd
|
||||
vcom -work work ../axi4_bram_1kx64_synth.vhd
|
||||
vcom -work work ../axi4_bram_1kx64_tb.vhd
|
||||
|
||||
vsim -novopt -t ps -L simprims_ver +transport_int_delays -sdftyp /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port=../../implement/results/routed.sdf $work.axi4_bram_1kx64_tb $work.glbl -novopt
|
||||
|
||||
#Disabled waveform to save the disk space
|
||||
add log -r /*
|
||||
#Ignore integer warnings at time 0
|
||||
set StdArithNoWarnings 1
|
||||
run 0
|
||||
set StdArithNoWarnings 0
|
||||
|
||||
run -all
|
||||
@@ -1,3 +0,0 @@
|
||||
#--------------------------------------------------------------------------------
|
||||
|
||||
vsim -c -do simulate_mti.do
|
||||
@@ -1,79 +0,0 @@
|
||||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
set work work
|
||||
#--------------------------------------------------------------------------------
|
||||
mkdir work
|
||||
|
||||
|
||||
ncvlog -work work ../../implement/results/routed.v
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
|
||||
ncvhdl -v93 -work work ../bmg_tb_pkg.vhd
|
||||
ncvhdl -v93 -work work ../random.vhd
|
||||
ncvhdl -v93 -work work ../data_gen.vhd
|
||||
ncvhdl -v93 -work work ../addr_gen.vhd
|
||||
ncvhdl -v93 -work work ../bmg_axi_protocol_chkr.vhd
|
||||
ncvhdl -v93 -work work ../axi_checker.vhd
|
||||
ncvhdl -v93 -work work ../bmg_stim_gen.vhd
|
||||
ncvhdl -v93 -work work ../axi4_bram_1kx64_synth.vhd
|
||||
ncvhdl -v93 -work work ../axi4_bram_1kx64_tb.vhd
|
||||
|
||||
echo "Compiling SDF file"
|
||||
ncsdfc ../../implement/results/routed.sdf -output ./routed.sdf.X
|
||||
|
||||
echo "Generating SDF command file"
|
||||
echo 'COMPILED_SDF_FILE = "routed.sdf.X",' > sdf.cmd
|
||||
echo 'SCOPE = :axi4_bram_1kx64_synth_inst:BMG_PORT,' >> sdf.cmd
|
||||
echo 'MTM_CONTROL = "MAXIMUM";' >> sdf.cmd
|
||||
|
||||
|
||||
echo "Elaborating Design"
|
||||
ncelab -access +rwc glbl -sdf_cmd_file sdf.cmd $work.axi4_bram_1kx64_tb
|
||||
|
||||
echo "Simulating Design"
|
||||
ncsim -gui -input @"simvision -input wave_ncsim.sv" $work.axi4_bram_1kx64_tb
|
||||
@@ -1,71 +0,0 @@
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#--------------------------------------------------------------------------------
|
||||
#!/bin/sh
|
||||
|
||||
rm -rf simv* csrc DVEfiles AN.DB
|
||||
|
||||
echo "Compiling Core Verilog UNISIM/Behavioral model"
|
||||
vlogan +v2k ../../implement/results/routed.v
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
vhdlan ../bmg_tb_pkg.vhd
|
||||
vhdlan ../random.vhd
|
||||
vhdlan ../data_gen.vhd
|
||||
vhdlan ../addr_gen.vhd
|
||||
vhdlan ../bmg_axi_protocol_chkr.vhd
|
||||
vhdlan ../axi_checker.vhd
|
||||
vhdlan ../bmg_stim_gen.vhd
|
||||
vhdlan ../axi4_bram_1kx64_synth.vhd
|
||||
vhdlan ../axi4_bram_1kx64_tb.vhd
|
||||
|
||||
|
||||
echo "Elaborating Design"
|
||||
vcs +neg_tchk +vcs+lic+wait -debug axi4_bram_1kx64_tb glbl
|
||||
|
||||
echo "Simulating Design"
|
||||
./simv -ucli -i ucli_commands.key
|
||||
dve -session vcs_session.tcl
|
||||
@@ -1,4 +0,0 @@
|
||||
dump -file bmg_vcs.vpd -type VPD
|
||||
dump -add axi4_bram_1kx64_tb
|
||||
run
|
||||
quit
|
||||
@@ -1,109 +0,0 @@
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#--------------------------------------------------------------------------------
|
||||
#--
|
||||
#-- BMG Generator v8.4 Core Demo Testbench
|
||||
#--
|
||||
#--------------------------------------------------------------------------------
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
# Filename: vcs_session.tcl
|
||||
#
|
||||
# Description:
|
||||
# This is the VCS wave form file.
|
||||
#
|
||||
#--------------------------------------------------------------------------------
|
||||
|
||||
if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } {
|
||||
gui_open_db -design V1 -file bmg_vcs.vpd -nosource
|
||||
}
|
||||
gui_set_precision 1ps
|
||||
gui_set_time_units 1ps
|
||||
|
||||
gui_open_window Wave
|
||||
gui_sg_create axi4_bram_1kx64_Group
|
||||
gui_list_add_group -id Wave.1 {axi4_bram_1kx64_Group}
|
||||
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/status
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_ACLK
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWADDR
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWVALID
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWREADY
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWLEN
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWSIZE
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWBURST
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWID
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WDATA
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WSTRB
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WVALID
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WREADY
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WLAST
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BID
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BRESP
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BVALID
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BREADY
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARID
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARADDR
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARLEN
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARSIZE
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARBURST
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARVALID
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARREADY
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RID
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RDATA
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RRESP
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RLAST
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RVALID
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RREADY
|
||||
gui_sg_addsignal -group axi4_bram_1kx64_Group /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_ARESETN
|
||||
|
||||
gui_zoom -window Wave.1 -full
|
||||
@@ -1,62 +0,0 @@
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
|
||||
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/status
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_ACLK
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWADDR
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWVALID
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWREADY
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWLEN
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWSIZE
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWBURST
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWID
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WDATA
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WSTRB
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WVALID
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WREADY
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WLAST
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BID
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BRESP
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BVALID
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BREADY
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARID
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARADDR
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARLEN
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARSIZE
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARBURST
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARVALID
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARREADY
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RID
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RDATA
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RRESP
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RLAST
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RVALID
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RREADY
|
||||
add wave -noupdate /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_ARESETN
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ps
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {9464063 ps}
|
||||
@@ -1,46 +0,0 @@
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
window new WaveWindow -name "Waves for BMG Example Design"
|
||||
waveform using "Waves for BMG Example Design"
|
||||
|
||||
|
||||
waveform add -signals /axi4_bram_1kx64_tb/status
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_ACLK
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWADDR
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWVALID
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWREADY
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWLEN
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWSIZE
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWBURST
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_AWID
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WDATA
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WSTRB
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WVALID
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WREADY
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_WLAST
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BID
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BRESP
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BVALID
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_BREADY
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARID
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARADDR
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARLEN
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARSIZE
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARBURST
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARVALID
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_ARREADY
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RID
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RDATA
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RRESP
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RLAST
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RVALID
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_AXI_RREADY
|
||||
waveform add -signals /axi4_bram_1kx64_tb/axi4_bram_1kx64_synth_inst/bmg_port/S_ARESETN
|
||||
console submit -using simulator -wait no "run"
|
||||
@@ -1,56 +0,0 @@
|
||||
# Output products list for <axi4_bram_1kx64>
|
||||
axi4_bram_1kx64/blk_mem_gen_v7_3_readme.txt
|
||||
axi4_bram_1kx64/doc/blk_mem_gen_v7_3_vinfo.html
|
||||
axi4_bram_1kx64/doc/pg058-blk-mem-gen.pdf
|
||||
axi4_bram_1kx64/example_design/axi4_bram_1kx64_exdes.ucf
|
||||
axi4_bram_1kx64/example_design/axi4_bram_1kx64_exdes.vhd
|
||||
axi4_bram_1kx64/example_design/axi4_bram_1kx64_exdes.xdc
|
||||
axi4_bram_1kx64/example_design/axi4_bram_1kx64_prod.vhd
|
||||
axi4_bram_1kx64/implement/implement.bat
|
||||
axi4_bram_1kx64/implement/implement.sh
|
||||
axi4_bram_1kx64/implement/planAhead_ise.bat
|
||||
axi4_bram_1kx64/implement/planAhead_ise.sh
|
||||
axi4_bram_1kx64/implement/planAhead_ise.tcl
|
||||
axi4_bram_1kx64/implement/xst.prj
|
||||
axi4_bram_1kx64/implement/xst.scr
|
||||
axi4_bram_1kx64/simulation/addr_gen.vhd
|
||||
axi4_bram_1kx64/simulation/axi4_bram_1kx64_synth.vhd
|
||||
axi4_bram_1kx64/simulation/axi4_bram_1kx64_tb.vhd
|
||||
axi4_bram_1kx64/simulation/axi_checker.vhd
|
||||
axi4_bram_1kx64/simulation/bmg_axi_protocol_chkr.vhd
|
||||
axi4_bram_1kx64/simulation/bmg_stim_gen.vhd
|
||||
axi4_bram_1kx64/simulation/bmg_tb_pkg.vhd
|
||||
axi4_bram_1kx64/simulation/data_gen.vhd
|
||||
axi4_bram_1kx64/simulation/functional/simcmds.tcl
|
||||
axi4_bram_1kx64/simulation/functional/simulate_isim.sh
|
||||
axi4_bram_1kx64/simulation/functional/simulate_mti.bat
|
||||
axi4_bram_1kx64/simulation/functional/simulate_mti.do
|
||||
axi4_bram_1kx64/simulation/functional/simulate_mti.sh
|
||||
axi4_bram_1kx64/simulation/functional/simulate_ncsim.sh
|
||||
axi4_bram_1kx64/simulation/functional/simulate_vcs.sh
|
||||
axi4_bram_1kx64/simulation/functional/ucli_commands.key
|
||||
axi4_bram_1kx64/simulation/functional/vcs_session.tcl
|
||||
axi4_bram_1kx64/simulation/functional/wave_mti.do
|
||||
axi4_bram_1kx64/simulation/functional/wave_ncsim.sv
|
||||
axi4_bram_1kx64/simulation/random.vhd
|
||||
axi4_bram_1kx64/simulation/timing/simcmds.tcl
|
||||
axi4_bram_1kx64/simulation/timing/simulate_isim.sh
|
||||
axi4_bram_1kx64/simulation/timing/simulate_mti.bat
|
||||
axi4_bram_1kx64/simulation/timing/simulate_mti.do
|
||||
axi4_bram_1kx64/simulation/timing/simulate_mti.sh
|
||||
axi4_bram_1kx64/simulation/timing/simulate_ncsim.sh
|
||||
axi4_bram_1kx64/simulation/timing/simulate_vcs.sh
|
||||
axi4_bram_1kx64/simulation/timing/ucli_commands.key
|
||||
axi4_bram_1kx64/simulation/timing/vcs_session.tcl
|
||||
axi4_bram_1kx64/simulation/timing/wave_mti.do
|
||||
axi4_bram_1kx64/simulation/timing/wave_ncsim.sv
|
||||
axi4_bram_1kx64.asy
|
||||
axi4_bram_1kx64.gise
|
||||
axi4_bram_1kx64.ngc
|
||||
axi4_bram_1kx64.v
|
||||
axi4_bram_1kx64.veo
|
||||
axi4_bram_1kx64.xco
|
||||
axi4_bram_1kx64.xise
|
||||
axi4_bram_1kx64_flist.txt
|
||||
axi4_bram_1kx64_xmdf.tcl
|
||||
summary.log
|
||||
@@ -1,251 +0,0 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide axi4_bram_1kx64_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::axi4_bram_1kx64_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::axi4_bram_1kx64_xmdf::xmdfInit { instance } {
|
||||
# Variable containing name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name axi4_bram_1kx64
|
||||
}
|
||||
# ::axi4_bram_1kx64_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::axi4_bram_1kx64_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/blk_mem_gen_v7_3_readme.txt
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/doc/blk_mem_gen_v7_3_vinfo.html
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/doc/pg058-blk-mem-gen.pdf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/example_design/axi4_bram_1kx64_exdes.ucf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/example_design/axi4_bram_1kx64_exdes.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/example_design/axi4_bram_1kx64_exdes.xdc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/example_design/axi4_bram_1kx64_prod.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/implement/implement.bat
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/implement/implement.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/implement/planAhead_ise.bat
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/implement/planAhead_ise.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/implement/planAhead_ise.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/implement/xst.prj
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/implement/xst.scr
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/addr_gen.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/axi4_bram_1kx64_synth.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/axi4_bram_1kx64_tb.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/axi_checker.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/bmg_axi_protocol_chkr.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/bmg_stim_gen.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/bmg_tb_pkg.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/data_gen.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/functional/simcmds.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/functional/simulate_isim.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/functional/simulate_mti.bat
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/functional/simulate_mti.do
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/functional/simulate_mti.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/functional/simulate_ncsim.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/functional/simulate_vcs.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/functional/ucli_commands.key
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/functional/vcs_session.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/functional/wave_mti.do
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/functional/wave_ncsim.sv
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/random.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/timing/simcmds.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/timing/simulate_isim.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/timing/simulate_mti.bat
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/timing/simulate_mti.do
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/timing/simulate_mti.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/timing/simulate_ncsim.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/timing/simulate_vcs.sh
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/timing/ucli_commands.key
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/timing/vcs_session.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/timing/wave_mti.do
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64/simulation/timing/wave_ncsim.sv
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64.asy
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64.ngc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64.veo
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path axi4_bram_1kx64_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path summary.log
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module axi4_bram_1kx64
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
@@ -1,65 +0,0 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 axi64_4k_2clk_fifo
|
||||
RECTANGLE Normal 32 32 800 4064
|
||||
LINE Normal 832 720 800 720
|
||||
PIN 832 720 RIGHT 36
|
||||
PINATTR PinName m_aclk
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 688 32 688
|
||||
PIN 0 688 LEFT 36
|
||||
PINATTR PinName s_aclk
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 720 32 720
|
||||
PIN 0 720 LEFT 36
|
||||
PINATTR PinName s_aresetn
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 832 784 800 784
|
||||
PIN 832 784 RIGHT 36
|
||||
PINATTR PinName m_axis_tvalid
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 832 816 800 816
|
||||
PIN 832 816 RIGHT 36
|
||||
PINATTR PinName m_axis_tready
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 832 848 800 848
|
||||
PIN 832 848 RIGHT 36
|
||||
PINATTR PinName m_axis_tdata[63:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 832 944 800 944
|
||||
PIN 832 944 RIGHT 36
|
||||
PINATTR PinName m_axis_tlast
|
||||
PINATTR Polarity OUT
|
||||
LINE Wide 832 1040 800 1040
|
||||
PIN 832 1040 RIGHT 36
|
||||
PINATTR PinName m_axis_tuser[3:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 0 784 32 784
|
||||
PIN 0 784 LEFT 36
|
||||
PINATTR PinName s_axis_tvalid
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 816 32 816
|
||||
PIN 0 816 LEFT 36
|
||||
PINATTR PinName s_axis_tready
|
||||
PINATTR Polarity OUT
|
||||
LINE Wide 0 848 32 848
|
||||
PIN 0 848 LEFT 36
|
||||
PINATTR PinName s_axis_tdata[63:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 944 32 944
|
||||
PIN 0 944 LEFT 36
|
||||
PINATTR PinName s_axis_tlast
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 1040 32 1040
|
||||
PIN 0 1040 LEFT 36
|
||||
PINATTR PinName s_axis_tuser[3:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 1200 32 1200
|
||||
PIN 0 1200 LEFT 36
|
||||
PINATTR PinName axis_wr_data_count[9:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Wide 832 1200 800 1200
|
||||
PIN 832 1200 RIGHT 36
|
||||
PINATTR PinName axis_rd_data_count[9:0]
|
||||
PINATTR Polarity OUT
|
||||
|
||||
@@ -1,31 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="axi64_4k_2clk_fifo.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="axi64_4k_2clk_fifo.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VEO" xil_pn:name="axi64_4k_2clk_fifo.veo" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
|
||||
</generated_project>
|
||||
File diff suppressed because one or more lines are too long
@@ -1,499 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* This file is owned and controlled by Xilinx and must be used solely *
|
||||
* for design, simulation, implementation and creation of design files *
|
||||
* limited to Xilinx devices or technologies. Use with non-Xilinx *
|
||||
* devices or technologies is expressly prohibited and immediately *
|
||||
* terminates your license. *
|
||||
* *
|
||||
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
|
||||
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
|
||||
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
|
||||
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
|
||||
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
|
||||
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
|
||||
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
|
||||
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
|
||||
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
|
||||
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
|
||||
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
|
||||
* PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* Xilinx products are not intended for use in life support appliances, *
|
||||
* devices, or systems. Use in such applications are expressly *
|
||||
* prohibited. *
|
||||
* *
|
||||
* (c) Copyright 1995-2014 Xilinx, Inc. *
|
||||
* All rights reserved. *
|
||||
*******************************************************************************/
|
||||
// You must compile the wrapper file axi64_4k_2clk_fifo.v when simulating
|
||||
// the core, axi64_4k_2clk_fifo. When compiling the wrapper file, be sure to
|
||||
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
||||
// instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
// The synthesis directives "translate_off/translate_on" specified below are
|
||||
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
|
||||
// tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module axi64_4k_2clk_fifo(
|
||||
m_aclk,
|
||||
s_aclk,
|
||||
s_aresetn,
|
||||
s_axis_tvalid,
|
||||
s_axis_tready,
|
||||
s_axis_tdata,
|
||||
s_axis_tlast,
|
||||
s_axis_tuser,
|
||||
m_axis_tvalid,
|
||||
m_axis_tready,
|
||||
m_axis_tdata,
|
||||
m_axis_tlast,
|
||||
m_axis_tuser,
|
||||
axis_wr_data_count,
|
||||
axis_rd_data_count
|
||||
);
|
||||
|
||||
input m_aclk;
|
||||
input s_aclk;
|
||||
input s_aresetn;
|
||||
input s_axis_tvalid;
|
||||
output s_axis_tready;
|
||||
input [63 : 0] s_axis_tdata;
|
||||
input s_axis_tlast;
|
||||
input [3 : 0] s_axis_tuser;
|
||||
output m_axis_tvalid;
|
||||
input m_axis_tready;
|
||||
output [63 : 0] m_axis_tdata;
|
||||
output m_axis_tlast;
|
||||
output [3 : 0] m_axis_tuser;
|
||||
output [9 : 0] axis_wr_data_count;
|
||||
output [9 : 0] axis_rd_data_count;
|
||||
|
||||
// synthesis translate_off
|
||||
|
||||
FIFO_GENERATOR_V9_3 #(
|
||||
.C_ADD_NGC_CONSTRAINT(0),
|
||||
.C_APPLICATION_TYPE_AXIS(0),
|
||||
.C_APPLICATION_TYPE_RACH(0),
|
||||
.C_APPLICATION_TYPE_RDCH(0),
|
||||
.C_APPLICATION_TYPE_WACH(0),
|
||||
.C_APPLICATION_TYPE_WDCH(0),
|
||||
.C_APPLICATION_TYPE_WRCH(0),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_AXI_DATA_WIDTH(64),
|
||||
.C_AXI_ID_WIDTH(4),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_AXI_TYPE(0),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXIS_TDATA_WIDTH(64),
|
||||
.C_AXIS_TDEST_WIDTH(4),
|
||||
.C_AXIS_TID_WIDTH(8),
|
||||
.C_AXIS_TKEEP_WIDTH(8),
|
||||
.C_AXIS_TSTRB_WIDTH(8),
|
||||
.C_AXIS_TUSER_WIDTH(4),
|
||||
.C_AXIS_TYPE(0),
|
||||
.C_COMMON_CLOCK(0),
|
||||
.C_COUNT_TYPE(0),
|
||||
.C_DATA_COUNT_WIDTH(10),
|
||||
.C_DEFAULT_VALUE("BlankString"),
|
||||
.C_DIN_WIDTH(18),
|
||||
.C_DIN_WIDTH_AXIS(69),
|
||||
.C_DIN_WIDTH_RACH(32),
|
||||
.C_DIN_WIDTH_RDCH(64),
|
||||
.C_DIN_WIDTH_WACH(32),
|
||||
.C_DIN_WIDTH_WDCH(64),
|
||||
.C_DIN_WIDTH_WRCH(2),
|
||||
.C_DOUT_RST_VAL("0"),
|
||||
.C_DOUT_WIDTH(18),
|
||||
.C_ENABLE_RLOCS(0),
|
||||
.C_ENABLE_RST_SYNC(1),
|
||||
.C_ERROR_INJECTION_TYPE(0),
|
||||
.C_ERROR_INJECTION_TYPE_AXIS(0),
|
||||
.C_ERROR_INJECTION_TYPE_RACH(0),
|
||||
.C_ERROR_INJECTION_TYPE_RDCH(0),
|
||||
.C_ERROR_INJECTION_TYPE_WACH(0),
|
||||
.C_ERROR_INJECTION_TYPE_WDCH(0),
|
||||
.C_ERROR_INJECTION_TYPE_WRCH(0),
|
||||
.C_FAMILY("kintex7"),
|
||||
.C_FULL_FLAGS_RST_VAL(1),
|
||||
.C_HAS_ALMOST_EMPTY(0),
|
||||
.C_HAS_ALMOST_FULL(0),
|
||||
.C_HAS_AXI_ARUSER(0),
|
||||
.C_HAS_AXI_AWUSER(0),
|
||||
.C_HAS_AXI_BUSER(0),
|
||||
.C_HAS_AXI_RD_CHANNEL(0),
|
||||
.C_HAS_AXI_RUSER(0),
|
||||
.C_HAS_AXI_WR_CHANNEL(0),
|
||||
.C_HAS_AXI_WUSER(0),
|
||||
.C_HAS_AXIS_TDATA(1),
|
||||
.C_HAS_AXIS_TDEST(0),
|
||||
.C_HAS_AXIS_TID(0),
|
||||
.C_HAS_AXIS_TKEEP(0),
|
||||
.C_HAS_AXIS_TLAST(1),
|
||||
.C_HAS_AXIS_TREADY(1),
|
||||
.C_HAS_AXIS_TSTRB(0),
|
||||
.C_HAS_AXIS_TUSER(1),
|
||||
.C_HAS_BACKUP(0),
|
||||
.C_HAS_DATA_COUNT(0),
|
||||
.C_HAS_DATA_COUNTS_AXIS(1),
|
||||
.C_HAS_DATA_COUNTS_RACH(0),
|
||||
.C_HAS_DATA_COUNTS_RDCH(0),
|
||||
.C_HAS_DATA_COUNTS_WACH(0),
|
||||
.C_HAS_DATA_COUNTS_WDCH(0),
|
||||
.C_HAS_DATA_COUNTS_WRCH(0),
|
||||
.C_HAS_INT_CLK(0),
|
||||
.C_HAS_MASTER_CE(0),
|
||||
.C_HAS_MEMINIT_FILE(0),
|
||||
.C_HAS_OVERFLOW(0),
|
||||
.C_HAS_PROG_FLAGS_AXIS(0),
|
||||
.C_HAS_PROG_FLAGS_RACH(0),
|
||||
.C_HAS_PROG_FLAGS_RDCH(0),
|
||||
.C_HAS_PROG_FLAGS_WACH(0),
|
||||
.C_HAS_PROG_FLAGS_WDCH(0),
|
||||
.C_HAS_PROG_FLAGS_WRCH(0),
|
||||
.C_HAS_RD_DATA_COUNT(0),
|
||||
.C_HAS_RD_RST(0),
|
||||
.C_HAS_RST(1),
|
||||
.C_HAS_SLAVE_CE(0),
|
||||
.C_HAS_SRST(0),
|
||||
.C_HAS_UNDERFLOW(0),
|
||||
.C_HAS_VALID(0),
|
||||
.C_HAS_WR_ACK(0),
|
||||
.C_HAS_WR_DATA_COUNT(0),
|
||||
.C_HAS_WR_RST(0),
|
||||
.C_IMPLEMENTATION_TYPE(0),
|
||||
.C_IMPLEMENTATION_TYPE_AXIS(11),
|
||||
.C_IMPLEMENTATION_TYPE_RACH(12),
|
||||
.C_IMPLEMENTATION_TYPE_RDCH(11),
|
||||
.C_IMPLEMENTATION_TYPE_WACH(12),
|
||||
.C_IMPLEMENTATION_TYPE_WDCH(11),
|
||||
.C_IMPLEMENTATION_TYPE_WRCH(12),
|
||||
.C_INIT_WR_PNTR_VAL(0),
|
||||
.C_INTERFACE_TYPE(1),
|
||||
.C_MEMORY_TYPE(1),
|
||||
.C_MIF_FILE_NAME("BlankString"),
|
||||
.C_MSGON_VAL(1),
|
||||
.C_OPTIMIZATION_MODE(0),
|
||||
.C_OVERFLOW_LOW(0),
|
||||
.C_PRELOAD_LATENCY(1),
|
||||
.C_PRELOAD_REGS(0),
|
||||
.C_PRIM_FIFO_TYPE("4kx4"),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(509),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(13),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1021),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(13),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1021),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(13),
|
||||
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
|
||||
.C_PROG_EMPTY_TYPE(0),
|
||||
.C_PROG_EMPTY_TYPE_AXIS(0),
|
||||
.C_PROG_EMPTY_TYPE_RACH(0),
|
||||
.C_PROG_EMPTY_TYPE_RDCH(0),
|
||||
.C_PROG_EMPTY_TYPE_WACH(0),
|
||||
.C_PROG_EMPTY_TYPE_WDCH(0),
|
||||
.C_PROG_EMPTY_TYPE_WRCH(0),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL(1022),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(511),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(15),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(15),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),
|
||||
.C_PROG_FULL_THRESH_NEGATE_VAL(1021),
|
||||
.C_PROG_FULL_TYPE(0),
|
||||
.C_PROG_FULL_TYPE_AXIS(0),
|
||||
.C_PROG_FULL_TYPE_RACH(0),
|
||||
.C_PROG_FULL_TYPE_RDCH(0),
|
||||
.C_PROG_FULL_TYPE_WACH(0),
|
||||
.C_PROG_FULL_TYPE_WDCH(0),
|
||||
.C_PROG_FULL_TYPE_WRCH(0),
|
||||
.C_RACH_TYPE(0),
|
||||
.C_RD_DATA_COUNT_WIDTH(10),
|
||||
.C_RD_DEPTH(1024),
|
||||
.C_RD_FREQ(1),
|
||||
.C_RD_PNTR_WIDTH(10),
|
||||
.C_RDCH_TYPE(0),
|
||||
.C_REG_SLICE_MODE_AXIS(0),
|
||||
.C_REG_SLICE_MODE_RACH(0),
|
||||
.C_REG_SLICE_MODE_RDCH(0),
|
||||
.C_REG_SLICE_MODE_WACH(0),
|
||||
.C_REG_SLICE_MODE_WDCH(0),
|
||||
.C_REG_SLICE_MODE_WRCH(0),
|
||||
.C_SYNCHRONIZER_STAGE(2),
|
||||
.C_UNDERFLOW_LOW(0),
|
||||
.C_USE_COMMON_OVERFLOW(0),
|
||||
.C_USE_COMMON_UNDERFLOW(0),
|
||||
.C_USE_DEFAULT_SETTINGS(0),
|
||||
.C_USE_DOUT_RST(1),
|
||||
.C_USE_ECC(0),
|
||||
.C_USE_ECC_AXIS(0),
|
||||
.C_USE_ECC_RACH(0),
|
||||
.C_USE_ECC_RDCH(0),
|
||||
.C_USE_ECC_WACH(0),
|
||||
.C_USE_ECC_WDCH(0),
|
||||
.C_USE_ECC_WRCH(0),
|
||||
.C_USE_EMBEDDED_REG(0),
|
||||
.C_USE_FIFO16_FLAGS(0),
|
||||
.C_USE_FWFT_DATA_COUNT(0),
|
||||
.C_VALID_LOW(0),
|
||||
.C_WACH_TYPE(0),
|
||||
.C_WDCH_TYPE(0),
|
||||
.C_WR_ACK_LOW(0),
|
||||
.C_WR_DATA_COUNT_WIDTH(10),
|
||||
.C_WR_DEPTH(1024),
|
||||
.C_WR_DEPTH_AXIS(512),
|
||||
.C_WR_DEPTH_RACH(16),
|
||||
.C_WR_DEPTH_RDCH(1024),
|
||||
.C_WR_DEPTH_WACH(16),
|
||||
.C_WR_DEPTH_WDCH(1024),
|
||||
.C_WR_DEPTH_WRCH(16),
|
||||
.C_WR_FREQ(1),
|
||||
.C_WR_PNTR_WIDTH(10),
|
||||
.C_WR_PNTR_WIDTH_AXIS(9),
|
||||
.C_WR_PNTR_WIDTH_RACH(4),
|
||||
.C_WR_PNTR_WIDTH_RDCH(10),
|
||||
.C_WR_PNTR_WIDTH_WACH(4),
|
||||
.C_WR_PNTR_WIDTH_WDCH(10),
|
||||
.C_WR_PNTR_WIDTH_WRCH(4),
|
||||
.C_WR_RESPONSE_LATENCY(1),
|
||||
.C_WRCH_TYPE(0)
|
||||
)
|
||||
inst (
|
||||
.M_ACLK(m_aclk),
|
||||
.S_ACLK(s_aclk),
|
||||
.S_ARESETN(s_aresetn),
|
||||
.S_AXIS_TVALID(s_axis_tvalid),
|
||||
.S_AXIS_TREADY(s_axis_tready),
|
||||
.S_AXIS_TDATA(s_axis_tdata),
|
||||
.S_AXIS_TLAST(s_axis_tlast),
|
||||
.S_AXIS_TUSER(s_axis_tuser),
|
||||
.M_AXIS_TVALID(m_axis_tvalid),
|
||||
.M_AXIS_TREADY(m_axis_tready),
|
||||
.M_AXIS_TDATA(m_axis_tdata),
|
||||
.M_AXIS_TLAST(m_axis_tlast),
|
||||
.M_AXIS_TUSER(m_axis_tuser),
|
||||
.AXIS_WR_DATA_COUNT(axis_wr_data_count),
|
||||
.AXIS_RD_DATA_COUNT(axis_rd_data_count),
|
||||
.BACKUP(),
|
||||
.BACKUP_MARKER(),
|
||||
.CLK(),
|
||||
.RST(),
|
||||
.SRST(),
|
||||
.WR_CLK(),
|
||||
.WR_RST(),
|
||||
.RD_CLK(),
|
||||
.RD_RST(),
|
||||
.DIN(),
|
||||
.WR_EN(),
|
||||
.RD_EN(),
|
||||
.PROG_EMPTY_THRESH(),
|
||||
.PROG_EMPTY_THRESH_ASSERT(),
|
||||
.PROG_EMPTY_THRESH_NEGATE(),
|
||||
.PROG_FULL_THRESH(),
|
||||
.PROG_FULL_THRESH_ASSERT(),
|
||||
.PROG_FULL_THRESH_NEGATE(),
|
||||
.INT_CLK(),
|
||||
.INJECTDBITERR(),
|
||||
.INJECTSBITERR(),
|
||||
.DOUT(),
|
||||
.FULL(),
|
||||
.ALMOST_FULL(),
|
||||
.WR_ACK(),
|
||||
.OVERFLOW(),
|
||||
.EMPTY(),
|
||||
.ALMOST_EMPTY(),
|
||||
.VALID(),
|
||||
.UNDERFLOW(),
|
||||
.DATA_COUNT(),
|
||||
.RD_DATA_COUNT(),
|
||||
.WR_DATA_COUNT(),
|
||||
.PROG_FULL(),
|
||||
.PROG_EMPTY(),
|
||||
.SBITERR(),
|
||||
.DBITERR(),
|
||||
.M_ACLK_EN(),
|
||||
.S_ACLK_EN(),
|
||||
.S_AXI_AWID(),
|
||||
.S_AXI_AWADDR(),
|
||||
.S_AXI_AWLEN(),
|
||||
.S_AXI_AWSIZE(),
|
||||
.S_AXI_AWBURST(),
|
||||
.S_AXI_AWLOCK(),
|
||||
.S_AXI_AWCACHE(),
|
||||
.S_AXI_AWPROT(),
|
||||
.S_AXI_AWQOS(),
|
||||
.S_AXI_AWREGION(),
|
||||
.S_AXI_AWUSER(),
|
||||
.S_AXI_AWVALID(),
|
||||
.S_AXI_AWREADY(),
|
||||
.S_AXI_WID(),
|
||||
.S_AXI_WDATA(),
|
||||
.S_AXI_WSTRB(),
|
||||
.S_AXI_WLAST(),
|
||||
.S_AXI_WUSER(),
|
||||
.S_AXI_WVALID(),
|
||||
.S_AXI_WREADY(),
|
||||
.S_AXI_BID(),
|
||||
.S_AXI_BRESP(),
|
||||
.S_AXI_BUSER(),
|
||||
.S_AXI_BVALID(),
|
||||
.S_AXI_BREADY(),
|
||||
.M_AXI_AWID(),
|
||||
.M_AXI_AWADDR(),
|
||||
.M_AXI_AWLEN(),
|
||||
.M_AXI_AWSIZE(),
|
||||
.M_AXI_AWBURST(),
|
||||
.M_AXI_AWLOCK(),
|
||||
.M_AXI_AWCACHE(),
|
||||
.M_AXI_AWPROT(),
|
||||
.M_AXI_AWQOS(),
|
||||
.M_AXI_AWREGION(),
|
||||
.M_AXI_AWUSER(),
|
||||
.M_AXI_AWVALID(),
|
||||
.M_AXI_AWREADY(),
|
||||
.M_AXI_WID(),
|
||||
.M_AXI_WDATA(),
|
||||
.M_AXI_WSTRB(),
|
||||
.M_AXI_WLAST(),
|
||||
.M_AXI_WUSER(),
|
||||
.M_AXI_WVALID(),
|
||||
.M_AXI_WREADY(),
|
||||
.M_AXI_BID(),
|
||||
.M_AXI_BRESP(),
|
||||
.M_AXI_BUSER(),
|
||||
.M_AXI_BVALID(),
|
||||
.M_AXI_BREADY(),
|
||||
.S_AXI_ARID(),
|
||||
.S_AXI_ARADDR(),
|
||||
.S_AXI_ARLEN(),
|
||||
.S_AXI_ARSIZE(),
|
||||
.S_AXI_ARBURST(),
|
||||
.S_AXI_ARLOCK(),
|
||||
.S_AXI_ARCACHE(),
|
||||
.S_AXI_ARPROT(),
|
||||
.S_AXI_ARQOS(),
|
||||
.S_AXI_ARREGION(),
|
||||
.S_AXI_ARUSER(),
|
||||
.S_AXI_ARVALID(),
|
||||
.S_AXI_ARREADY(),
|
||||
.S_AXI_RID(),
|
||||
.S_AXI_RDATA(),
|
||||
.S_AXI_RRESP(),
|
||||
.S_AXI_RLAST(),
|
||||
.S_AXI_RUSER(),
|
||||
.S_AXI_RVALID(),
|
||||
.S_AXI_RREADY(),
|
||||
.M_AXI_ARID(),
|
||||
.M_AXI_ARADDR(),
|
||||
.M_AXI_ARLEN(),
|
||||
.M_AXI_ARSIZE(),
|
||||
.M_AXI_ARBURST(),
|
||||
.M_AXI_ARLOCK(),
|
||||
.M_AXI_ARCACHE(),
|
||||
.M_AXI_ARPROT(),
|
||||
.M_AXI_ARQOS(),
|
||||
.M_AXI_ARREGION(),
|
||||
.M_AXI_ARUSER(),
|
||||
.M_AXI_ARVALID(),
|
||||
.M_AXI_ARREADY(),
|
||||
.M_AXI_RID(),
|
||||
.M_AXI_RDATA(),
|
||||
.M_AXI_RRESP(),
|
||||
.M_AXI_RLAST(),
|
||||
.M_AXI_RUSER(),
|
||||
.M_AXI_RVALID(),
|
||||
.M_AXI_RREADY(),
|
||||
.S_AXIS_TSTRB(),
|
||||
.S_AXIS_TKEEP(),
|
||||
.S_AXIS_TID(),
|
||||
.S_AXIS_TDEST(),
|
||||
.M_AXIS_TSTRB(),
|
||||
.M_AXIS_TKEEP(),
|
||||
.M_AXIS_TID(),
|
||||
.M_AXIS_TDEST(),
|
||||
.AXI_AW_INJECTSBITERR(),
|
||||
.AXI_AW_INJECTDBITERR(),
|
||||
.AXI_AW_PROG_FULL_THRESH(),
|
||||
.AXI_AW_PROG_EMPTY_THRESH(),
|
||||
.AXI_AW_DATA_COUNT(),
|
||||
.AXI_AW_WR_DATA_COUNT(),
|
||||
.AXI_AW_RD_DATA_COUNT(),
|
||||
.AXI_AW_SBITERR(),
|
||||
.AXI_AW_DBITERR(),
|
||||
.AXI_AW_OVERFLOW(),
|
||||
.AXI_AW_UNDERFLOW(),
|
||||
.AXI_AW_PROG_FULL(),
|
||||
.AXI_AW_PROG_EMPTY(),
|
||||
.AXI_W_INJECTSBITERR(),
|
||||
.AXI_W_INJECTDBITERR(),
|
||||
.AXI_W_PROG_FULL_THRESH(),
|
||||
.AXI_W_PROG_EMPTY_THRESH(),
|
||||
.AXI_W_DATA_COUNT(),
|
||||
.AXI_W_WR_DATA_COUNT(),
|
||||
.AXI_W_RD_DATA_COUNT(),
|
||||
.AXI_W_SBITERR(),
|
||||
.AXI_W_DBITERR(),
|
||||
.AXI_W_OVERFLOW(),
|
||||
.AXI_W_UNDERFLOW(),
|
||||
.AXI_B_INJECTSBITERR(),
|
||||
.AXI_W_PROG_FULL(),
|
||||
.AXI_W_PROG_EMPTY(),
|
||||
.AXI_B_INJECTDBITERR(),
|
||||
.AXI_B_PROG_FULL_THRESH(),
|
||||
.AXI_B_PROG_EMPTY_THRESH(),
|
||||
.AXI_B_DATA_COUNT(),
|
||||
.AXI_B_WR_DATA_COUNT(),
|
||||
.AXI_B_RD_DATA_COUNT(),
|
||||
.AXI_B_SBITERR(),
|
||||
.AXI_B_DBITERR(),
|
||||
.AXI_B_OVERFLOW(),
|
||||
.AXI_B_UNDERFLOW(),
|
||||
.AXI_AR_INJECTSBITERR(),
|
||||
.AXI_B_PROG_FULL(),
|
||||
.AXI_B_PROG_EMPTY(),
|
||||
.AXI_AR_INJECTDBITERR(),
|
||||
.AXI_AR_PROG_FULL_THRESH(),
|
||||
.AXI_AR_PROG_EMPTY_THRESH(),
|
||||
.AXI_AR_DATA_COUNT(),
|
||||
.AXI_AR_WR_DATA_COUNT(),
|
||||
.AXI_AR_RD_DATA_COUNT(),
|
||||
.AXI_AR_SBITERR(),
|
||||
.AXI_AR_DBITERR(),
|
||||
.AXI_AR_OVERFLOW(),
|
||||
.AXI_AR_UNDERFLOW(),
|
||||
.AXI_AR_PROG_FULL(),
|
||||
.AXI_AR_PROG_EMPTY(),
|
||||
.AXI_R_INJECTSBITERR(),
|
||||
.AXI_R_INJECTDBITERR(),
|
||||
.AXI_R_PROG_FULL_THRESH(),
|
||||
.AXI_R_PROG_EMPTY_THRESH(),
|
||||
.AXI_R_DATA_COUNT(),
|
||||
.AXI_R_WR_DATA_COUNT(),
|
||||
.AXI_R_RD_DATA_COUNT(),
|
||||
.AXI_R_SBITERR(),
|
||||
.AXI_R_DBITERR(),
|
||||
.AXI_R_OVERFLOW(),
|
||||
.AXI_R_UNDERFLOW(),
|
||||
.AXIS_INJECTSBITERR(),
|
||||
.AXI_R_PROG_FULL(),
|
||||
.AXI_R_PROG_EMPTY(),
|
||||
.AXIS_INJECTDBITERR(),
|
||||
.AXIS_PROG_FULL_THRESH(),
|
||||
.AXIS_PROG_EMPTY_THRESH(),
|
||||
.AXIS_DATA_COUNT(),
|
||||
.AXIS_SBITERR(),
|
||||
.AXIS_DBITERR(),
|
||||
.AXIS_OVERFLOW(),
|
||||
.AXIS_UNDERFLOW(),
|
||||
.AXIS_PROG_FULL(),
|
||||
.AXIS_PROG_EMPTY()
|
||||
);
|
||||
|
||||
// synthesis translate_on
|
||||
|
||||
endmodule
|
||||
@@ -1,83 +0,0 @@
|
||||
/*******************************************************************************
|
||||
* This file is owned and controlled by Xilinx and must be used solely *
|
||||
* for design, simulation, implementation and creation of design files *
|
||||
* limited to Xilinx devices or technologies. Use with non-Xilinx *
|
||||
* devices or technologies is expressly prohibited and immediately *
|
||||
* terminates your license. *
|
||||
* *
|
||||
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
|
||||
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
|
||||
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
|
||||
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
|
||||
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
|
||||
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
|
||||
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
|
||||
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
|
||||
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
|
||||
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
|
||||
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
|
||||
* PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* Xilinx products are not intended for use in life support appliances, *
|
||||
* devices, or systems. Use in such applications are expressly *
|
||||
* prohibited. *
|
||||
* *
|
||||
* (c) Copyright 1995-2014 Xilinx, Inc. *
|
||||
* All rights reserved. *
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 *
|
||||
* *
|
||||
* Rev 1. The FIFO Generator is a parameterizable first-in/first-out *
|
||||
* memory queue generator. Use it to generate resource and performance *
|
||||
* optimized FIFOs with common or independent read/write clock domains, *
|
||||
* and optional fixed or programmable full and empty flags and *
|
||||
* handshaking signals. Choose from a selection of memory resource *
|
||||
* types for implementation. Optional Hamming code based error *
|
||||
* detection and correction as well as error injection capability for *
|
||||
* system test help to insure data integrity. FIFO width and depth are *
|
||||
* parameterizable, and for native interface FIFOs, asymmetric read and *
|
||||
* write port widths are also supported. *
|
||||
*******************************************************************************/
|
||||
|
||||
// Interfaces:
|
||||
// AXI4Stream_MASTER_M_AXIS
|
||||
// AXI4Stream_SLAVE_S_AXIS
|
||||
// AXI4_MASTER_M_AXI
|
||||
// AXI4_SLAVE_S_AXI
|
||||
// AXI4Lite_MASTER_M_AXI
|
||||
// AXI4Lite_SLAVE_S_AXI
|
||||
// master_aclk
|
||||
// slave_aclk
|
||||
// slave_aresetn
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
axi64_4k_2clk_fifo your_instance_name (
|
||||
.m_aclk(m_aclk), // input m_aclk
|
||||
.s_aclk(s_aclk), // input s_aclk
|
||||
.s_aresetn(s_aresetn), // input s_aresetn
|
||||
.s_axis_tvalid(s_axis_tvalid), // input s_axis_tvalid
|
||||
.s_axis_tready(s_axis_tready), // output s_axis_tready
|
||||
.s_axis_tdata(s_axis_tdata), // input [63 : 0] s_axis_tdata
|
||||
.s_axis_tlast(s_axis_tlast), // input s_axis_tlast
|
||||
.s_axis_tuser(s_axis_tuser), // input [3 : 0] s_axis_tuser
|
||||
.m_axis_tvalid(m_axis_tvalid), // output m_axis_tvalid
|
||||
.m_axis_tready(m_axis_tready), // input m_axis_tready
|
||||
.m_axis_tdata(m_axis_tdata), // output [63 : 0] m_axis_tdata
|
||||
.m_axis_tlast(m_axis_tlast), // output m_axis_tlast
|
||||
.m_axis_tuser(m_axis_tuser), // output [3 : 0] m_axis_tuser
|
||||
.axis_wr_data_count(axis_wr_data_count), // output [9 : 0] axis_wr_data_count
|
||||
.axis_rd_data_count(axis_rd_data_count) // output [9 : 0] axis_rd_data_count
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file axi64_4k_2clk_fifo.v when simulating
|
||||
// the core, axi64_4k_2clk_fifo. When compiling the wrapper file, be sure to
|
||||
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
||||
// instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
@@ -1,213 +0,0 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.7
|
||||
# Date: Wed Sep 3 23:46:32 2014
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:fifo_generator:9.3
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Verilog
|
||||
SET device = xc7k410t
|
||||
SET devicefamily = kintex7
|
||||
SET flowvendor = Foundation_ISE
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = ffg900
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -2
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = false
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET add_ngc_constraint_axi=false
|
||||
CSET almost_empty_flag=false
|
||||
CSET almost_full_flag=false
|
||||
CSET aruser_width=1
|
||||
CSET awuser_width=1
|
||||
CSET axi_address_width=32
|
||||
CSET axi_data_width=64
|
||||
CSET axi_type=AXI4_Stream
|
||||
CSET axis_type=FIFO
|
||||
CSET buser_width=1
|
||||
CSET clock_enable_type=Slave_Interface_Clock_Enable
|
||||
CSET clock_type_axi=Independent_Clock
|
||||
CSET component_name=axi64_4k_2clk_fifo
|
||||
CSET data_count=false
|
||||
CSET data_count_width=10
|
||||
CSET disable_timing_violations=false
|
||||
CSET disable_timing_violations_axi=false
|
||||
CSET dout_reset_value=0
|
||||
CSET empty_threshold_assert_value=2
|
||||
CSET empty_threshold_assert_value_axis=509
|
||||
CSET empty_threshold_assert_value_rach=13
|
||||
CSET empty_threshold_assert_value_rdch=1021
|
||||
CSET empty_threshold_assert_value_wach=13
|
||||
CSET empty_threshold_assert_value_wdch=1021
|
||||
CSET empty_threshold_assert_value_wrch=13
|
||||
CSET empty_threshold_negate_value=3
|
||||
CSET enable_aruser=false
|
||||
CSET enable_awuser=false
|
||||
CSET enable_buser=false
|
||||
CSET enable_common_overflow=false
|
||||
CSET enable_common_underflow=false
|
||||
CSET enable_data_counts_axis=true
|
||||
CSET enable_data_counts_rach=false
|
||||
CSET enable_data_counts_rdch=false
|
||||
CSET enable_data_counts_wach=false
|
||||
CSET enable_data_counts_wdch=false
|
||||
CSET enable_data_counts_wrch=false
|
||||
CSET enable_ecc=false
|
||||
CSET enable_ecc_axis=false
|
||||
CSET enable_ecc_rach=false
|
||||
CSET enable_ecc_rdch=false
|
||||
CSET enable_ecc_wach=false
|
||||
CSET enable_ecc_wdch=false
|
||||
CSET enable_ecc_wrch=false
|
||||
CSET enable_read_channel=false
|
||||
CSET enable_read_pointer_increment_by2=false
|
||||
CSET enable_reset_synchronization=true
|
||||
CSET enable_ruser=false
|
||||
CSET enable_tdata=true
|
||||
CSET enable_tdest=false
|
||||
CSET enable_tid=false
|
||||
CSET enable_tkeep=false
|
||||
CSET enable_tlast=true
|
||||
CSET enable_tready=true
|
||||
CSET enable_tstrobe=false
|
||||
CSET enable_tuser=true
|
||||
CSET enable_write_channel=false
|
||||
CSET enable_wuser=false
|
||||
CSET fifo_application_type_axis=Data_FIFO
|
||||
CSET fifo_application_type_rach=Data_FIFO
|
||||
CSET fifo_application_type_rdch=Data_FIFO
|
||||
CSET fifo_application_type_wach=Data_FIFO
|
||||
CSET fifo_application_type_wdch=Data_FIFO
|
||||
CSET fifo_application_type_wrch=Data_FIFO
|
||||
CSET fifo_implementation=Common_Clock_Block_RAM
|
||||
CSET fifo_implementation_axis=Independent_Clocks_Block_RAM
|
||||
CSET fifo_implementation_rach=Independent_Clocks_Distributed_RAM
|
||||
CSET fifo_implementation_rdch=Independent_Clocks_Block_RAM
|
||||
CSET fifo_implementation_wach=Independent_Clocks_Distributed_RAM
|
||||
CSET fifo_implementation_wdch=Independent_Clocks_Block_RAM
|
||||
CSET fifo_implementation_wrch=Independent_Clocks_Distributed_RAM
|
||||
CSET full_flags_reset_value=1
|
||||
CSET full_threshold_assert_value=1022
|
||||
CSET full_threshold_assert_value_axis=511
|
||||
CSET full_threshold_assert_value_rach=15
|
||||
CSET full_threshold_assert_value_rdch=1023
|
||||
CSET full_threshold_assert_value_wach=15
|
||||
CSET full_threshold_assert_value_wdch=1023
|
||||
CSET full_threshold_assert_value_wrch=15
|
||||
CSET full_threshold_negate_value=1021
|
||||
CSET id_width=4
|
||||
CSET inject_dbit_error=false
|
||||
CSET inject_dbit_error_axis=false
|
||||
CSET inject_dbit_error_rach=false
|
||||
CSET inject_dbit_error_rdch=false
|
||||
CSET inject_dbit_error_wach=false
|
||||
CSET inject_dbit_error_wdch=false
|
||||
CSET inject_dbit_error_wrch=false
|
||||
CSET inject_sbit_error=false
|
||||
CSET inject_sbit_error_axis=false
|
||||
CSET inject_sbit_error_rach=false
|
||||
CSET inject_sbit_error_rdch=false
|
||||
CSET inject_sbit_error_wach=false
|
||||
CSET inject_sbit_error_wdch=false
|
||||
CSET inject_sbit_error_wrch=false
|
||||
CSET input_data_width=18
|
||||
CSET input_depth=1024
|
||||
CSET input_depth_axis=512
|
||||
CSET input_depth_rach=16
|
||||
CSET input_depth_rdch=1024
|
||||
CSET input_depth_wach=16
|
||||
CSET input_depth_wdch=1024
|
||||
CSET input_depth_wrch=16
|
||||
CSET interface_type=AXI4
|
||||
CSET output_data_width=18
|
||||
CSET output_depth=1024
|
||||
CSET overflow_flag=false
|
||||
CSET overflow_flag_axi=false
|
||||
CSET overflow_sense=Active_High
|
||||
CSET overflow_sense_axi=Active_High
|
||||
CSET performance_options=Standard_FIFO
|
||||
CSET programmable_empty_type=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
|
||||
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
|
||||
CSET programmable_full_type=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
|
||||
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
|
||||
CSET rach_type=FIFO
|
||||
CSET rdch_type=FIFO
|
||||
CSET read_clock_frequency=1
|
||||
CSET read_data_count=false
|
||||
CSET read_data_count_width=10
|
||||
CSET register_slice_mode_axis=Fully_Registered
|
||||
CSET register_slice_mode_rach=Fully_Registered
|
||||
CSET register_slice_mode_rdch=Fully_Registered
|
||||
CSET register_slice_mode_wach=Fully_Registered
|
||||
CSET register_slice_mode_wdch=Fully_Registered
|
||||
CSET register_slice_mode_wrch=Fully_Registered
|
||||
CSET reset_pin=true
|
||||
CSET reset_type=Asynchronous_Reset
|
||||
CSET ruser_width=1
|
||||
CSET synchronization_stages=2
|
||||
CSET synchronization_stages_axi=2
|
||||
CSET tdata_width=64
|
||||
CSET tdest_width=4
|
||||
CSET tid_width=8
|
||||
CSET tkeep_width=8
|
||||
CSET tstrb_width=8
|
||||
CSET tuser_width=4
|
||||
CSET underflow_flag=false
|
||||
CSET underflow_flag_axi=false
|
||||
CSET underflow_sense=Active_High
|
||||
CSET underflow_sense_axi=Active_High
|
||||
CSET use_clock_enable=false
|
||||
CSET use_dout_reset=true
|
||||
CSET use_embedded_registers=false
|
||||
CSET use_extra_logic=false
|
||||
CSET valid_flag=false
|
||||
CSET valid_sense=Active_High
|
||||
CSET wach_type=FIFO
|
||||
CSET wdch_type=FIFO
|
||||
CSET wrch_type=FIFO
|
||||
CSET write_acknowledge_flag=false
|
||||
CSET write_acknowledge_sense=Active_High
|
||||
CSET write_clock_frequency=1
|
||||
CSET write_data_count=false
|
||||
CSET write_data_count_width=10
|
||||
CSET wuser_width=1
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-11-19T12:39:56Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: 3dff5455
|
||||
@@ -1,361 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="axi64_4k_2clk_fifo.ngc" xil_pn:type="FILE_NGC">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="axi64_4k_2clk_fifo.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc7k410t" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Kintex7" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|axi64_4k_2clk_fifo" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="axi64_4k_2clk_fifo.ngc" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/axi64_4k_2clk_fifo" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="axi64_4k_2clk_fifo" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="ffg900" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="axi64_4k_2clk_fifo_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="axi64_4k_2clk_fifo_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="axi64_4k_2clk_fifo_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="axi64_4k_2clk_fifo_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="axi64_4k_2clk_fifo" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="kintex7" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-09-03T16:47:54" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="B549470EEC291A61A895D80D7556E7AD" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
@@ -1,236 +0,0 @@
|
||||
CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1
|
||||
|
||||
Release Date: December 18, 2012
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURE HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
|
||||
|
||||
For system requirements:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
All Virtex-6 devices
|
||||
All Spartan-6 devices
|
||||
All Virtex-5 devices
|
||||
All Spartan-3 devices
|
||||
All Virtex-4 devices
|
||||
|
||||
|
||||
2.2 Vivado
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
3. NEW FEATURE HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- ISE 14.4 software support
|
||||
|
||||
|
||||
3.2 Vivado
|
||||
|
||||
- 2012.4 software support
|
||||
- IP level constraint for Built-in FIFO reset synchronizer
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
4.1 ISE
|
||||
|
||||
- N/A
|
||||
|
||||
|
||||
4.2 Vivado
|
||||
|
||||
- N/A
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
The following are known issues for v9.3 Rev 1 of this core at time of release:
|
||||
|
||||
1. Importing an XCO file alters the XCO configurations
|
||||
|
||||
Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
|
||||
into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,
|
||||
page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
|
||||
|
||||
CR 467240
|
||||
AR 31379
|
||||
|
||||
2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
|
||||
|
||||
Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
|
||||
correct behavior of the FIFO status flags cannot be guaranteed after the first write.
|
||||
|
||||
Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
|
||||
For more information and additional workaround see Answer Record 41099.
|
||||
|
||||
5.2 Vivado
|
||||
|
||||
The following are known issues for v9.3 Rev 1 of this core at time of release:
|
||||
|
||||
1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen
|
||||
ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
|
||||
|
||||
CR 665836
|
||||
|
||||
The most recent information, including known issues, workarounds, and
|
||||
resolutions for this version is provided in the IP Release Notes User Guide
|
||||
located at
|
||||
|
||||
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
To obtain technical support, create a WebCase at www.xilinx.com/support.
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer
|
||||
10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
|
||||
07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
|
||||
04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
|
||||
AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
|
||||
01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
|
||||
10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support
|
||||
06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
|
||||
03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
|
||||
10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support
|
||||
09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support
|
||||
07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support
|
||||
06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support
|
||||
12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
|
||||
09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
|
||||
06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support
|
||||
04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support
|
||||
09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
|
||||
03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes
|
||||
10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
|
||||
08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
|
||||
04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
|
||||
09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
|
||||
07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support
|
||||
01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3
|
||||
08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2
|
||||
04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1
|
||||
11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0
|
||||
05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support
|
||||
04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release
|
||||
================================================================================
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
@@ -1,247 +0,0 @@
|
||||
<HTML>
|
||||
<HEAD>
|
||||
<TITLE>fifo_generator_v9_3_vinfo</TITLE>
|
||||
<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
|
||||
</HEAD>
|
||||
<BODY>
|
||||
<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
|
||||
CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1
|
||||
|
||||
Release Date: December 18, 2012
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURE HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
|
||||
|
||||
For system requirements:
|
||||
|
||||
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
<A HREF="http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm">www.xilinx.com/products/ipcenter/FIFO_Generator.htm</A>
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
All Virtex-6 devices
|
||||
All Spartan-6 devices
|
||||
All Virtex-5 devices
|
||||
All Spartan-3 devices
|
||||
All Virtex-4 devices
|
||||
|
||||
|
||||
2.2 Vivado
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
3. NEW FEATURE HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- ISE 14.4 software support
|
||||
|
||||
|
||||
3.2 Vivado
|
||||
|
||||
- 2012.4 software support
|
||||
- IP level constraint for Built-in FIFO reset synchronizer
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
4.1 ISE
|
||||
|
||||
- N/A
|
||||
|
||||
|
||||
4.2 Vivado
|
||||
|
||||
- N/A
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
The following are known issues for v9.3 Rev 1 of this core at time of release:
|
||||
|
||||
1. Importing an XCO file alters the XCO configurations
|
||||
|
||||
Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
|
||||
into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,
|
||||
page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
|
||||
|
||||
CR 467240
|
||||
AR 31379
|
||||
|
||||
2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
|
||||
|
||||
Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
|
||||
correct behavior of the FIFO status flags cannot be guaranteed after the first write.
|
||||
|
||||
Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
|
||||
For more information and additional workaround see Answer Record 41099.
|
||||
|
||||
5.2 Vivado
|
||||
|
||||
The following are known issues for v9.3 Rev 1 of this core at time of release:
|
||||
|
||||
1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen
|
||||
ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
|
||||
|
||||
CR 665836
|
||||
|
||||
The most recent information, including known issues, workarounds, and
|
||||
resolutions for this version is provided in the IP Release Notes User Guide
|
||||
located at
|
||||
|
||||
<A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer
|
||||
10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
|
||||
07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
|
||||
04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
|
||||
AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
|
||||
01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
|
||||
10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support
|
||||
06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
|
||||
03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
|
||||
10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support
|
||||
09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support
|
||||
07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support
|
||||
06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support
|
||||
12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
|
||||
09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
|
||||
06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support
|
||||
04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support
|
||||
09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
|
||||
03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes
|
||||
10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
|
||||
08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
|
||||
04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
|
||||
09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
|
||||
07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support
|
||||
01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3
|
||||
08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2
|
||||
04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1
|
||||
11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0
|
||||
05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support
|
||||
04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release
|
||||
================================================================================
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
</FONT>
|
||||
</PRE>
|
||||
</BODY>
|
||||
</HTML>
|
||||
Binary file not shown.
@@ -1,56 +0,0 @@
|
||||
################################################################################
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
# Core Period Constraint. This constraint can be modified, and is
|
||||
# valid as long as it is met after place and route.
|
||||
NET "S_ACLK" TNM_NET = "S_ACLK";
|
||||
NET "M_ACLK" TNM_NET = "M_ACLK";
|
||||
TIMESPEC "TS_S_ACLK" = PERIOD "S_ACLK" 1 MHZ;
|
||||
TIMESPEC "TS_M_ACLK" = PERIOD "M_ACLK" 1 MHZ;
|
||||
################################################################################
|
||||
@@ -1,156 +0,0 @@
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- FIFO Generator Core - core top file for implementation
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: axi64_4k_2clk_fifo_exdes.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- This is the FIFO core wrapper with BUFG instances for clock connections.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Entity Declaration
|
||||
--------------------------------------------------------------------------------
|
||||
entity axi64_4k_2clk_fifo_exdes is
|
||||
PORT (
|
||||
S_ARESETN : IN std_logic;
|
||||
M_AXIS_TVALID : OUT std_logic;
|
||||
M_AXIS_TREADY : IN std_logic;
|
||||
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT std_logic;
|
||||
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN std_logic;
|
||||
S_AXIS_TREADY : OUT std_logic;
|
||||
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN std_logic;
|
||||
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
|
||||
AXIS_WR_DATA_COUNT : OUT std_logic_vector(9 DOWNTO 0);
|
||||
AXIS_RD_DATA_COUNT : OUT std_logic_vector(9 DOWNTO 0);
|
||||
M_ACLK : IN std_logic;
|
||||
S_ACLK : IN std_logic);
|
||||
|
||||
end axi64_4k_2clk_fifo_exdes;
|
||||
|
||||
|
||||
|
||||
architecture xilinx of axi64_4k_2clk_fifo_exdes is
|
||||
|
||||
|
||||
signal s_aclk_i : std_logic;
|
||||
signal m_aclk_i : std_logic;
|
||||
|
||||
|
||||
component axi64_4k_2clk_fifo is
|
||||
PORT (
|
||||
S_ARESETN : IN std_logic;
|
||||
M_AXIS_TVALID : OUT std_logic;
|
||||
M_AXIS_TREADY : IN std_logic;
|
||||
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT std_logic;
|
||||
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN std_logic;
|
||||
S_AXIS_TREADY : OUT std_logic;
|
||||
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN std_logic;
|
||||
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
|
||||
AXIS_WR_DATA_COUNT : OUT std_logic_vector(9 DOWNTO 0);
|
||||
AXIS_RD_DATA_COUNT : OUT std_logic_vector(9 DOWNTO 0);
|
||||
M_ACLK : IN std_logic;
|
||||
S_ACLK : IN std_logic);
|
||||
|
||||
end component;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
s_aclk_buf: bufg
|
||||
PORT map(
|
||||
i => S_ACLK,
|
||||
o => s_aclk_i
|
||||
);
|
||||
|
||||
m_aclk_buf: bufg
|
||||
PORT map(
|
||||
i => M_ACLK,
|
||||
o => m_aclk_i
|
||||
);
|
||||
|
||||
exdes_inst : axi64_4k_2clk_fifo
|
||||
PORT MAP (
|
||||
S_ARESETN => s_aresetn,
|
||||
M_AXIS_TVALID => m_axis_tvalid,
|
||||
M_AXIS_TREADY => m_axis_tready,
|
||||
M_AXIS_TDATA => m_axis_tdata,
|
||||
M_AXIS_TLAST => m_axis_tlast,
|
||||
M_AXIS_TUSER => m_axis_tuser,
|
||||
S_AXIS_TVALID => s_axis_tvalid,
|
||||
S_AXIS_TREADY => s_axis_tready,
|
||||
S_AXIS_TDATA => s_axis_tdata,
|
||||
S_AXIS_TLAST => s_axis_tlast,
|
||||
S_AXIS_TUSER => s_axis_tuser,
|
||||
AXIS_WR_DATA_COUNT => axis_wr_data_count,
|
||||
AXIS_RD_DATA_COUNT => axis_rd_data_count,
|
||||
M_ACLK => m_aclk_i,
|
||||
S_ACLK => s_aclk_i);
|
||||
|
||||
end xilinx;
|
||||
@@ -1,236 +0,0 @@
|
||||
CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1
|
||||
|
||||
Release Date: December 18, 2012
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
|
||||
1. INTRODUCTION
|
||||
2. DEVICE SUPPORT
|
||||
3. NEW FEATURE HISTORY
|
||||
4. RESOLVED ISSUES
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
7. CORE RELEASE HISTORY
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
1. INTRODUCTION
|
||||
|
||||
For installation instructions for this release, please go to:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
|
||||
|
||||
For system requirements:
|
||||
|
||||
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
|
||||
|
||||
This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1
|
||||
solution. For the latest core updates, see the product page at:
|
||||
|
||||
http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
2. DEVICE SUPPORT
|
||||
|
||||
|
||||
2.1 ISE
|
||||
|
||||
The following device families are supported by the core for this release.
|
||||
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
All Virtex-6 devices
|
||||
All Spartan-6 devices
|
||||
All Virtex-5 devices
|
||||
All Spartan-3 devices
|
||||
All Virtex-4 devices
|
||||
|
||||
|
||||
2.2 Vivado
|
||||
|
||||
All 7 Series devices
|
||||
Zynq-7000 devices
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
3. NEW FEATURE HISTORY
|
||||
|
||||
|
||||
3.1 ISE
|
||||
|
||||
- ISE 14.4 software support
|
||||
|
||||
|
||||
3.2 Vivado
|
||||
|
||||
- 2012.4 software support
|
||||
- IP level constraint for Built-in FIFO reset synchronizer
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
4. RESOLVED ISSUES
|
||||
|
||||
|
||||
4.1 ISE
|
||||
|
||||
- N/A
|
||||
|
||||
|
||||
4.2 Vivado
|
||||
|
||||
- N/A
|
||||
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
5. KNOWN ISSUES & LIMITATIONS
|
||||
|
||||
|
||||
5.1 ISE
|
||||
|
||||
The following are known issues for v9.3 Rev 1 of this core at time of release:
|
||||
|
||||
1. Importing an XCO file alters the XCO configurations
|
||||
|
||||
Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
|
||||
into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,
|
||||
page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
|
||||
|
||||
CR 467240
|
||||
AR 31379
|
||||
|
||||
2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
|
||||
|
||||
Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
|
||||
correct behavior of the FIFO status flags cannot be guaranteed after the first write.
|
||||
|
||||
Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
|
||||
For more information and additional workaround see Answer Record 41099.
|
||||
|
||||
5.2 Vivado
|
||||
|
||||
The following are known issues for v9.3 Rev 1 of this core at time of release:
|
||||
|
||||
1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen
|
||||
ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
|
||||
|
||||
CR 665836
|
||||
|
||||
The most recent information, including known issues, workarounds, and
|
||||
resolutions for this version is provided in the IP Release Notes User Guide
|
||||
located at
|
||||
|
||||
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
6. TECHNICAL SUPPORT & FEEDBACK
|
||||
|
||||
To obtain technical support, create a WebCase at www.xilinx.com/support.
|
||||
Questions are routed to a team with expertise using this product.
|
||||
|
||||
Xilinx provides technical support for use of this product when used
|
||||
according to the guidelines described in the core documentation, and
|
||||
cannot guarantee timing, functionality, or support of this product for
|
||||
designs that do not follow specified guidelines.
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
7. CORE RELEASE HISTORY
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
12/18/2012 Xilinx, Inc. 9.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer
|
||||
10/16/2012 Xilinx, Inc. 9.3 ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
|
||||
07/25/2012 Xilinx, Inc. 9.2 ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
|
||||
04/24/2012 Xilinx, Inc. 9.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
|
||||
AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
|
||||
01/18/2012 Xilinx, Inc. 8.4 ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
|
||||
10/19/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L device support
|
||||
06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
|
||||
03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
|
||||
10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support
|
||||
09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support
|
||||
07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support
|
||||
06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support
|
||||
04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support
|
||||
12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
|
||||
09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
|
||||
06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support
|
||||
04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support
|
||||
09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
|
||||
03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes
|
||||
10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
|
||||
08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
|
||||
04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
|
||||
09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
|
||||
07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support
|
||||
01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3
|
||||
08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2
|
||||
04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1
|
||||
11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0
|
||||
05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support
|
||||
04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release
|
||||
================================================================================
|
||||
|
||||
................................................................................
|
||||
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
|
||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
@@ -1,88 +0,0 @@
|
||||
:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
::
|
||||
:: This file contains confidential and proprietary information
|
||||
:: of Xilinx, Inc. and is protected under U.S. and
|
||||
:: international copyright and other intellectual property
|
||||
:: laws.
|
||||
::
|
||||
:: DISCLAIMER
|
||||
:: This disclaimer is not a license and does not grant any
|
||||
:: rights to the materials distributed herewith. Except as
|
||||
:: otherwise provided in a valid license issued to you by
|
||||
:: Xilinx, and to the maximum extent permitted by applicable
|
||||
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
:: (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
:: including negligence, or under any other theory of
|
||||
:: liability) for any loss or damage of any kind or nature
|
||||
:: related to, arising under or in connection with these
|
||||
:: materials, including for any direct, or any indirect,
|
||||
:: special, incidental, or consequential loss or damage
|
||||
:: (including loss of data, profits, goodwill, or any type of
|
||||
:: loss or damage suffered as a result of any action brought
|
||||
:: by a third party) even if such damage or loss was
|
||||
:: reasonably foreseeable or Xilinx had been advised of the
|
||||
:: possibility of the same.
|
||||
::
|
||||
:: CRITICAL APPLICATIONS
|
||||
:: Xilinx products are not designed or intended to be fail-
|
||||
:: safe, or for use in any application requiring fail-safe
|
||||
:: performance, such as life-support or safety devices or
|
||||
:: systems, Class III medical devices, nuclear facilities,
|
||||
:: applications related to the deployment of airbags, or any
|
||||
:: other applications that could lead to death, personal
|
||||
:: injury, or severe property or environmental damage
|
||||
:: (individually and collectively, "Critical
|
||||
:: Applications"). Customer assumes the sole risk and
|
||||
:: liability of any use of Xilinx products in Critical
|
||||
:: Applications, subject only to applicable laws and
|
||||
:: regulations governing limitations on product liability.
|
||||
::
|
||||
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
:: PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
rem Clean up the results directory
|
||||
rmdir /S /Q results
|
||||
mkdir results
|
||||
|
||||
rem Synthesize the VHDL Wrapper Files
|
||||
|
||||
#Synthesize the Wrapper Files
|
||||
|
||||
echo 'Synthesizing example design with XST';
|
||||
xst -ifn xst.scr
|
||||
copy axi64_4k_2clk_fifo_exdes.ngc .\results\
|
||||
|
||||
|
||||
rem Copy the netlist generated by Coregen
|
||||
echo 'Copying files from the netlist directory to the results directory'
|
||||
copy ..\..\axi64_4k_2clk_fifo.ngc results\
|
||||
|
||||
|
||||
rem Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
copy ..\example_design\axi64_4k_2clk_fifo_exdes.ucf results\
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
|
||||
ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi64_4k_2clk_fifo_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map axi64_4k_2clk_fifo_exdes -o mapped.ncd
|
||||
|
||||
echo 'Running par'
|
||||
par mapped.ncd routed.ncd
|
||||
|
||||
echo 'Running trce'
|
||||
trce -e 10 routed.ncd mapped.pcf -o routed
|
||||
|
||||
echo 'Running design through bitgen'
|
||||
bitgen -w routed -g UnconstrainedPins:Allow
|
||||
|
||||
echo 'Running netgen to create gate level Verilog model'
|
||||
netgen -ofmt verilog -sim -tm axi64_4k_2clk_fifo_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
|
||||
@@ -1,87 +0,0 @@
|
||||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
# Clean up the results directory
|
||||
rm -rf results
|
||||
mkdir results
|
||||
|
||||
#Synthesize the Wrapper Files
|
||||
|
||||
echo 'Synthesizing example design with XST';
|
||||
xst -ifn xst.scr
|
||||
cp axi64_4k_2clk_fifo_exdes.ngc ./results/
|
||||
|
||||
|
||||
# Copy the netlist generated by Coregen
|
||||
echo 'Copying files from the netlist directory to the results directory'
|
||||
cp ../../axi64_4k_2clk_fifo.ngc results/
|
||||
|
||||
# Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
cp ../example_design/axi64_4k_2clk_fifo_exdes.ucf results/
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
|
||||
ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi64_4k_2clk_fifo_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map axi64_4k_2clk_fifo_exdes -o mapped.ncd
|
||||
|
||||
echo 'Running par'
|
||||
par mapped.ncd routed.ncd
|
||||
|
||||
echo 'Running trce'
|
||||
trce -e 10 routed.ncd mapped.pcf -o routed
|
||||
|
||||
echo 'Running design through bitgen'
|
||||
bitgen -w routed -g UnconstrainedPins:Allow
|
||||
|
||||
echo 'Running netgen to create gate level Verilog model'
|
||||
netgen -ofmt verilog -sim -tm axi64_4k_2clk_fifo_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
|
||||
|
||||
@@ -1,87 +0,0 @@
|
||||
:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
::
|
||||
:: This file contains confidential and proprietary information
|
||||
:: of Xilinx, Inc. and is protected under U.S. and
|
||||
:: international copyright and other intellectual property
|
||||
:: laws.
|
||||
::
|
||||
:: DISCLAIMER
|
||||
:: This disclaimer is not a license and does not grant any
|
||||
:: rights to the materials distributed herewith. Except as
|
||||
:: otherwise provided in a valid license issued to you by
|
||||
:: Xilinx, and to the maximum extent permitted by applicable
|
||||
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
:: (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
:: including negligence, or under any other theory of
|
||||
:: liability) for any loss or damage of any kind or nature
|
||||
:: related to, arising under or in connection with these
|
||||
:: materials, including for any direct, or any indirect,
|
||||
:: special, incidental, or consequential loss or damage
|
||||
:: (including loss of data, profits, goodwill, or any type of
|
||||
:: loss or damage suffered as a result of any action brought
|
||||
:: by a third party) even if such damage or loss was
|
||||
:: reasonably foreseeable or Xilinx had been advised of the
|
||||
:: possibility of the same.
|
||||
::
|
||||
:: CRITICAL APPLICATIONS
|
||||
:: Xilinx products are not designed or intended to be fail-
|
||||
:: safe, or for use in any application requiring fail-safe
|
||||
:: performance, such as life-support or safety devices or
|
||||
:: systems, Class III medical devices, nuclear facilities,
|
||||
:: applications related to the deployment of airbags, or any
|
||||
:: other applications that could lead to death, personal
|
||||
:: injury, or severe property or environmental damage
|
||||
:: (individually and collectively, "Critical
|
||||
:: Applications"). Customer assumes the sole risk and
|
||||
:: liability of any use of Xilinx products in Critical
|
||||
:: Applications, subject only to applicable laws and
|
||||
:: regulations governing limitations on product liability.
|
||||
::
|
||||
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
:: PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
rem Clean up the results directory
|
||||
rmdir /S /Q results
|
||||
mkdir results
|
||||
|
||||
rem Synthesize the VHDL Wrapper Files
|
||||
|
||||
#Synthesize the Wrapper Files
|
||||
|
||||
echo 'Synthesizing example design with Synplify'
|
||||
synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx
|
||||
|
||||
|
||||
rem Copy the netlist generated by Coregen
|
||||
echo 'Copying files from the netlist directory to the results directory'
|
||||
copy ..\..\axi64_4k_2clk_fifo.ngc results\
|
||||
|
||||
|
||||
rem Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
copy ..\example_design\axi64_4k_2clk_fifo_exdes.ucf results\
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
|
||||
ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi64_4k_2clk_fifo_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map axi64_4k_2clk_fifo_exdes -o mapped.ncd
|
||||
|
||||
echo 'Running par'
|
||||
par mapped.ncd routed.ncd
|
||||
|
||||
echo 'Running trce'
|
||||
trce -e 10 routed.ncd mapped.pcf -o routed
|
||||
|
||||
echo 'Running design through bitgen'
|
||||
bitgen -w routed -g UnconstrainedPins:Allow
|
||||
|
||||
echo 'Running netgen to create gate level Verilog model'
|
||||
netgen -ofmt verilog -sim -tm axi64_4k_2clk_fifo_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
|
||||
@@ -1,86 +0,0 @@
|
||||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
# Clean up the results directory
|
||||
rm -rf results
|
||||
mkdir results
|
||||
|
||||
#Synthesize the Wrapper Files
|
||||
|
||||
echo 'Synthesizing example design with Synplify'
|
||||
synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx
|
||||
|
||||
|
||||
# Copy the netlist generated by Coregen
|
||||
echo 'Copying files from the netlist directory to the results directory'
|
||||
cp ../../axi64_4k_2clk_fifo.ngc results/
|
||||
|
||||
# Copy the constraints files generated by Coregen
|
||||
echo 'Copying files from constraints directory to results directory'
|
||||
cp ../example_design/axi64_4k_2clk_fifo_exdes.ucf results/
|
||||
|
||||
cd results
|
||||
|
||||
echo 'Running ngdbuild'
|
||||
|
||||
ngdbuild -p xc7k410t-ffg900-2 -sd ../../../ axi64_4k_2clk_fifo_exdes
|
||||
|
||||
echo 'Running map'
|
||||
map axi64_4k_2clk_fifo_exdes -o mapped.ncd
|
||||
|
||||
echo 'Running par'
|
||||
par mapped.ncd routed.ncd
|
||||
|
||||
echo 'Running trce'
|
||||
trce -e 10 routed.ncd mapped.pcf -o routed
|
||||
|
||||
echo 'Running design through bitgen'
|
||||
bitgen -w routed -g UnconstrainedPins:Allow
|
||||
|
||||
echo 'Running netgen to create gate level Verilog model'
|
||||
netgen -ofmt verilog -sim -tm axi64_4k_2clk_fifo_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
|
||||
|
||||
@@ -1,54 +0,0 @@
|
||||
:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
::
|
||||
:: This file contains confidential and proprietary information
|
||||
:: of Xilinx, Inc. and is protected under U.S. and
|
||||
:: international copyright and other intellectual property
|
||||
:: laws.
|
||||
::
|
||||
:: DISCLAIMER
|
||||
:: This disclaimer is not a license and does not grant any
|
||||
:: rights to the materials distributed herewith. Except as
|
||||
:: otherwise provided in a valid license issued to you by
|
||||
:: Xilinx, and to the maximum extent permitted by applicable
|
||||
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
:: (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
:: including negligence, or under any other theory of
|
||||
:: liability) for any loss or damage of any kind or nature
|
||||
:: related to, arising under or in connection with these
|
||||
:: materials, including for any direct, or any indirect,
|
||||
:: special, incidental, or consequential loss or damage
|
||||
:: (including loss of data, profits, goodwill, or any type of
|
||||
:: loss or damage suffered as a result of any action brought
|
||||
:: by a third party) even if such damage or loss was
|
||||
:: reasonably foreseeable or Xilinx had been advised of the
|
||||
:: possibility of the same.
|
||||
::
|
||||
:: CRITICAL APPLICATIONS
|
||||
:: Xilinx products are not designed or intended to be fail-
|
||||
:: safe, or for use in any application requiring fail-safe
|
||||
:: performance, such as life-support or safety devices or
|
||||
:: systems, Class III medical devices, nuclear facilities,
|
||||
:: applications related to the deployment of airbags, or any
|
||||
:: other applications that could lead to death, personal
|
||||
:: injury, or severe property or environmental damage
|
||||
:: (individually and collectively, "Critical
|
||||
:: Applications"). Customer assumes the sole risk and
|
||||
:: liability of any use of Xilinx products in Critical
|
||||
:: Applications, subject only to applicable laws and
|
||||
:: regulations governing limitations on product liability.
|
||||
::
|
||||
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
:: PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
rem -----------------------------------------------------------------------------
|
||||
rem Script to synthesize and implement the Coregen FIFO Generator
|
||||
rem -----------------------------------------------------------------------------
|
||||
rmdir /S /Q results
|
||||
mkdir results
|
||||
cd results
|
||||
copy ..\..\..\axi64_4k_2clk_fifo.ngc .
|
||||
planAhead -mode batch -source ..\planAhead_ise.tcl
|
||||
@@ -1,55 +0,0 @@
|
||||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
#-----------------------------------------------------------------------------
|
||||
# Script to synthesize and implement the Coregen FIFO Generator
|
||||
#-----------------------------------------------------------------------------
|
||||
rm -rf results
|
||||
mkdir results
|
||||
cd results
|
||||
cp ../../../axi64_4k_2clk_fifo.ngc .
|
||||
planAhead -mode batch -source ../planAhead_ise.tcl
|
||||
@@ -1,67 +0,0 @@
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
|
||||
set device xc7k410tffg900-2
|
||||
set projName axi64_4k_2clk_fifo
|
||||
set design axi64_4k_2clk_fifo
|
||||
set projDir [file dirname [info script]]
|
||||
create_project $projName $projDir/results/$projName -part $device -force
|
||||
set_property design_mode RTL [current_fileset -srcset]
|
||||
set top_module axi64_4k_2clk_fifo_exdes
|
||||
add_files -norecurse {../../example_design/axi64_4k_2clk_fifo_exdes.vhd}
|
||||
add_files -norecurse {./axi64_4k_2clk_fifo.ngc}
|
||||
import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/axi64_4k_2clk_fifo_exdes.xdc}
|
||||
set_property top axi64_4k_2clk_fifo_exdes [get_property srcset [current_run]]
|
||||
synth_design
|
||||
opt_design
|
||||
place_design
|
||||
route_design
|
||||
write_sdf -rename_top_module axi64_4k_2clk_fifo_exdes -file routed.sdf
|
||||
write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module axi64_4k_2clk_fifo_exdes routed.v
|
||||
report_timing -nworst 30 -path_type full -file routed.twr
|
||||
report_drc -file report.drc
|
||||
write_bitstream -bitgen_options {-g UnconstrainedPins:Allow}
|
||||
@@ -1 +0,0 @@
|
||||
work ../example_design/axi64_4k_2clk_fifo_exdes.vhd
|
||||
@@ -1,13 +0,0 @@
|
||||
run
|
||||
-ifmt VHDL
|
||||
-ent axi64_4k_2clk_fifo_exdes
|
||||
-p xc7k410t-ffg900-2
|
||||
-ifn xst.prj
|
||||
-write_timing_constraints No
|
||||
-iobuf YES
|
||||
-max_fanout 100
|
||||
-ofn axi64_4k_2clk_fifo_exdes
|
||||
-ofmt NGC
|
||||
-bus_delimiter ()
|
||||
-hierarchy_separator /
|
||||
-case Maintain
|
||||
@@ -1,154 +0,0 @@
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- FIFO Generator Core Demo Testbench
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: axi64_4k_2clk_fifo_dgen.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Used for write interface stimulus generation
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.std_logic_unsigned.all;
|
||||
USE IEEE.std_logic_arith.all;
|
||||
USE IEEE.std_logic_misc.all;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.axi64_4k_2clk_fifo_pkg.ALL;
|
||||
|
||||
ENTITY axi64_4k_2clk_fifo_dgen IS
|
||||
GENERIC (
|
||||
C_DIN_WIDTH : INTEGER := 32;
|
||||
C_DOUT_WIDTH : INTEGER := 32;
|
||||
C_CH_TYPE : INTEGER := 0;
|
||||
TB_SEED : INTEGER := 2
|
||||
);
|
||||
PORT (
|
||||
RESET : IN STD_LOGIC;
|
||||
WR_CLK : IN STD_LOGIC;
|
||||
PRC_WR_EN : IN STD_LOGIC;
|
||||
FULL : IN STD_LOGIC;
|
||||
WR_EN : OUT STD_LOGIC;
|
||||
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
|
||||
);
|
||||
END ENTITY;
|
||||
|
||||
|
||||
ARCHITECTURE fg_dg_arch OF axi64_4k_2clk_fifo_dgen IS
|
||||
|
||||
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
|
||||
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
|
||||
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
|
||||
|
||||
SIGNAL pr_w_en : STD_LOGIC := '0';
|
||||
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
|
||||
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
|
||||
SIGNAL wr_d_sel : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '0');
|
||||
BEGIN
|
||||
|
||||
WR_EN <= PRC_WR_EN ;
|
||||
WR_DATA <= wr_data_i AFTER 100 ns;
|
||||
|
||||
----------------------------------------------
|
||||
-- Generation of DATA
|
||||
----------------------------------------------
|
||||
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
|
||||
rd_gen_inst1:axi64_4k_2clk_fifo_rng
|
||||
GENERIC MAP(
|
||||
WIDTH => 8,
|
||||
SEED => TB_SEED+N
|
||||
)
|
||||
PORT MAP(
|
||||
CLK => WR_CLK,
|
||||
RESET => RESET,
|
||||
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
|
||||
ENABLE => pr_w_en
|
||||
);
|
||||
END GENERATE;
|
||||
|
||||
gen_fifo_stim: IF(C_CH_TYPE /= 2) GENERATE
|
||||
-- DIN_WIDTH < DOUT_WIDTH
|
||||
gen_din_lt_dout: IF(C_DIN_WIDTH < C_DOUT_WIDTH) GENERATE
|
||||
BEGIN
|
||||
pr_w_en <= (AND_REDUCE(wr_d_sel)) AND PRC_WR_EN AND NOT FULL;
|
||||
wr_data_i <= rand_num(C_DOUT_WIDTH-C_DIN_WIDTH*conv_integer(wr_d_sel)-1 DOWNTO C_DOUT_WIDTH-C_DIN_WIDTH*(conv_integer(wr_d_sel)+1));
|
||||
|
||||
PROCESS(WR_CLK,RESET)
|
||||
BEGIN
|
||||
IF(RESET = '1') THEN
|
||||
wr_d_sel <= (OTHERS => '0');
|
||||
ELSIF(WR_CLK'event AND WR_CLK = '1') THEN
|
||||
IF(FULL = '0' AND PRC_WR_EN = '1') THEN
|
||||
wr_d_sel <= wr_d_sel + "1";
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
END GENERATE gen_din_lt_dout;
|
||||
-- DIN_WIDTH >= DOUT_WIDTH
|
||||
gen_din_gteq_dout:IF(C_DIN_WIDTH >= C_DOUT_WIDTH) GENERATE
|
||||
pr_w_en <= PRC_WR_EN AND NOT FULL;
|
||||
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
|
||||
END GENERATE gen_din_gteq_dout;
|
||||
END GENERATE gen_fifo_stim;
|
||||
|
||||
----------------------------------------------
|
||||
-- Wiring logic stimulus generation
|
||||
----------------------------------------------
|
||||
gen_wiring_stim: IF (C_CH_TYPE = 2) GENERATE
|
||||
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
|
||||
pr_w_en <= PRC_WR_EN;
|
||||
END GENERATE gen_wiring_stim;
|
||||
|
||||
END ARCHITECTURE;
|
||||
@@ -1,150 +0,0 @@
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- FIFO Generator Core Demo Testbench
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: axi64_4k_2clk_fifo_dverif.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Used for FIFO read interface stimulus generation and data checking
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.std_logic_unsigned.all;
|
||||
USE IEEE.std_logic_arith.all;
|
||||
USE IEEE.std_logic_misc.all;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.axi64_4k_2clk_fifo_pkg.ALL;
|
||||
|
||||
ENTITY axi64_4k_2clk_fifo_dverif IS
|
||||
GENERIC(
|
||||
C_DIN_WIDTH : INTEGER := 0;
|
||||
C_DOUT_WIDTH : INTEGER := 0;
|
||||
C_USE_EMBEDDED_REG : INTEGER := 0;
|
||||
C_CH_TYPE : INTEGER := 0;
|
||||
TB_SEED : INTEGER := 2
|
||||
);
|
||||
PORT(
|
||||
RESET : IN STD_LOGIC;
|
||||
RD_CLK : IN STD_LOGIC;
|
||||
PRC_RD_EN : IN STD_LOGIC;
|
||||
EMPTY : IN STD_LOGIC;
|
||||
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
|
||||
RD_EN : OUT STD_LOGIC;
|
||||
DOUT_CHK : OUT STD_LOGIC
|
||||
);
|
||||
END ENTITY;
|
||||
|
||||
|
||||
ARCHITECTURE fg_dv_arch OF axi64_4k_2clk_fifo_dverif IS
|
||||
|
||||
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
|
||||
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
|
||||
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
|
||||
|
||||
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL data_chk : STD_LOGIC := '1';
|
||||
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
|
||||
SIGNAL rd_en_i : STD_LOGIC := '0';
|
||||
SIGNAL pr_r_en : STD_LOGIC := '0';
|
||||
SIGNAL rd_en_d1 : STD_LOGIC := '1';
|
||||
BEGIN
|
||||
|
||||
|
||||
DOUT_CHK <= data_chk;
|
||||
RD_EN <= rd_en_i;
|
||||
rd_en_i <= PRC_RD_EN;
|
||||
rd_en_d1 <= '1';
|
||||
|
||||
|
||||
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
|
||||
-------------------------------------------------------
|
||||
-- Expected data generation and checking for data_fifo
|
||||
-------------------------------------------------------
|
||||
|
||||
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
|
||||
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
|
||||
|
||||
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
|
||||
rd_gen_inst2:axi64_4k_2clk_fifo_rng
|
||||
GENERIC MAP(
|
||||
WIDTH => 8,
|
||||
SEED => TB_SEED+N
|
||||
)
|
||||
PORT MAP(
|
||||
CLK => RD_CLK,
|
||||
RESET => RESET,
|
||||
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
|
||||
ENABLE => pr_r_en
|
||||
);
|
||||
END GENERATE;
|
||||
|
||||
PROCESS (RD_CLK,RESET)
|
||||
BEGIN
|
||||
IF(RESET = '1') THEN
|
||||
data_chk <= '0';
|
||||
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
|
||||
IF(EMPTY = '0') THEN
|
||||
IF(DATA_OUT = expected_dout) THEN
|
||||
data_chk <= '0';
|
||||
ELSE
|
||||
data_chk <= '1';
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
END GENERATE data_fifo_chk;
|
||||
|
||||
END ARCHITECTURE;
|
||||
@@ -1,602 +0,0 @@
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- FIFO Generator Core Demo Testbench
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: axi64_4k_2clk_fifo_pctrl.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Used for protocol control on write and read interface stimulus and status generation
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.std_logic_unsigned.all;
|
||||
USE IEEE.std_logic_arith.all;
|
||||
USE IEEE.std_logic_misc.all;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.axi64_4k_2clk_fifo_pkg.ALL;
|
||||
|
||||
ENTITY axi64_4k_2clk_fifo_pctrl IS
|
||||
GENERIC(
|
||||
AXI_CHANNEL : STRING :="NONE";
|
||||
C_APPLICATION_TYPE : INTEGER := 0;
|
||||
C_DIN_WIDTH : INTEGER := 0;
|
||||
C_DOUT_WIDTH : INTEGER := 0;
|
||||
C_WR_PNTR_WIDTH : INTEGER := 0;
|
||||
C_RD_PNTR_WIDTH : INTEGER := 0;
|
||||
C_CH_TYPE : INTEGER := 0;
|
||||
FREEZEON_ERROR : INTEGER := 0;
|
||||
TB_STOP_CNT : INTEGER := 2;
|
||||
TB_SEED : INTEGER := 2
|
||||
);
|
||||
PORT(
|
||||
RESET_WR : IN STD_LOGIC;
|
||||
RESET_RD : IN STD_LOGIC;
|
||||
WR_CLK : IN STD_LOGIC;
|
||||
RD_CLK : IN STD_LOGIC;
|
||||
FULL : IN STD_LOGIC;
|
||||
EMPTY : IN STD_LOGIC;
|
||||
ALMOST_FULL : IN STD_LOGIC;
|
||||
ALMOST_EMPTY : IN STD_LOGIC;
|
||||
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
|
||||
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
|
||||
DOUT_CHK : IN STD_LOGIC;
|
||||
PRC_WR_EN : OUT STD_LOGIC;
|
||||
PRC_RD_EN : OUT STD_LOGIC;
|
||||
RESET_EN : OUT STD_LOGIC;
|
||||
SIM_DONE : OUT STD_LOGIC;
|
||||
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
|
||||
);
|
||||
END ENTITY;
|
||||
|
||||
|
||||
ARCHITECTURE fg_pc_arch OF axi64_4k_2clk_fifo_pctrl IS
|
||||
|
||||
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
|
||||
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
|
||||
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
|
||||
|
||||
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
|
||||
SIGNAL data_chk_wr : STD_LOGIC := '0';
|
||||
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
|
||||
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
|
||||
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
|
||||
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
|
||||
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
|
||||
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
|
||||
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
|
||||
SIGNAL wr_en_i : STD_LOGIC := '0';
|
||||
SIGNAL rd_en_i : STD_LOGIC := '0';
|
||||
SIGNAL state : STD_LOGIC := '0';
|
||||
SIGNAL wr_control : STD_LOGIC := '0';
|
||||
SIGNAL rd_control : STD_LOGIC := '0';
|
||||
SIGNAL stop_on_err : STD_LOGIC := '0';
|
||||
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
|
||||
SIGNAL sim_done_i : STD_LOGIC := '0';
|
||||
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
|
||||
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
|
||||
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
|
||||
SIGNAL prc_we_i : STD_LOGIC := '0';
|
||||
SIGNAL prc_re_i : STD_LOGIC := '0';
|
||||
SIGNAL reset_en_i : STD_LOGIC := '0';
|
||||
SIGNAL sim_done_d1 : STD_LOGIC := '0';
|
||||
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
|
||||
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
|
||||
SIGNAL empty_d1 : STD_LOGIC := '0';
|
||||
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
|
||||
SIGNAL state_d1 : STD_LOGIC := '0';
|
||||
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
|
||||
SIGNAL rd_en_d1 : STD_LOGIC := '0';
|
||||
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
|
||||
SIGNAL wr_en_d1 : STD_LOGIC := '0';
|
||||
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
|
||||
SIGNAL full_chk_d1 : STD_LOGIC := '0';
|
||||
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
|
||||
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
|
||||
|
||||
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
|
||||
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
|
||||
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
|
||||
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
|
||||
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
|
||||
SIGNAL reset_en_d1 : STD_LOGIC := '0';
|
||||
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
|
||||
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
|
||||
|
||||
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
|
||||
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
|
||||
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
|
||||
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
|
||||
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
|
||||
BEGIN
|
||||
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
|
||||
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
|
||||
|
||||
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
|
||||
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
|
||||
|
||||
SIM_DONE <= sim_done_i;
|
||||
rdw_gt_wrw <= (OTHERS => '1');
|
||||
wrw_gt_rdw <= (OTHERS => '1');
|
||||
|
||||
PROCESS(RD_CLK)
|
||||
BEGIN
|
||||
IF (RD_CLK'event AND RD_CLK='1') THEN
|
||||
IF(prc_re_i = '1') THEN
|
||||
rd_activ_cont <= rd_activ_cont + "1";
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
PROCESS(sim_done_i)
|
||||
BEGIN
|
||||
assert sim_done_i = '0'
|
||||
report "Simulation Complete for:" & AXI_CHANNEL
|
||||
severity note;
|
||||
END PROCESS;
|
||||
|
||||
-----------------------------------------------------
|
||||
-- SIM_DONE SIGNAL GENERATION
|
||||
-----------------------------------------------------
|
||||
PROCESS (RD_CLK,RESET_RD)
|
||||
BEGIN
|
||||
IF(RESET_RD = '1') THEN
|
||||
--sim_done_i <= '0';
|
||||
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
|
||||
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
|
||||
sim_done_i <= '1';
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
-- TB Timeout/Stop
|
||||
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0 AND C_CH_TYPE /= 2) GENERATE
|
||||
PROCESS (RD_CLK)
|
||||
BEGIN
|
||||
IF (RD_CLK'event AND RD_CLK='1') THEN
|
||||
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
|
||||
sim_stop_cntr <= sim_stop_cntr - "1";
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
END GENERATE fifo_tb_stop_run;
|
||||
|
||||
pwr_tb_stop_run:IF(C_CH_TYPE = 2) GENERATE
|
||||
PROCESS (RD_CLK)
|
||||
BEGIN
|
||||
IF (RD_CLK'event AND RD_CLK='1') THEN
|
||||
IF(prc_re_i = '1') THEN
|
||||
sim_stop_cntr <= sim_stop_cntr - "1";
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
END GENERATE pwr_tb_stop_run;
|
||||
|
||||
-- Stop when error found
|
||||
PROCESS (RD_CLK)
|
||||
BEGIN
|
||||
IF (RD_CLK'event AND RD_CLK='1') THEN
|
||||
IF(sim_done_i = '0') THEN
|
||||
status_d1_i <= status_i OR status_d1_i;
|
||||
END IF;
|
||||
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
|
||||
stop_on_err <= '1';
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
-----------------------------------------------------
|
||||
|
||||
-----------------------------------------------------
|
||||
-- CHECKS FOR FIFO
|
||||
-----------------------------------------------------
|
||||
|
||||
fifo_flags_checks:IF(C_CH_TYPE /= 2) GENERATE
|
||||
|
||||
PROCESS(RD_CLK,RESET_RD)
|
||||
BEGIN
|
||||
IF(RESET_RD = '1') THEN
|
||||
post_rst_dly_rd <= (OTHERS => '1');
|
||||
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
|
||||
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(WR_CLK,RESET_WR)
|
||||
BEGIN
|
||||
IF(RESET_WR = '1') THEN
|
||||
post_rst_dly_wr <= (OTHERS => '1');
|
||||
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
|
||||
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
-- FULL de-assert Counter
|
||||
PROCESS(WR_CLK,RESET_WR)
|
||||
BEGIN
|
||||
IF(RESET_WR = '1') THEN
|
||||
full_ds_timeout <= (OTHERS => '0');
|
||||
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
|
||||
IF(state = '1') THEN
|
||||
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
|
||||
full_ds_timeout <= full_ds_timeout + '1';
|
||||
END IF;
|
||||
ELSE
|
||||
full_ds_timeout <= (OTHERS => '0');
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
-- EMPTY deassert counter
|
||||
PROCESS(RD_CLK,RESET_RD)
|
||||
BEGIN
|
||||
IF(RESET_RD = '1') THEN
|
||||
empty_ds_timeout <= (OTHERS => '0');
|
||||
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
|
||||
IF(state = '0') THEN
|
||||
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
|
||||
empty_ds_timeout <= empty_ds_timeout + '1';
|
||||
END IF;
|
||||
ELSE
|
||||
empty_ds_timeout <= (OTHERS => '0');
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
-- Full check signal generation
|
||||
PROCESS(WR_CLK,RESET_WR)
|
||||
BEGIN
|
||||
IF(RESET_WR = '1') THEN
|
||||
full_chk_i <= '0';
|
||||
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
|
||||
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
|
||||
full_chk_i <= '0';
|
||||
ELSE
|
||||
full_chk_i <= AND_REDUCE(full_as_timeout) OR
|
||||
AND_REDUCE(full_ds_timeout);
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
-- Empty checks
|
||||
PROCESS(RD_CLK,RESET_RD)
|
||||
BEGIN
|
||||
IF(RESET_RD = '1') THEN
|
||||
empty_chk_i <= '0';
|
||||
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
|
||||
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
|
||||
empty_chk_i <= '0';
|
||||
ELSE
|
||||
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
|
||||
AND_REDUCE(empty_ds_timeout);
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
END GENERATE fifo_flags_checks;
|
||||
|
||||
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
|
||||
PRC_WR_EN <= prc_we_i AFTER 100 ns;
|
||||
PRC_RD_EN <= prc_re_i AFTER 50 ns;
|
||||
data_chk_i <= dout_chk;
|
||||
END GENERATE fifo_d_chk;
|
||||
-----------------------------------------------------
|
||||
|
||||
-----------------------------------------------------
|
||||
-- Wiring logic data checks
|
||||
-----------------------------------------------------
|
||||
wiring_d_chk:IF(C_CH_TYPE = 2) GENERATE
|
||||
PROCESS(WR_CLK,RESET_WR)
|
||||
BEGIN
|
||||
IF(RESET_WR = '1') THEN
|
||||
data_chk_wr <= '0';
|
||||
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
|
||||
IF ((DATA_OUT = DATA_IN) AND (FULL = NOT rd_en_i) AND (EMPTY = NOT wr_en_i)) THEN
|
||||
data_chk_wr <= '0';
|
||||
ELSE
|
||||
data_chk_wr <= '1';
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
data_chk_i <= data_chk_rd2;
|
||||
PRC_WR_EN <= prc_we_i AFTER 100 ns;
|
||||
PRC_RD_EN <= prc_re_i AFTER 50 ns;
|
||||
END GENERATE wiring_d_chk;
|
||||
|
||||
|
||||
-----------------------------------------------------
|
||||
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
|
||||
-----------------------------------------------------
|
||||
PROCESS(WR_CLK,RESET_WR)
|
||||
BEGIN
|
||||
IF(RESET_WR = '1') THEN
|
||||
empty_wr_dom1 <= '1';
|
||||
empty_wr_dom2 <= '1';
|
||||
state_d1 <= '0';
|
||||
wr_en_d1 <= '0';
|
||||
rd_en_wr1 <= '0';
|
||||
rd_en_wr2 <= '0';
|
||||
full_chk_d1 <= '0';
|
||||
reset_en_d1 <= '0';
|
||||
data_chk_wr_d1 <= '0';
|
||||
sim_done_wr1 <= '0';
|
||||
sim_done_wr2 <= '0';
|
||||
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
|
||||
sim_done_wr1 <= sim_done_d1;
|
||||
sim_done_wr2 <= sim_done_wr1;
|
||||
data_chk_wr_d1 <= data_chk_wr;
|
||||
reset_en_d1 <= reset_en_i;
|
||||
state_d1 <= state;
|
||||
empty_wr_dom1 <= empty_d1;
|
||||
empty_wr_dom2 <= empty_wr_dom1;
|
||||
wr_en_d1 <= wr_en_i;
|
||||
rd_en_wr1 <= rd_en_d1;
|
||||
rd_en_wr2 <= rd_en_wr1;
|
||||
full_chk_d1 <= full_chk_i;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(RD_CLK,RESET_RD)
|
||||
BEGIN
|
||||
IF(RESET_RD = '1') THEN
|
||||
empty_d1 <= '1';
|
||||
state_rd_dom1 <= '0';
|
||||
state_rd_dom2 <= '0';
|
||||
state_rd_dom3 <= '0';
|
||||
wr_en_rd1 <= '0';
|
||||
wr_en_rd2 <= '0';
|
||||
rd_en_d1 <= '0';
|
||||
full_chk_rd1 <= '0';
|
||||
full_chk_rd2 <= '0';
|
||||
reset_en_rd1 <= '0';
|
||||
reset_en_rd2 <= '0';
|
||||
data_chk_rd1 <= '0';
|
||||
data_chk_rd2 <= '0';
|
||||
sim_done_d1 <= '0';
|
||||
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
|
||||
sim_done_d1 <= sim_done_i;
|
||||
data_chk_rd1 <= data_chk_wr_d1;
|
||||
data_chk_rd2 <= data_chk_rd1;
|
||||
reset_en_rd1 <= reset_en_d1;
|
||||
reset_en_rd2 <= reset_en_rd1;
|
||||
empty_d1 <= EMPTY;
|
||||
rd_en_d1 <= rd_en_i;
|
||||
state_rd_dom1 <= state_d1;
|
||||
state_rd_dom2 <= state_rd_dom1;
|
||||
state_rd_dom3 <= state_rd_dom2;
|
||||
wr_en_rd1 <= wr_en_d1;
|
||||
wr_en_rd2 <= wr_en_rd1;
|
||||
full_chk_rd1 <= full_chk_d1;
|
||||
full_chk_rd2 <= full_chk_rd1;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
RESET_EN <= reset_en_rd2;
|
||||
|
||||
|
||||
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
|
||||
-----------------------------------------------------
|
||||
-- WR_EN GENERATION
|
||||
-----------------------------------------------------
|
||||
gen_rand_wr_en:axi64_4k_2clk_fifo_rng
|
||||
GENERIC MAP(
|
||||
WIDTH => 8,
|
||||
SEED => TB_SEED+1
|
||||
)
|
||||
PORT MAP(
|
||||
CLK => WR_CLK,
|
||||
RESET => RESET_WR,
|
||||
RANDOM_NUM => wr_en_gen,
|
||||
ENABLE => '1'
|
||||
);
|
||||
|
||||
PROCESS(WR_CLK,RESET_WR)
|
||||
BEGIN
|
||||
IF(RESET_WR = '1') THEN
|
||||
wr_en_i <= '0';
|
||||
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
|
||||
IF(state = '1') THEN
|
||||
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
|
||||
ELSE
|
||||
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
-----------------------------------------------------
|
||||
-- WR_EN CONTROL
|
||||
-----------------------------------------------------
|
||||
PROCESS(WR_CLK,RESET_WR)
|
||||
BEGIN
|
||||
IF(RESET_WR = '1') THEN
|
||||
wr_cntr <= (OTHERS => '0');
|
||||
wr_control <= '1';
|
||||
full_as_timeout <= (OTHERS => '0');
|
||||
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
|
||||
IF(state = '1') THEN
|
||||
IF(wr_en_i = '1') THEN
|
||||
wr_cntr <= wr_cntr + "1";
|
||||
END IF;
|
||||
full_as_timeout <= (OTHERS => '0');
|
||||
ELSE
|
||||
wr_cntr <= (OTHERS => '0');
|
||||
IF(rd_en_wr2 = '0') THEN
|
||||
IF(wr_en_i = '1') THEN
|
||||
full_as_timeout <= full_as_timeout + "1";
|
||||
END IF;
|
||||
ELSE
|
||||
full_as_timeout <= (OTHERS => '0');
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
wr_control <= NOT wr_cntr(wr_cntr'high);
|
||||
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
-----------------------------------------------------
|
||||
-- RD_EN GENERATION
|
||||
-----------------------------------------------------
|
||||
gen_rand_rd_en:axi64_4k_2clk_fifo_rng
|
||||
GENERIC MAP(
|
||||
WIDTH => 8,
|
||||
SEED => TB_SEED
|
||||
)
|
||||
PORT MAP(
|
||||
CLK => RD_CLK,
|
||||
RESET => RESET_RD,
|
||||
RANDOM_NUM => rd_en_gen,
|
||||
ENABLE => '1'
|
||||
);
|
||||
|
||||
PROCESS(RD_CLK,RESET_RD)
|
||||
BEGIN
|
||||
IF(RESET_RD = '1') THEN
|
||||
rd_en_i <= '0';
|
||||
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
|
||||
IF(state_rd_dom2 = '0') THEN
|
||||
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
|
||||
ELSE
|
||||
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
-----------------------------------------------------
|
||||
-- RD_EN CONTROL
|
||||
-----------------------------------------------------
|
||||
PROCESS(RD_CLK,RESET_RD)
|
||||
BEGIN
|
||||
IF(RESET_RD = '1') THEN
|
||||
rd_cntr <= (OTHERS => '0');
|
||||
rd_control <= '1';
|
||||
empty_as_timeout <= (OTHERS => '0');
|
||||
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
|
||||
IF(state_rd_dom2 = '0') THEN
|
||||
IF(rd_en_i = '1') THEN
|
||||
rd_cntr <= rd_cntr + "1";
|
||||
END IF;
|
||||
empty_as_timeout <= (OTHERS => '0');
|
||||
ELSE
|
||||
rd_cntr <= (OTHERS => '0');
|
||||
IF(wr_en_rd2 = '0') THEN
|
||||
IF(rd_en_i = '1') THEN
|
||||
empty_as_timeout <= empty_as_timeout + "1";
|
||||
END IF;
|
||||
ELSE
|
||||
empty_as_timeout <= (OTHERS => '0');
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
rd_control <= NOT rd_cntr(rd_cntr'high);
|
||||
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
-----------------------------------------------------
|
||||
-- STIMULUS CONTROL
|
||||
-----------------------------------------------------
|
||||
PROCESS(WR_CLK,RESET_WR)
|
||||
BEGIN
|
||||
IF(RESET_WR = '1') THEN
|
||||
state <= '0';
|
||||
reset_en_i <= '0';
|
||||
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
|
||||
CASE state IS
|
||||
WHEN '0' =>
|
||||
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
|
||||
state <= '1';
|
||||
reset_en_i <= '0';
|
||||
END IF;
|
||||
WHEN '1' =>
|
||||
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
|
||||
state <= '0';
|
||||
reset_en_i <= '1';
|
||||
END IF;
|
||||
WHEN OTHERS => state <= state;
|
||||
END CASE;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
END GENERATE data_fifo_en;
|
||||
|
||||
-----------------------------------------------------
|
||||
-- Wiring logic enable generation
|
||||
-----------------------------------------------------
|
||||
axi_pw_enable:IF(C_CH_TYPE = 2) GENERATE
|
||||
RESET_EN <= '1';
|
||||
|
||||
PROCESS(WR_CLK)
|
||||
BEGIN
|
||||
IF (WR_CLK'event AND WR_CLK='1') THEN
|
||||
wr_en_i <= NOT wr_en_i;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(RD_CLK)
|
||||
BEGIN
|
||||
IF (RD_CLK'event AND RD_CLK='1') THEN
|
||||
rd_en_i <= NOT rd_en_i;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
END GENERATE axi_pw_enable;
|
||||
|
||||
END ARCHITECTURE;
|
||||
@@ -1,354 +0,0 @@
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- FIFO Generator Core Demo Testbench
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: axi64_4k_2clk_fifo_pkg.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- This is the demo testbench package file for FIFO Generator core.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.std_logic_arith.ALL;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
PACKAGE axi64_4k_2clk_fifo_pkg IS
|
||||
|
||||
FUNCTION divroundup (
|
||||
data_value : INTEGER;
|
||||
divisor : INTEGER)
|
||||
RETURN INTEGER;
|
||||
------------------------
|
||||
FUNCTION if_then_else (
|
||||
condition : BOOLEAN;
|
||||
true_case : INTEGER;
|
||||
false_case : INTEGER)
|
||||
RETURN INTEGER;
|
||||
------------------------
|
||||
FUNCTION if_then_else (
|
||||
condition : BOOLEAN;
|
||||
true_case : STD_LOGIC;
|
||||
false_case : STD_LOGIC)
|
||||
RETURN STD_LOGIC;
|
||||
------------------------
|
||||
FUNCTION if_then_else (
|
||||
condition : BOOLEAN;
|
||||
true_case : TIME;
|
||||
false_case : TIME)
|
||||
RETURN TIME;
|
||||
------------------------
|
||||
FUNCTION log2roundup (
|
||||
data_value : INTEGER)
|
||||
RETURN INTEGER;
|
||||
------------------------
|
||||
FUNCTION hexstr_to_std_logic_vec(
|
||||
arg1 : string;
|
||||
size : integer )
|
||||
RETURN std_logic_vector;
|
||||
------------------------
|
||||
COMPONENT axi64_4k_2clk_fifo_rng IS
|
||||
GENERIC (WIDTH : integer := 8;
|
||||
SEED : integer := 3);
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESET : IN STD_LOGIC;
|
||||
ENABLE : IN STD_LOGIC;
|
||||
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
------------------------
|
||||
|
||||
COMPONENT axi64_4k_2clk_fifo_dgen IS
|
||||
GENERIC (
|
||||
C_DIN_WIDTH : INTEGER := 32;
|
||||
C_DOUT_WIDTH : INTEGER := 32;
|
||||
C_CH_TYPE : INTEGER := 0;
|
||||
TB_SEED : INTEGER := 2
|
||||
);
|
||||
PORT (
|
||||
RESET : IN STD_LOGIC;
|
||||
WR_CLK : IN STD_LOGIC;
|
||||
PRC_WR_EN : IN STD_LOGIC;
|
||||
FULL : IN STD_LOGIC;
|
||||
WR_EN : OUT STD_LOGIC;
|
||||
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
------------------------
|
||||
|
||||
COMPONENT axi64_4k_2clk_fifo_dverif IS
|
||||
GENERIC(
|
||||
C_DIN_WIDTH : INTEGER := 0;
|
||||
C_DOUT_WIDTH : INTEGER := 0;
|
||||
C_USE_EMBEDDED_REG : INTEGER := 0;
|
||||
C_CH_TYPE : INTEGER := 0;
|
||||
TB_SEED : INTEGER := 2
|
||||
);
|
||||
PORT(
|
||||
RESET : IN STD_LOGIC;
|
||||
RD_CLK : IN STD_LOGIC;
|
||||
PRC_RD_EN : IN STD_LOGIC;
|
||||
EMPTY : IN STD_LOGIC;
|
||||
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
|
||||
RD_EN : OUT STD_LOGIC;
|
||||
DOUT_CHK : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
------------------------
|
||||
|
||||
COMPONENT axi64_4k_2clk_fifo_pctrl IS
|
||||
GENERIC(
|
||||
AXI_CHANNEL : STRING := "NONE";
|
||||
C_APPLICATION_TYPE : INTEGER := 0;
|
||||
C_DIN_WIDTH : INTEGER := 0;
|
||||
C_DOUT_WIDTH : INTEGER := 0;
|
||||
C_WR_PNTR_WIDTH : INTEGER := 0;
|
||||
C_RD_PNTR_WIDTH : INTEGER := 0;
|
||||
C_CH_TYPE : INTEGER := 0;
|
||||
FREEZEON_ERROR : INTEGER := 0;
|
||||
TB_STOP_CNT : INTEGER := 2;
|
||||
TB_SEED : INTEGER := 2
|
||||
);
|
||||
PORT(
|
||||
RESET_WR : IN STD_LOGIC;
|
||||
RESET_RD : IN STD_LOGIC;
|
||||
WR_CLK : IN STD_LOGIC;
|
||||
RD_CLK : IN STD_LOGIC;
|
||||
FULL : IN STD_LOGIC;
|
||||
EMPTY : IN STD_LOGIC;
|
||||
ALMOST_FULL : IN STD_LOGIC;
|
||||
ALMOST_EMPTY : IN STD_LOGIC;
|
||||
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
|
||||
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
|
||||
DOUT_CHK : IN STD_LOGIC;
|
||||
PRC_WR_EN : OUT STD_LOGIC;
|
||||
PRC_RD_EN : OUT STD_LOGIC;
|
||||
RESET_EN : OUT STD_LOGIC;
|
||||
SIM_DONE : OUT STD_LOGIC;
|
||||
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
------------------------
|
||||
COMPONENT axi64_4k_2clk_fifo_synth IS
|
||||
GENERIC(
|
||||
FREEZEON_ERROR : INTEGER := 0;
|
||||
TB_STOP_CNT : INTEGER := 0;
|
||||
TB_SEED : INTEGER := 1
|
||||
);
|
||||
PORT(
|
||||
S_ACLK : IN STD_LOGIC;
|
||||
M_ACLK : IN STD_LOGIC;
|
||||
RESET : IN STD_LOGIC;
|
||||
SIM_DONE : OUT STD_LOGIC;
|
||||
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
------------------------
|
||||
COMPONENT axi64_4k_2clk_fifo_exdes IS
|
||||
PORT (
|
||||
S_ARESETN : IN std_logic;
|
||||
M_AXIS_TVALID : OUT std_logic;
|
||||
M_AXIS_TREADY : IN std_logic;
|
||||
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
|
||||
M_AXIS_TLAST : OUT std_logic;
|
||||
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
|
||||
S_AXIS_TVALID : IN std_logic;
|
||||
S_AXIS_TREADY : OUT std_logic;
|
||||
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
|
||||
S_AXIS_TLAST : IN std_logic;
|
||||
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
|
||||
AXIS_WR_DATA_COUNT : OUT std_logic_vector(9 DOWNTO 0);
|
||||
AXIS_RD_DATA_COUNT : OUT std_logic_vector(9 DOWNTO 0);
|
||||
M_ACLK : IN std_logic;
|
||||
S_ACLK : IN std_logic);
|
||||
|
||||
END COMPONENT;
|
||||
------------------------
|
||||
|
||||
|
||||
END axi64_4k_2clk_fifo_pkg;
|
||||
|
||||
|
||||
|
||||
PACKAGE BODY axi64_4k_2clk_fifo_pkg IS
|
||||
|
||||
FUNCTION divroundup (
|
||||
data_value : INTEGER;
|
||||
divisor : INTEGER)
|
||||
RETURN INTEGER IS
|
||||
VARIABLE div : INTEGER;
|
||||
BEGIN
|
||||
div := data_value/divisor;
|
||||
IF ( (data_value MOD divisor) /= 0) THEN
|
||||
div := div+1;
|
||||
END IF;
|
||||
RETURN div;
|
||||
END divroundup;
|
||||
---------------------------------
|
||||
FUNCTION if_then_else (
|
||||
condition : BOOLEAN;
|
||||
true_case : INTEGER;
|
||||
false_case : INTEGER)
|
||||
RETURN INTEGER IS
|
||||
VARIABLE retval : INTEGER := 0;
|
||||
BEGIN
|
||||
IF condition=false THEN
|
||||
retval:=false_case;
|
||||
ELSE
|
||||
retval:=true_case;
|
||||
END IF;
|
||||
RETURN retval;
|
||||
END if_then_else;
|
||||
---------------------------------
|
||||
FUNCTION if_then_else (
|
||||
condition : BOOLEAN;
|
||||
true_case : STD_LOGIC;
|
||||
false_case : STD_LOGIC)
|
||||
RETURN STD_LOGIC IS
|
||||
VARIABLE retval : STD_LOGIC := '0';
|
||||
BEGIN
|
||||
IF condition=false THEN
|
||||
retval:=false_case;
|
||||
ELSE
|
||||
retval:=true_case;
|
||||
END IF;
|
||||
RETURN retval;
|
||||
END if_then_else;
|
||||
---------------------------------
|
||||
FUNCTION if_then_else (
|
||||
condition : BOOLEAN;
|
||||
true_case : TIME;
|
||||
false_case : TIME)
|
||||
RETURN TIME IS
|
||||
VARIABLE retval : TIME := 0 ps;
|
||||
BEGIN
|
||||
IF condition=false THEN
|
||||
retval:=false_case;
|
||||
ELSE
|
||||
retval:=true_case;
|
||||
END IF;
|
||||
RETURN retval;
|
||||
END if_then_else;
|
||||
-------------------------------
|
||||
FUNCTION log2roundup (
|
||||
data_value : INTEGER)
|
||||
RETURN INTEGER IS
|
||||
|
||||
VARIABLE width : INTEGER := 0;
|
||||
VARIABLE cnt : INTEGER := 1;
|
||||
BEGIN
|
||||
IF (data_value <= 1) THEN
|
||||
width := 1;
|
||||
ELSE
|
||||
WHILE (cnt < data_value) LOOP
|
||||
width := width + 1;
|
||||
cnt := cnt *2;
|
||||
END LOOP;
|
||||
END IF;
|
||||
|
||||
RETURN width;
|
||||
END log2roundup;
|
||||
------------------------------------------------------------------------------
|
||||
-- hexstr_to_std_logic_vec
|
||||
-- This function converts a hex string to a std_logic_vector
|
||||
------------------------------------------------------------------------------
|
||||
FUNCTION hexstr_to_std_logic_vec(
|
||||
arg1 : string;
|
||||
size : integer )
|
||||
RETURN std_logic_vector IS
|
||||
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
|
||||
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
|
||||
VARIABLE index : integer := 0;
|
||||
BEGIN
|
||||
FOR i IN arg1'reverse_range LOOP
|
||||
CASE arg1(i) IS
|
||||
WHEN '0' => bin := (OTHERS => '0');
|
||||
WHEN '1' => bin := (0 => '1', OTHERS => '0');
|
||||
WHEN '2' => bin := (1 => '1', OTHERS => '0');
|
||||
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
|
||||
WHEN '4' => bin := (2 => '1', OTHERS => '0');
|
||||
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
|
||||
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
|
||||
WHEN '7' => bin := (3 => '0', OTHERS => '1');
|
||||
WHEN '8' => bin := (3 => '1', OTHERS => '0');
|
||||
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
|
||||
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
|
||||
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
|
||||
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
|
||||
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
|
||||
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
|
||||
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
|
||||
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
|
||||
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
|
||||
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
|
||||
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
|
||||
WHEN 'F' => bin := (OTHERS => '1');
|
||||
WHEN 'f' => bin := (OTHERS => '1');
|
||||
WHEN OTHERS =>
|
||||
FOR j IN 0 TO 3 LOOP
|
||||
bin(j) := 'X';
|
||||
END LOOP;
|
||||
END CASE;
|
||||
FOR j IN 0 TO 3 LOOP
|
||||
IF (index*4)+j < size THEN
|
||||
result((index*4)+j) := bin(j);
|
||||
END IF;
|
||||
END LOOP;
|
||||
index := index + 1;
|
||||
END LOOP;
|
||||
RETURN result;
|
||||
END hexstr_to_std_logic_vec;
|
||||
|
||||
END axi64_4k_2clk_fifo_pkg;
|
||||
@@ -1,100 +0,0 @@
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- FIFO Generator Core Demo Testbench
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: axi64_4k_2clk_fifo_rng.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- Used for generation of pseudo random numbers
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.std_logic_unsigned.all;
|
||||
USE IEEE.std_logic_arith.all;
|
||||
USE IEEE.std_logic_misc.all;
|
||||
|
||||
ENTITY axi64_4k_2clk_fifo_rng IS
|
||||
GENERIC (
|
||||
WIDTH : integer := 8;
|
||||
SEED : integer := 3);
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
RESET : IN STD_LOGIC;
|
||||
ENABLE : IN STD_LOGIC;
|
||||
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
|
||||
END ENTITY;
|
||||
|
||||
ARCHITECTURE rg_arch OF axi64_4k_2clk_fifo_rng IS
|
||||
BEGIN
|
||||
PROCESS (CLK,RESET)
|
||||
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
|
||||
VARIABLE temp : STD_LOGIC := '0';
|
||||
BEGIN
|
||||
IF(RESET = '1') THEN
|
||||
rand_temp := conv_std_logic_vector(SEED,width);
|
||||
temp := '0';
|
||||
ELSIF (CLK'event AND CLK = '1') THEN
|
||||
IF (ENABLE = '1') THEN
|
||||
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
|
||||
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
|
||||
rand_temp(0) := temp;
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
RANDOM_NUM <= rand_temp;
|
||||
|
||||
END PROCESS;
|
||||
|
||||
END ARCHITECTURE;
|
||||
@@ -1,317 +0,0 @@
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- FIFO Generator Core Demo Testbench
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: axi64_4k_2clk_fifo_synth.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- This is the demo testbench for fifo_generator core.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.STD_LOGIC_1164.ALL;
|
||||
USE ieee.STD_LOGIC_unsigned.ALL;
|
||||
USE IEEE.STD_LOGIC_arith.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
USE ieee.STD_LOGIC_misc.ALL;
|
||||
|
||||
LIBRARY std;
|
||||
USE std.textio.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.axi64_4k_2clk_fifo_pkg.ALL;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Entity Declaration
|
||||
--------------------------------------------------------------------------------
|
||||
ENTITY axi64_4k_2clk_fifo_synth IS
|
||||
GENERIC(
|
||||
FREEZEON_ERROR : INTEGER := 0;
|
||||
TB_STOP_CNT : INTEGER := 0;
|
||||
TB_SEED : INTEGER := 1
|
||||
);
|
||||
PORT(
|
||||
S_ACLK : IN STD_LOGIC;
|
||||
M_ACLK : IN STD_LOGIC;
|
||||
RESET : IN STD_LOGIC;
|
||||
SIM_DONE : OUT STD_LOGIC;
|
||||
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
|
||||
);
|
||||
END ENTITY;
|
||||
|
||||
ARCHITECTURE simulation_arch OF axi64_4k_2clk_fifo_synth IS
|
||||
CONSTANT TDATA_OFFSET : INTEGER := if_then_else(1 = 1,69-64,69);
|
||||
CONSTANT TSTRB_OFFSET : INTEGER := if_then_else(0 = 1,TDATA_OFFSET-8,TDATA_OFFSET);
|
||||
CONSTANT TKEEP_OFFSET : INTEGER := if_then_else(0 = 1,TSTRB_OFFSET-8,TSTRB_OFFSET);
|
||||
CONSTANT TID_OFFSET : INTEGER := if_then_else(0 = 1,TKEEP_OFFSET-8,TKEEP_OFFSET);
|
||||
CONSTANT TDEST_OFFSET : INTEGER := if_then_else(0 = 1,TID_OFFSET-4,TID_OFFSET);
|
||||
CONSTANT TLAST_OFFSET : INTEGER := if_then_else(1 = 1,TDEST_OFFSET-4,TDEST_OFFSET);
|
||||
|
||||
-- FIFO interface signal declarations
|
||||
SIGNAL s_aresetn : STD_LOGIC;
|
||||
SIGNAL m_axis_tvalid : STD_LOGIC;
|
||||
SIGNAL m_axis_tready : STD_LOGIC;
|
||||
SIGNAL m_axis_tdata : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
|
||||
SIGNAL m_axis_tlast : STD_LOGIC;
|
||||
SIGNAL m_axis_tuser : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
|
||||
SIGNAL s_axis_tvalid : STD_LOGIC;
|
||||
SIGNAL s_axis_tready : STD_LOGIC;
|
||||
SIGNAL s_axis_tdata : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
|
||||
SIGNAL s_axis_tlast : STD_LOGIC;
|
||||
SIGNAL s_axis_tuser : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
|
||||
SIGNAL axis_wr_data_count : STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
SIGNAL axis_rd_data_count : STD_LOGIC_VECTOR(9 DOWNTO 0);
|
||||
SIGNAL m_aclk_i : STD_LOGIC;
|
||||
SIGNAL s_aclk_i : STD_LOGIC;
|
||||
-- TB Signals
|
||||
SIGNAL prc_we_i : STD_LOGIC := '0';
|
||||
SIGNAL prc_re_i : STD_LOGIC := '0';
|
||||
SIGNAL dout_chk_i : STD_LOGIC := '0';
|
||||
SIGNAL rst_int_rd : STD_LOGIC := '0';
|
||||
SIGNAL rst_int_wr : STD_LOGIC := '0';
|
||||
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
|
||||
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
|
||||
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
|
||||
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
|
||||
SIGNAL rst_s_rd : STD_LOGIC := '0';
|
||||
SIGNAL reset_en : STD_LOGIC := '0';
|
||||
SIGNAL din_axis : STD_LOGIC_VECTOR(69-1 DOWNTO 0);
|
||||
SIGNAL dout_axis : STD_LOGIC_VECTOR(69-1 DOWNTO 0);
|
||||
SIGNAL wr_en_axis : STD_LOGIC := '0';
|
||||
SIGNAL rd_en_axis : STD_LOGIC := '0';
|
||||
SIGNAL full_axis : STD_LOGIC := '0';
|
||||
SIGNAL empty_axis : STD_LOGIC := '0';
|
||||
SIGNAL status_axis : STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
|
||||
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
|
||||
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
|
||||
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
|
||||
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
|
||||
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
|
||||
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
|
||||
|
||||
|
||||
BEGIN
|
||||
|
||||
---- Reset generation logic -----
|
||||
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
|
||||
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
|
||||
|
||||
--Testbench reset synchronization
|
||||
PROCESS(m_aclk_i,RESET)
|
||||
BEGIN
|
||||
IF(RESET = '1') THEN
|
||||
rst_async_rd1 <= '1';
|
||||
rst_async_rd2 <= '1';
|
||||
rst_async_rd3 <= '1';
|
||||
ELSIF(m_aclk_i'event AND m_aclk_i='1') THEN
|
||||
rst_async_rd1 <= RESET;
|
||||
rst_async_rd2 <= rst_async_rd1;
|
||||
rst_async_rd3 <= rst_async_rd2;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(s_aclk_i,RESET)
|
||||
BEGIN
|
||||
IF(RESET = '1') THEN
|
||||
rst_async_wr1 <= '1';
|
||||
rst_async_wr2 <= '1';
|
||||
rst_async_wr3 <= '1';
|
||||
ELSIF(s_aclk_i'event AND s_aclk_i='1') THEN
|
||||
rst_async_wr1 <= RESET;
|
||||
rst_async_wr2 <= rst_async_wr1;
|
||||
rst_async_wr3 <= rst_async_wr2;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
--Soft reset for core and testbench
|
||||
PROCESS(m_aclk_i)
|
||||
BEGIN
|
||||
IF(m_aclk_i'event AND m_aclk_i='1') THEN
|
||||
rst_gen_rd <= rst_gen_rd + "1";
|
||||
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
|
||||
rst_s_rd <= '1';
|
||||
assert false
|
||||
report "Reset applied..Memory Collision checks are not valid"
|
||||
severity note;
|
||||
ELSE
|
||||
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
|
||||
rst_s_rd <= '0';
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS(s_aclk_i)
|
||||
BEGIN
|
||||
IF(s_aclk_i'event AND s_aclk_i='1') THEN
|
||||
rst_s_wr1 <= rst_s_rd;
|
||||
rst_s_wr2 <= rst_s_wr1;
|
||||
rst_s_wr3 <= rst_s_wr2;
|
||||
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
|
||||
assert false
|
||||
report "Reset removed..Memory Collision checks are valid"
|
||||
severity note;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
------------------
|
||||
|
||||
---- Clock buffers for testbench ----
|
||||
s_aclk_i <= S_ACLK;
|
||||
m_aclk_i <= M_ACLK;
|
||||
------------------
|
||||
|
||||
s_aresetn <= NOT (RESET OR rst_s_rd) AFTER 12 ns;
|
||||
|
||||
|
||||
|
||||
|
||||
S_AXIS_TVALID <= wr_en_axis;
|
||||
M_AXIS_TREADY <= rd_en_axis;
|
||||
full_axis <= NOT s_axis_tready;
|
||||
empty_axis <= NOT m_axis_tvalid;
|
||||
|
||||
fg_dg_axis: axi64_4k_2clk_fifo_dgen
|
||||
GENERIC MAP (
|
||||
C_DIN_WIDTH => 69,
|
||||
C_DOUT_WIDTH => 69,
|
||||
TB_SEED => TB_SEED,
|
||||
C_CH_TYPE => 0
|
||||
)
|
||||
PORT MAP (
|
||||
RESET => rst_int_wr,
|
||||
WR_CLK => s_aclk_i,
|
||||
PRC_WR_EN => prc_we_i,
|
||||
FULL => full_axis,
|
||||
WR_EN => wr_en_axis,
|
||||
WR_DATA => din_axis
|
||||
);
|
||||
|
||||
fg_dv_axis: axi64_4k_2clk_fifo_dverif
|
||||
GENERIC MAP (
|
||||
C_DOUT_WIDTH => 69,
|
||||
C_DIN_WIDTH => 69,
|
||||
C_USE_EMBEDDED_REG => 0,
|
||||
TB_SEED => TB_SEED,
|
||||
C_CH_TYPE => 0
|
||||
)
|
||||
PORT MAP(
|
||||
RESET => rst_int_rd,
|
||||
RD_CLK => m_aclk_i,
|
||||
PRC_RD_EN => prc_re_i,
|
||||
RD_EN => rd_en_axis,
|
||||
EMPTY => empty_axis,
|
||||
DATA_OUT => dout_axis,
|
||||
DOUT_CHK => dout_chk_i
|
||||
);
|
||||
|
||||
fg_pc_axis: axi64_4k_2clk_fifo_pctrl
|
||||
GENERIC MAP (
|
||||
AXI_CHANNEL => "AXI4_Stream",
|
||||
C_APPLICATION_TYPE => 0,
|
||||
C_DOUT_WIDTH => 69,
|
||||
C_DIN_WIDTH => 69,
|
||||
C_WR_PNTR_WIDTH => 9,
|
||||
C_RD_PNTR_WIDTH => 9,
|
||||
C_CH_TYPE => 0,
|
||||
FREEZEON_ERROR => FREEZEON_ERROR,
|
||||
TB_SEED => TB_SEED,
|
||||
TB_STOP_CNT => TB_STOP_CNT
|
||||
)
|
||||
PORT MAP(
|
||||
RESET_WR => rst_int_wr,
|
||||
RESET_RD => rst_int_rd,
|
||||
RESET_EN => reset_en,
|
||||
WR_CLK => s_aclk_i,
|
||||
RD_CLK => m_aclk_i,
|
||||
PRC_WR_EN => prc_we_i,
|
||||
PRC_RD_EN => prc_re_i,
|
||||
FULL => full_axis,
|
||||
EMPTY => empty_axis,
|
||||
ALMOST_FULL => '0',
|
||||
ALMOST_EMPTY => '0',
|
||||
DATA_IN => din_axis,
|
||||
DATA_OUT => dout_axis,
|
||||
DOUT_CHK => dout_chk_i,
|
||||
SIM_DONE => SIM_DONE,
|
||||
STATUS => STATUS
|
||||
);
|
||||
s_axis_tdata <= din_axis(69-1 DOWNTO TDATA_OFFSET);
|
||||
dout_axis(69-1 DOWNTO TDATA_OFFSET) <= m_axis_tdata;
|
||||
s_axis_tuser <= DIN_AXIS(TDEST_OFFSET-1 DOWNTO TLAST_OFFSET);
|
||||
dout_axis(TDEST_OFFSET-1 DOWNTO TLAST_OFFSET) <= m_axis_tuser;
|
||||
s_axis_tlast <= din_axis(0);
|
||||
dout_axis(0) <= m_axis_tlast;
|
||||
|
||||
axi64_4k_2clk_fifo_inst : axi64_4k_2clk_fifo_exdes
|
||||
PORT MAP (
|
||||
S_ARESETN => s_aresetn,
|
||||
M_AXIS_TVALID => m_axis_tvalid,
|
||||
M_AXIS_TREADY => m_axis_tready,
|
||||
M_AXIS_TDATA => m_axis_tdata,
|
||||
M_AXIS_TLAST => m_axis_tlast,
|
||||
M_AXIS_TUSER => m_axis_tuser,
|
||||
S_AXIS_TVALID => s_axis_tvalid,
|
||||
S_AXIS_TREADY => s_axis_tready,
|
||||
S_AXIS_TDATA => s_axis_tdata,
|
||||
S_AXIS_TLAST => s_axis_tlast,
|
||||
S_AXIS_TUSER => s_axis_tuser,
|
||||
AXIS_WR_DATA_COUNT => axis_wr_data_count,
|
||||
AXIS_RD_DATA_COUNT => axis_rd_data_count,
|
||||
M_ACLK => m_aclk_i,
|
||||
S_ACLK => s_aclk_i);
|
||||
|
||||
END ARCHITECTURE;
|
||||
@@ -1,208 +0,0 @@
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- FIFO Generator Core Demo Testbench
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- Filename: axi64_4k_2clk_fifo_tb.vhd
|
||||
--
|
||||
-- Description:
|
||||
-- This is the demo testbench top file for fifo_generator core.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Library Declarations
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
LIBRARY std;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.std_logic_unsigned.ALL;
|
||||
USE IEEE.std_logic_arith.ALL;
|
||||
USE IEEE.std_logic_misc.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
USE ieee.std_logic_textio.ALL;
|
||||
USE std.textio.ALL;
|
||||
|
||||
LIBRARY work;
|
||||
USE work.axi64_4k_2clk_fifo_pkg.ALL;
|
||||
|
||||
ENTITY axi64_4k_2clk_fifo_tb IS
|
||||
END ENTITY;
|
||||
|
||||
|
||||
ARCHITECTURE axi64_4k_2clk_fifo_arch OF axi64_4k_2clk_fifo_tb IS
|
||||
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
|
||||
SIGNAL wr_clk : STD_LOGIC;
|
||||
SIGNAL rd_clk : STD_LOGIC;
|
||||
SIGNAL reset : STD_LOGIC;
|
||||
SIGNAL sim_done : STD_LOGIC := '0';
|
||||
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
|
||||
-- Write and Read clock periods
|
||||
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
|
||||
CONSTANT rd_clk_period_by_2 : TIME := 100 ns;
|
||||
-- Procedures to display strings
|
||||
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
|
||||
variable dp_l : line := null;
|
||||
BEGIN
|
||||
write(dp_l,str);
|
||||
writeline(output,dp_l);
|
||||
END PROCEDURE;
|
||||
|
||||
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
|
||||
variable dp_lx : line := null;
|
||||
BEGIN
|
||||
hwrite(dp_lx,hex);
|
||||
writeline(output,dp_lx);
|
||||
END PROCEDURE;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Generation of clock
|
||||
|
||||
PROCESS BEGIN
|
||||
WAIT FOR 400 ns; -- Wait for global reset
|
||||
WHILE 1 = 1 LOOP
|
||||
wr_clk <= '0';
|
||||
WAIT FOR wr_clk_period_by_2;
|
||||
wr_clk <= '1';
|
||||
WAIT FOR wr_clk_period_by_2;
|
||||
END LOOP;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS BEGIN
|
||||
WAIT FOR 200 ns;-- Wait for global reset
|
||||
WHILE 1 = 1 LOOP
|
||||
rd_clk <= '0';
|
||||
WAIT FOR rd_clk_period_by_2;
|
||||
rd_clk <= '1';
|
||||
WAIT FOR rd_clk_period_by_2;
|
||||
END LOOP;
|
||||
END PROCESS;
|
||||
|
||||
-- Generation of Reset
|
||||
|
||||
PROCESS BEGIN
|
||||
reset <= '1';
|
||||
WAIT FOR 4200 ns;
|
||||
reset <= '0';
|
||||
WAIT;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
-- Error message printing based on STATUS signal from axi64_4k_2clk_fifo_synth
|
||||
|
||||
PROCESS(status)
|
||||
BEGIN
|
||||
IF(status /= "0" AND status /= "1") THEN
|
||||
disp_str("STATUS:");
|
||||
disp_hex(status);
|
||||
END IF;
|
||||
|
||||
IF(status(7) = '1') THEN
|
||||
assert false
|
||||
report "Data mismatch found"
|
||||
severity error;
|
||||
END IF;
|
||||
|
||||
IF(status(1) = '1') THEN
|
||||
END IF;
|
||||
|
||||
IF(status(5) = '1') THEN
|
||||
assert false
|
||||
report "Empty flag Mismatch/timeout"
|
||||
severity error;
|
||||
END IF;
|
||||
|
||||
IF(status(6) = '1') THEN
|
||||
assert false
|
||||
report "Full Flag Mismatch/timeout"
|
||||
severity error;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
|
||||
PROCESS
|
||||
BEGIN
|
||||
wait until sim_done = '1';
|
||||
IF(status /= "0" AND status /= "1") THEN
|
||||
assert false
|
||||
report "Simulation failed"
|
||||
severity failure;
|
||||
ELSE
|
||||
assert false
|
||||
report "Test Completed Successfully"
|
||||
severity failure;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS
|
||||
BEGIN
|
||||
wait for 400 ms;
|
||||
assert false
|
||||
report "Test bench timed out"
|
||||
severity failure;
|
||||
END PROCESS;
|
||||
|
||||
-- Instance of axi64_4k_2clk_fifo_synth
|
||||
|
||||
axi64_4k_2clk_fifo_synth_inst:axi64_4k_2clk_fifo_synth
|
||||
GENERIC MAP(
|
||||
FREEZEON_ERROR => 0,
|
||||
TB_STOP_CNT => 2,
|
||||
TB_SEED => 20
|
||||
)
|
||||
PORT MAP(
|
||||
S_ACLK => wr_clk,
|
||||
M_ACLK => rd_clk,
|
||||
RESET => reset,
|
||||
SIM_DONE => sim_done,
|
||||
STATUS => status
|
||||
);
|
||||
|
||||
END ARCHITECTURE;
|
||||
@@ -1,63 +0,0 @@
|
||||
:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
::
|
||||
:: This file contains confidential and proprietary information
|
||||
:: of Xilinx, Inc. and is protected under U.S. and
|
||||
:: international copyright and other intellectual property
|
||||
:: laws.
|
||||
::
|
||||
:: DISCLAIMER
|
||||
:: This disclaimer is not a license and does not grant any
|
||||
:: rights to the materials distributed herewith. Except as
|
||||
:: otherwise provided in a valid license issued to you by
|
||||
:: Xilinx, and to the maximum extent permitted by applicable
|
||||
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
:: (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
:: including negligence, or under any other theory of
|
||||
:: liability) for any loss or damage of any kind or nature
|
||||
:: related to, arising under or in connection with these
|
||||
:: materials, including for any direct, or any indirect,
|
||||
:: special, incidental, or consequential loss or damage
|
||||
:: (including loss of data, profits, goodwill, or any type of
|
||||
:: loss or damage suffered as a result of any action brought
|
||||
:: by a third party) even if such damage or loss was
|
||||
:: reasonably foreseeable or Xilinx had been advised of the
|
||||
:: possibility of the same.
|
||||
::
|
||||
:: CRITICAL APPLICATIONS
|
||||
:: Xilinx products are not designed or intended to be fail-
|
||||
:: safe, or for use in any application requiring fail-safe
|
||||
:: performance, such as life-support or safety devices or
|
||||
:: systems, Class III medical devices, nuclear facilities,
|
||||
:: applications related to the deployment of airbags, or any
|
||||
:: other applications that could lead to death, personal
|
||||
:: injury, or severe property or environmental damage
|
||||
:: (individually and collectively, "Critical
|
||||
:: Applications"). Customer assumes the sole risk and
|
||||
:: liability of any use of Xilinx products in Critical
|
||||
:: Applications, subject only to applicable laws and
|
||||
:: regulations governing limitations on product liability.
|
||||
::
|
||||
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
:: PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
echo "Compiling Core Verilog UNISIM/Behavioral model"
|
||||
vlogcomp -work work ..\\..\\..\\axi64_4k_2clk_fifo.v
|
||||
vhpcomp -work work ..\\..\\example_design\\axi64_4k_2clk_fifo_exdes.vhd
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
vhpcomp -work work ..\\axi64_4k_2clk_fifo_pkg.vhd
|
||||
vhpcomp -work work ..\\axi64_4k_2clk_fifo_rng.vhd
|
||||
vhpcomp -work work ..\\axi64_4k_2clk_fifo_dgen.vhd
|
||||
vhpcomp -work work ..\\axi64_4k_2clk_fifo_dverif.vhd
|
||||
vhpcomp -work work ..\\axi64_4k_2clk_fifo_pctrl.vhd
|
||||
vhpcomp -work work ..\\axi64_4k_2clk_fifo_synth.vhd
|
||||
vhpcomp -work work ..\\axi64_4k_2clk_fifo_tb.vhd
|
||||
|
||||
vlogcomp -work work $XILINX\\verilog\\src\\glbl.v
|
||||
fuse work.axi64_4k_2clk_fifo_tb work.glbl -L xilinxcorelib_ver -L unisims_ver -o axi64_4k_2clk_fifo_tb.exe
|
||||
|
||||
.\\axi64_4k_2clk_fifo_tb.exe -gui -tclbatch .\\wave_isim.tcl
|
||||
@@ -1,65 +0,0 @@
|
||||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#--------------------------------------------------------------------------------
|
||||
|
||||
echo "Compiling Core Verilog UNISIM/Behavioral model"
|
||||
vlogcomp -work work ../../../axi64_4k_2clk_fifo.v
|
||||
vhpcomp -work work ../../example_design/axi64_4k_2clk_fifo_exdes.vhd
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
vhpcomp -work work ../axi64_4k_2clk_fifo_pkg.vhd
|
||||
vhpcomp -work work ../axi64_4k_2clk_fifo_rng.vhd
|
||||
vhpcomp -work work ../axi64_4k_2clk_fifo_dgen.vhd
|
||||
vhpcomp -work work ../axi64_4k_2clk_fifo_dverif.vhd
|
||||
vhpcomp -work work ../axi64_4k_2clk_fifo_pctrl.vhd
|
||||
vhpcomp -work work ../axi64_4k_2clk_fifo_synth.vhd
|
||||
vhpcomp -work work ../axi64_4k_2clk_fifo_tb.vhd
|
||||
|
||||
vlogcomp -work work $XILINX/verilog/src/glbl.v
|
||||
fuse work.axi64_4k_2clk_fifo_tb work.glbl -L xilinxcorelib_ver -L unisims_ver -o axi64_4k_2clk_fifo_tb.exe
|
||||
|
||||
./axi64_4k_2clk_fifo_tb.exe -gui -tclbatch ./wave_isim.tcl
|
||||
@@ -1,47 +0,0 @@
|
||||
:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
::
|
||||
:: This file contains confidential and proprietary information
|
||||
:: of Xilinx, Inc. and is protected under U.S. and
|
||||
:: international copyright and other intellectual property
|
||||
:: laws.
|
||||
::
|
||||
:: DISCLAIMER
|
||||
:: This disclaimer is not a license and does not grant any
|
||||
:: rights to the materials distributed herewith. Except as
|
||||
:: otherwise provided in a valid license issued to you by
|
||||
:: Xilinx, and to the maximum extent permitted by applicable
|
||||
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
:: (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
:: including negligence, or under any other theory of
|
||||
:: liability) for any loss or damage of any kind or nature
|
||||
:: related to, arising under or in connection with these
|
||||
:: materials, including for any direct, or any indirect,
|
||||
:: special, incidental, or consequential loss or damage
|
||||
:: (including loss of data, profits, goodwill, or any type of
|
||||
:: loss or damage suffered as a result of any action brought
|
||||
:: by a third party) even if such damage or loss was
|
||||
:: reasonably foreseeable or Xilinx had been advised of the
|
||||
:: possibility of the same.
|
||||
::
|
||||
:: CRITICAL APPLICATIONS
|
||||
:: Xilinx products are not designed or intended to be fail-
|
||||
:: safe, or for use in any application requiring fail-safe
|
||||
:: performance, such as life-support or safety devices or
|
||||
:: systems, Class III medical devices, nuclear facilities,
|
||||
:: applications related to the deployment of airbags, or any
|
||||
:: other applications that could lead to death, personal
|
||||
:: injury, or severe property or environmental damage
|
||||
:: (individually and collectively, "Critical
|
||||
:: Applications"). Customer assumes the sole risk and
|
||||
:: liability of any use of Xilinx products in Critical
|
||||
:: Applications, subject only to applicable laws and
|
||||
:: regulations governing limitations on product liability.
|
||||
::
|
||||
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
:: PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
vsim -c -do simulate_mti.do
|
||||
@@ -1,74 +0,0 @@
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#--------------------------------------------------------------------------------
|
||||
|
||||
vlib work
|
||||
vmap work work
|
||||
|
||||
echo "Compiling Core Verilog UNISIM/Behavioral model"
|
||||
vlog -work work ../../../axi64_4k_2clk_fifo.v
|
||||
vcom -work work ../../example_design/axi64_4k_2clk_fifo_exdes.vhd
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
vcom -work work ../axi64_4k_2clk_fifo_pkg.vhd
|
||||
vcom -work work ../axi64_4k_2clk_fifo_rng.vhd
|
||||
vcom -work work ../axi64_4k_2clk_fifo_dgen.vhd
|
||||
vcom -work work ../axi64_4k_2clk_fifo_dverif.vhd
|
||||
vcom -work work ../axi64_4k_2clk_fifo_pctrl.vhd
|
||||
vcom -work work ../axi64_4k_2clk_fifo_synth.vhd
|
||||
vcom -work work ../axi64_4k_2clk_fifo_tb.vhd
|
||||
|
||||
vlog -work work $env(XILINX)/verilog/src/glbl.v
|
||||
vsim -t ps -voptargs="+acc" -L XilinxCoreLib_ver -L unisims_ver glbl work.axi64_4k_2clk_fifo_tb
|
||||
|
||||
add log -r /*
|
||||
do wave_mti.do
|
||||
#Ignore integer warnings at time 0
|
||||
set StdArithNoWarnings 1
|
||||
run 0
|
||||
set StdArithNoWarnings 0
|
||||
|
||||
run -all
|
||||
@@ -1,49 +0,0 @@
|
||||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#--------------------------------------------------------------------------------
|
||||
|
||||
vsim -c -do simulate_mti.do
|
||||
@@ -1,69 +0,0 @@
|
||||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#--------------------------------------------------------------------------------
|
||||
mkdir work
|
||||
|
||||
echo "Compiling Core Verilog UNISIM/Behavioral model"
|
||||
ncvlog -work work ../../../axi64_4k_2clk_fifo.v
|
||||
ncvhdl -v93 -work work ../../example_design/axi64_4k_2clk_fifo_exdes.vhd
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
ncvhdl -v93 -work work ../axi64_4k_2clk_fifo_pkg.vhd
|
||||
ncvhdl -v93 -work work ../axi64_4k_2clk_fifo_rng.vhd
|
||||
ncvhdl -v93 -work work ../axi64_4k_2clk_fifo_dgen.vhd
|
||||
ncvhdl -v93 -work work ../axi64_4k_2clk_fifo_dverif.vhd
|
||||
ncvhdl -v93 -work work ../axi64_4k_2clk_fifo_pctrl.vhd
|
||||
ncvhdl -v93 -work work ../axi64_4k_2clk_fifo_synth.vhd
|
||||
ncvhdl -v93 -work work ../axi64_4k_2clk_fifo_tb.vhd
|
||||
|
||||
echo "Elaborating Design"
|
||||
ncvlog -work work $XILINX/verilog/src/glbl.v
|
||||
ncelab -access +rwc glbl work.axi64_4k_2clk_fifo_tb
|
||||
|
||||
echo "Simulating Design"
|
||||
ncsim -gui -input @"simvision -input wave_ncsim.sv" work.axi64_4k_2clk_fifo_tb
|
||||
|
||||
@@ -1,69 +0,0 @@
|
||||
#!/bin/sh
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#--------------------------------------------------------------------------------
|
||||
rm -rf simv* csrc DVEfiles AN.DB
|
||||
|
||||
echo "Compiling Core Verilog UNISIM/Behavioral model"
|
||||
vlogan +v2k ../../../axi64_4k_2clk_fifo.v
|
||||
vhdlan ../../example_design/axi64_4k_2clk_fifo_exdes.vhd
|
||||
|
||||
echo "Compiling Test Bench Files"
|
||||
vhdlan ../axi64_4k_2clk_fifo_pkg.vhd
|
||||
vhdlan ../axi64_4k_2clk_fifo_rng.vhd
|
||||
vhdlan ../axi64_4k_2clk_fifo_dgen.vhd
|
||||
vhdlan ../axi64_4k_2clk_fifo_dverif.vhd
|
||||
vhdlan ../axi64_4k_2clk_fifo_pctrl.vhd
|
||||
vhdlan ../axi64_4k_2clk_fifo_synth.vhd
|
||||
vhdlan ../axi64_4k_2clk_fifo_tb.vhd
|
||||
|
||||
echo "Elaborating Design"
|
||||
vlogan +v2k $XILINX/verilog/src/glbl.v
|
||||
vcs -time_res 1ps +vcs+lic+wait -debug axi64_4k_2clk_fifo_tb glbl
|
||||
|
||||
echo "Simulating Design"
|
||||
./simv -ucli -i ucli_commands.key
|
||||
dve -session vcs_session.tcl
|
||||
@@ -1,4 +0,0 @@
|
||||
dump -file axi64_4k_2clk_fifo.vpd -type VPD
|
||||
dump -add axi64_4k_2clk_fifo_tb
|
||||
run
|
||||
quit
|
||||
@@ -1,76 +0,0 @@
|
||||
#--------------------------------------------------------------------------------
|
||||
#--
|
||||
#-- FIFO Generator Core Demo Testbench
|
||||
#--
|
||||
#--------------------------------------------------------------------------------
|
||||
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
# Filename: vcs_session.tcl
|
||||
#
|
||||
# Description:
|
||||
# This is the VCS wave form file.
|
||||
#
|
||||
#--------------------------------------------------------------------------------
|
||||
if { ![gui_is_db_opened -db {axi64_4k_2clk_fifo.vpd}] } {
|
||||
gui_open_db -design V1 -file axi64_4k_2clk_fifo.vpd -nosource
|
||||
}
|
||||
gui_set_precision 1ps
|
||||
gui_set_time_units 1ps
|
||||
|
||||
|
||||
gui_open_window Wave
|
||||
gui_sg_create axi64_4k_2clk_fifo_Group
|
||||
gui_list_add_group -id Wave.1 {axi64_4k_2clk_fifo_Group}
|
||||
|
||||
gui_sg_addsignal -group axi64_4k_2clk_fifo_Group {Slave interface} -divider
|
||||
gui_sg_addsignal -group axi64_4k_2clk_fifo_Group /axi64_4k_2clk_fifo_tb/axi64_4k_2clk_fifo_synth_inst/axi64_4k_2clk_fifo_inst/S_ACLK
|
||||
gui_sg_addsignal -group axi64_4k_2clk_fifo_Group /axi64_4k_2clk_fifo_tb/axi64_4k_2clk_fifo_synth_inst/axi64_4k_2clk_fifo_inst/S_AXIS_TVALID
|
||||
gui_sg_addsignal -group axi64_4k_2clk_fifo_Group /axi64_4k_2clk_fifo_tb/axi64_4k_2clk_fifo_synth_inst/axi64_4k_2clk_fifo_inst/S_AXIS_TREADY
|
||||
gui_sg_addsignal -group axi64_4k_2clk_fifo_Group {Master Interface} -divider
|
||||
gui_sg_addsignal -group axi64_4k_2clk_fifo_Group /axi64_4k_2clk_fifo_tb/axi64_4k_2clk_fifo_synth_inst/axi64_4k_2clk_fifo_inst/M_ACLK
|
||||
gui_sg_addsignal -group axi64_4k_2clk_fifo_Group /axi64_4k_2clk_fifo_tb/axi64_4k_2clk_fifo_synth_inst/axi64_4k_2clk_fifo_inst/M_AXIS_TVALID
|
||||
gui_sg_addsignal -group axi64_4k_2clk_fifo_Group /axi64_4k_2clk_fifo_tb/axi64_4k_2clk_fifo_synth_inst/axi64_4k_2clk_fifo_inst/M_AXIS_TREADY
|
||||
gui_zoom -window Wave.1 -full
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user