Ashish Chaudhari
adf2da6ac7
- Fixed 10GigE firmware communication issues and sequence errors for TX - Multiple changes to help ease timing closure - Cleaned up build scripts - Switched to Xilinx ISE 14.7 as the default build tool for X300 Original-commit: 64d71dcbc5fa6790385b288de25224d386b047b0
107 lines
3.2 KiB
Makefile
107 lines
3.2 KiB
Makefile
#
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# Copyright 2012-2013 Ettus Research LLC
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#
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# Uncomment the following lines to build radio's with no DSP's
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#OPTIONS += DELETE_DSP0=1
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#OPTIONS += DELETE_DSP1=1
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# Uncomment the following line to add a debug UART on GPIO 10 & 11
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#OPTIONS += DEBUG_UART=1
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CREATE_LVBITX=python ../../lib/io_port2/create-lvbitx.py
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GIGE_DEFS=BUILD_1G=1 $(OPTIONS)
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HYBRID_DEFS=ETH10G_PORT1=1 BUILD_1G=1 BUILD_10G=1 $(OPTIONS)
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XGIGE_DEFS=ETH10G_PORT0=1 ETH10G_PORT1=1 BUILD_10G=1 $(OPTIONS)
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HYBRID_SRAM_DEFS=ETH10G_PORT1=1 BUILD_1G=1 BUILD_10G=1 NO_DRAM_FIFOS=1 SRAM_FIFO_SIZE=16 $(OPTIONS)
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XGIGE_SRAM_DEFS=ETH10G_PORT0=1 ETH10G_PORT1=1 BUILD_10G=1 NO_DRAM_FIFOS=1 SRAM_FIFO_SIZE=16 $(OPTIONS)
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X300: X300_HGS X300_HG X300_XGS X300_XG
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X310: X310_HGS X310_HG X310_XGS X310_XG
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all: X300 X310
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clean:
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rm -rf build-*_*
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rm -rf build
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print_report = \
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echo "========================================================================"; \
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cat $(1)/x300.syr | grep "Device utilization summary:" -A 30; \
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echo "========================================================================"; \
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echo "Timing Summary:\n"; \
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cat $(1)/x300.twr | grep constraint | grep met | grep -v "*"; \
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echo "========================================================================";
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# ise_build($1=Device, $2=Definitions)
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ifndef EXPORT_ONLY
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ise_build = make -f Makefile.x300.inc bin NAME=$@ DEVICE=$1 $2 EXTRA_DEFS="$2"
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else
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ise_build = @echo "Skipping ISE build and exporting pre-built files.";
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endif
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# post_build($1=Device, $2=Flavor)
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post_build = \
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@$(call print_report,build-$(1)_$(2)) \
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mkdir -p build; \
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echo "Exporting bitstream files..."; \
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cp build-$(1)_$(2)/x300.bin build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bin; \
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cp build-$(1)_$(2)/x300.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
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echo "Generating LVBITX..."; \
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$(CREATE_LVBITX) --input-bin=build-$(1)_$(2)/x300.bin --output-lvbitx=build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).lvbitx --device="USRP $(1)" x3x0_base.lvbitx; \
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cp -f x3x0_base.lvbitx build/`echo $(1) | tr A-Z a-z`.lvbitx_base; \
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echo "Exporting logs..."; \
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cp build-$(1)_$(2)/x300.syr build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).syr; \
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cp build-$(1)_$(2)/x300.twr build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).twr; \
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echo "\nDONE ... $(1)_$(2)\n";
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#1Gig on both ports
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X310_1G:
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$(call ise_build,XC7K410T,$(GIGE_DEFS))
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$(call post_build,X310,1G)
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X300_1G:
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$(call ise_build,XC7K325T,$(GIGE_DEFS))
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$(call post_build,X300,1G)
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#1Gig on port0, 10Gig on port1
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X310_HG:
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$(call ise_build,XC7K410T,$(HYBRID_DEFS))
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$(call post_build,X310,HG)
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X300_HG:
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$(call ise_build,XC7K325T,$(HYBRID_DEFS))
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$(call post_build,X300,HG)
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#10Gig on both ports
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X310_XG:
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$(call ise_build,XC7K410T,$(XGIGE_DEFS))
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$(call post_build,X310,XG)
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X300_XG:
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$(call ise_build,XC7K325T,$(XGIGE_DEFS))
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$(call post_build,X300,XG)
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# 1Gig on port0, 10Gig on port1, SRAM Tx FIFO's
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X310_HGS:
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$(call ise_build,XC7K410T,$(HYBRID_SRAM_DEFS))
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$(call post_build,X310,HGS)
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X300_HGS:
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$(call ise_build,XC7K325T,$(HYBRID_SRAM_DEFS))
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$(call post_build,X300,HGS)
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# 10Gig on both ports, SRAM Tx FIFO's
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X310_XGS:
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$(call ise_build,XC7K410T,$(XGIGE_SRAM_DEFS))
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$(call post_build,X310,XGS)
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X300_XGS:
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$(call ise_build,XC7K325T,$(XGIGE_SRAM_DEFS))
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$(call post_build,X300,XGS)
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.PHONY: all clean
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