Ashish Chaudhari
adf2da6ac7
- Fixed 10GigE firmware communication issues and sequence errors for TX - Multiple changes to help ease timing closure - Cleaned up build scripts - Switched to Xilinx ISE 14.7 as the default build tool for X300 Original-commit: 64d71dcbc5fa6790385b288de25224d386b047b0
68 lines
1.8 KiB
Makefile
68 lines
1.8 KiB
Makefile
#
|
|
# Copyright 2012 Ettus Research LLC
|
|
#
|
|
|
|
##################################################
|
|
# Coregen Sources
|
|
##################################################
|
|
CG_TMP_DIR = $(HOME)/.tmp/$(NAME)_coregen
|
|
CG_SOURCE_DIR = $(BASE_DIR)/x300/coregen
|
|
CG_BUILD_DIR = $(BUILD_DIR)/coregen
|
|
|
|
COREGEN_SRCS = $(abspath $(addprefix $(CG_BUILD_DIR)/, \
|
|
input_sample_fifo.v \
|
|
input_sample_fifo.xco \
|
|
axi64_4k_2clk_fifo.v \
|
|
axi64_8k_2clk_fifo.v \
|
|
fifo_4k_2clk.v \
|
|
fifo_short_2clk.v \
|
|
fifo_short_2clk.xco \
|
|
radio_clk_gen.v \
|
|
radio_clk_gen.xco \
|
|
bus_clk_gen.v \
|
|
bus_clk_gen.xco \
|
|
pcie_clk_gen.v \
|
|
pcie_clk_gen.xco \
|
|
bootram.xco \
|
|
))
|
|
|
|
COREGEN_DRAM_SRCS = $(abspath $(addprefix $(CG_SOURCE_DIR)/, \
|
|
axi_intercon_2x64_128.xco \
|
|
ddr3_32bit/user_design/rtl/ddr3_32bit.v \
|
|
ddr3_32bit/user_design/constraints/ddr3_32bit.ucf \
|
|
ddr3_32bit.xco \
|
|
))
|
|
|
|
COREGEN_CHIPSCOPE_SRCS = $(abspath $(addprefix $(CG_SOURCE_DIR)/, \
|
|
chipscope_ila.v \
|
|
chipscope_ila.xco \
|
|
chipscope_ila_64.v \
|
|
chipscope_ila_64.xco \
|
|
chipscope_icon.v \
|
|
chipscope_icon.xco \
|
|
chipscope_icon_2port.v \
|
|
chipscope_icon_2port.xco \
|
|
))
|
|
|
|
COREGEN_ONE_GIG_SRCS = $(abspath $(addprefix $(CG_SOURCE_DIR)/, \
|
|
gige_sfp_mdio.v \
|
|
))
|
|
|
|
COREGEN_TEN_GIG_SRCS = $(abspath $(addprefix $(CG_SOURCE_DIR)/, \
|
|
ten_gig_eth_pcs_pma.v \
|
|
))
|
|
|
|
#make rule to regenerate bootram when the coe file is changed
|
|
#this takes place out of tree to make the coregen tool happy
|
|
$(CG_TMP_DIR)/bootram.coe: $(CG_SOURCE_DIR)/bootram.coe
|
|
mkdir -p $(CG_TMP_DIR)
|
|
cp -r $(CG_SOURCE_DIR)/* $(CG_TMP_DIR)/
|
|
coregen -b $(CG_TMP_DIR)/bootram.xco -p $(CG_TMP_DIR) -r
|
|
|
|
#copy all coregen products into the build dir
|
|
#these products will be deleted with make clean
|
|
$(COREGEN_SRCS): $(CG_TMP_DIR)/bootram.coe
|
|
mkdir -p $(CG_BUILD_DIR)
|
|
cp -r $(CG_SOURCE_DIR)/* $(CG_BUILD_DIR)/
|
|
cp -r $(CG_TMP_DIR)/bootram.* $(CG_BUILD_DIR)/
|