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fpga: Add X440/FBX support

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Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>


Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
This commit is contained in:
Javier Valenzuela
2023-06-12 10:27:29 -05:00
committed by Aki Tomita
co-authored by Martin Braun Wade Fife Ryan Marlow
parent a405111ce7
commit 5cadf901c7
121 changed files with 20670 additions and 8739 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/x400/x4xx.v
+682 -7
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@@ -27,7 +27,16 @@ module x4xx (
// Analog ports
`ifdef X410
`ifdef X440
input wire [3:0] DB0_RX_P,
input wire [3:0] DB0_RX_N,
input wire [3:0] DB1_RX_P,
input wire [3:0] DB1_RX_N,
output wire [3:0] DB0_TX_P,
output wire [3:0] DB0_TX_N,
output wire [3:0] DB1_TX_P,
output wire [3:0] DB1_TX_N,
`else // X410
input wire [1:0] DB0_RX_P,
input wire [1:0] DB0_RX_N,
input wire [1:0] DB1_RX_P,
@@ -246,11 +255,17 @@ module x4xx (
);
// Variant-dependent register map.
`ifdef X410
`ifdef X440
`include "regmap/x440/versioning_regs_regmap_utils.vh"
`else // Use X410 as the default variant for regmap.
`include "regmap/x410/versioning_regs_regmap_utils.vh"
`endif
`ifdef X410
// Both of these provide the same values for what we need, but we'll keep the
// if/else clause for consistency with other includes.
`ifdef X440
`include "regmap/x440/rfdc_regs_regmap_utils.vh"
`else // Use X410 as the default variant for regmap.
`include "regmap/x410/rfdc_regs_regmap_utils.vh"
`endif
@@ -302,8 +317,8 @@ module x4xx (
localparam NUM_DBOARDS = 2;
`ifdef X410
localparam NUM_TIMEKEEPERS = 1;
`ifdef X440
localparam NUM_TIMEKEEPERS = NUM_DBOARDS;
`else
localparam NUM_TIMEKEEPERS = 1;
`endif
@@ -454,6 +469,19 @@ module x4xx (
assign clk40_rstn = ~clk40_rst;
assign bus_clk_rstn = ~bus_clk_rst;
// Need a 5 MHz pulse on X440 to use as a sync ref
`ifdef X440
wire clk5;
clock_div #(
.N(2)
) clock_div_5mhz (
.clk_in (base_ref_clk),
.clk_in_rst (brc_rst),
.clk_out (clk5)
);
`endif
//---------------------------------------------------------------------------
// PPS Handling
//---------------------------------------------------------------------------
@@ -641,6 +669,8 @@ module x4xx (
`ifdef X410
localparam NUM_CH_PER_DB = 2;
`elsif X440
localparam NUM_CH_PER_DB = 4;
`else
localparam NUM_CH_PER_DB = 2;
`endif
@@ -1250,6 +1280,468 @@ module x4xx (
.s_axi_hpc1_aruser (),
.s_axi_hpc1_awuser ()
);
`elsif X440
x440_ps_rfdc_bd x440_ps_rfdc_bd_i (
.adc_data_out_resetn_dclk (adc_data_out_resetn_dclk),
.adc_enable_data_rclk (adc_enable_data_rclk),
.adc_reset_pulse_dclk (adc_reset_pulse),
.adc_rfdc_axi_resetn_rclk (adc_rfdc_axi_resetn_rclk),
.bus_clk (bus_clk),
.bus_rstn (bus_clk_rstn),
.clk40 (clk40),
.clk40_rstn (clk40_rstn),
.dac_data_in_resetn_dclk (dac_data_in_resetn_dclk),
.dac_data_in_resetn_dclk2x (dac_data_in_resetn_dclk2x),
.dac_data_in_resetn_rclk (dac_data_in_resetn_rclk),
.dac_data_in_resetn_rclk2x (dac_data_in_resetn_rclk2x),
.dac_reset_pulse_dclk (dac_reset_pulse),
.data_clk (data_clk),
.data_clk_2x (data_clk_2x),
.data_clock_locked (),
.enable_gated_clocks_clk40 (1'b1),
.enable_sysref_rclk (1'b1),
.fir_resetn_rclk2x (fir_resetn_rclk2x),
.gated_base_clks_valid_clk40 (),
.radio0_invert_adc_iq_r0clk (invert_adc_iq_rclk2[3:0]),
.radio0_invert_dac_iq_r0clk (invert_dac_iq_rclk2[3:0]),
.radio1_invert_adc_iq_r1clk (invert_adc_iq_rclk2[7:4]),
.radio1_invert_dac_iq_r1clk (invert_dac_iq_rclk2[7:4]),
.irq0_lpd_rpu_n (1'b1),
.irq1_lpd_rpu_n (1'b1),
.jtag0_tck (),
.jtag0_tdi (),
.jtag0_tdo (),
.jtag0_tms (),
.nco_reset_done_dclk (nco_reset_done),
.pl_clk40 (clk40),
.pl_clk100 (clk100),
.pl_clk166 (clk166),
.pl_clk200 (clk200),
.pl_ps_irq0 (pl_ps_irq0),
.pl_ps_irq1 (pl_ps_irq1),
.pl_resetn0 (pl_resetn0),
.pl_resetn1 (),
.pl_resetn2 (),
.pl_resetn3 (),
.pll_ref_clk_in (pll_ref_clk_in),
.pll_ref_clk_out (pll_ref_clk),
.rf_axi_status_clk40 (rf_axi_status_clk40),
.rf_dsp_info_clk40 (rf_dsp_info_clk40),
.rf_rfdc_info_clk40 (rf_rfdc_info_clk40),
.radio0_rfdc_clk_1x (rfdc_clk[0]),
.radio0_rfdc_clk_2x (rfdc_clk_2x[0]),
.radio1_rfdc_clk_1x (rfdc_clk[1]),
.radio1_rfdc_clk_2x (rfdc_clk_2x[1]),
.rfdc_irq (),
.s_axi_hp0_aclk (clk40),
.s_axi_hp1_aclk (clk40),
.s_axi_hpc0_aclk (),
.start_nco_reset_dclk (start_nco_reset),
.sysref_out_pclk (),
.sysref_out_rclk (),
.sysref_pl_in (sysref_pl),
`ifdef QSFP0_0
.s_axi_hp0_aruser (axi_hp0_aruser),
.s_axi_hp0_awuser (axi_hp0_awuser),
.s_axi_hp0_awid (axi_hp0_awid),
.s_axi_hp0_awaddr (axi_hp0_awaddr),
.s_axi_hp0_awlen (axi_hp0_awlen),
.s_axi_hp0_awsize (axi_hp0_awsize),
.s_axi_hp0_awburst (axi_hp0_awburst),
.s_axi_hp0_awlock (axi_hp0_awlock),
.s_axi_hp0_awcache (axi_hp0_awcache),
.s_axi_hp0_awprot (axi_hp0_awprot),
.s_axi_hp0_awvalid (axi_hp0_awvalid),
.s_axi_hp0_awready (axi_hp0_awready),
.s_axi_hp0_wdata (axi_hp0_wdata),
.s_axi_hp0_wstrb (axi_hp0_wstrb),
.s_axi_hp0_wlast (axi_hp0_wlast),
.s_axi_hp0_wvalid (axi_hp0_wvalid),
.s_axi_hp0_wready (axi_hp0_wready),
.s_axi_hp0_bid (),
.s_axi_hp0_bresp (axi_hp0_bresp),
.s_axi_hp0_bvalid (axi_hp0_bvalid),
.s_axi_hp0_bready (axi_hp0_bready),
.s_axi_hp0_arid (axi_hp0_arid),
.s_axi_hp0_araddr (axi_hp0_araddr),
.s_axi_hp0_arlen (axi_hp0_arlen),
.s_axi_hp0_arsize (axi_hp0_arsize),
.s_axi_hp0_arburst (axi_hp0_arburst),
.s_axi_hp0_arlock (axi_hp0_arlock),
.s_axi_hp0_arcache (axi_hp0_arcache),
.s_axi_hp0_arprot (axi_hp0_arprot),
.s_axi_hp0_arvalid (axi_hp0_arvalid),
.s_axi_hp0_arready (axi_hp0_arready),
.s_axi_hp0_rid (),
.s_axi_hp0_rdata (axi_hp0_rdata),
.s_axi_hp0_rresp (axi_hp0_rresp),
.s_axi_hp0_rlast (axi_hp0_rlast),
.s_axi_hp0_rvalid (axi_hp0_rvalid),
.s_axi_hp0_rready (axi_hp0_rready),
.s_axi_hp0_awqos (axi_hp0_awqos),
.s_axi_hp0_arqos (axi_hp0_arqos),
`else
// Disconnect the DMA interface if the associated QSFP port is not used.
.s_axi_hp0_awvalid (1'b0),
.s_axi_hp0_wvalid (1'b0),
.s_axi_hp0_bready (1'b1),
.s_axi_hp0_arvalid (1'b0),
.s_axi_hp0_rready (1'b1),
`endif
.s_axis_eth_dma_tdata (e2h_dma_tdata),
.s_axis_eth_dma_tkeep (e2h_dma_tkeep),
.s_axis_eth_dma_tlast (e2h_dma_tlast),
.s_axis_eth_dma_tready (e2h_dma_tready),
.s_axis_eth_dma_tvalid (e2h_dma_tvalid),
`ifdef QSFP1_0
.s_axi_hp1_aruser (axi_hp1_aruser),
.s_axi_hp1_awuser (axi_hp1_awuser),
.s_axi_hp1_awid (axi_hp1_awid),
.s_axi_hp1_awaddr (axi_hp1_awaddr),
.s_axi_hp1_awlen (axi_hp1_awlen),
.s_axi_hp1_awsize (axi_hp1_awsize),
.s_axi_hp1_awburst (axi_hp1_awburst),
.s_axi_hp1_awlock (axi_hp1_awlock),
.s_axi_hp1_awcache (axi_hp1_awcache),
.s_axi_hp1_awprot (axi_hp1_awprot),
.s_axi_hp1_awvalid (axi_hp1_awvalid),
.s_axi_hp1_awready (axi_hp1_awready),
.s_axi_hp1_wdata (axi_hp1_wdata),
.s_axi_hp1_wstrb (axi_hp1_wstrb),
.s_axi_hp1_wlast (axi_hp1_wlast),
.s_axi_hp1_wvalid (axi_hp1_wvalid),
.s_axi_hp1_wready (axi_hp1_wready),
.s_axi_hp1_bid (),
.s_axi_hp1_bresp (axi_hp1_bresp),
.s_axi_hp1_bvalid (axi_hp1_bvalid),
.s_axi_hp1_bready (axi_hp1_bready),
.s_axi_hp1_arid (axi_hp1_arid),
.s_axi_hp1_araddr (axi_hp1_araddr),
.s_axi_hp1_arlen (axi_hp1_arlen),
.s_axi_hp1_arsize (axi_hp1_arsize),
.s_axi_hp1_arburst (axi_hp1_arburst),
.s_axi_hp1_arlock (axi_hp1_arlock),
.s_axi_hp1_arcache (axi_hp1_arcache),
.s_axi_hp1_arprot (axi_hp1_arprot),
.s_axi_hp1_arvalid (axi_hp1_arvalid),
.s_axi_hp1_arready (axi_hp1_arready),
.s_axi_hp1_rid (),
.s_axi_hp1_rdata (axi_hp1_rdata),
.s_axi_hp1_rresp (axi_hp1_rresp),
.s_axi_hp1_rlast (axi_hp1_rlast),
.s_axi_hp1_rvalid (axi_hp1_rvalid),
.s_axi_hp1_rready (axi_hp1_rready),
.s_axi_hp1_awqos (axi_hp1_awqos),
.s_axi_hp1_arqos (axi_hp1_arqos),
`else
// Disconnect the DMA interface if the associated QSFP port is not used.
.s_axi_hp1_awvalid (1'b0),
.s_axi_hp1_wvalid (1'b0),
.s_axi_hp1_bready (1'b1),
.s_axi_hp1_arvalid (1'b0),
.s_axi_hp1_rready (1'b1),
`endif
.s_axi_hpc0_aruser (),
.s_axi_hpc0_awuser (),
.s_axi_hpc0_awid (),
.s_axi_hpc0_awaddr (),
.s_axi_hpc0_awlen (),
.s_axi_hpc0_awsize (),
.s_axi_hpc0_awburst (),
.s_axi_hpc0_awlock (),
.s_axi_hpc0_awcache (),
.s_axi_hpc0_awprot (),
.s_axi_hpc0_awvalid (),
.s_axi_hpc0_awready (),
.s_axi_hpc0_wdata (),
.s_axi_hpc0_wstrb (),
.s_axi_hpc0_wlast (),
.s_axi_hpc0_wvalid (),
.s_axi_hpc0_wready (),
.s_axi_hpc0_bid (),
.s_axi_hpc0_bresp (),
.s_axi_hpc0_bvalid (),
.s_axi_hpc0_bready (),
.s_axi_hpc0_arid (),
.s_axi_hpc0_araddr (),
.s_axi_hpc0_arlen (),
.s_axi_hpc0_arsize (),
.s_axi_hpc0_arburst (),
.s_axi_hpc0_arlock (),
.s_axi_hpc0_arcache (),
.s_axi_hpc0_arprot (),
.s_axi_hpc0_arvalid (),
.s_axi_hpc0_arready (),
.s_axi_hpc0_rid (),
.s_axi_hpc0_rdata (),
.s_axi_hpc0_rresp (),
.s_axi_hpc0_rlast (),
.s_axi_hpc0_rvalid (),
.s_axi_hpc0_rready (),
.s_axi_hpc0_awqos (),
.s_axi_hpc0_arqos (),
.adc0_clk_clk_n (ADC_CLK_N[0]),
.adc0_clk_clk_p (ADC_CLK_P[0]),
.adc1_clk_clk_n (ADC_CLK_N[0]),
.adc1_clk_clk_p (ADC_CLK_P[0]),
.adc2_clk_clk_n (ADC_CLK_N[2]),
.adc2_clk_clk_p (ADC_CLK_P[2]),
.adc3_clk_clk_n (ADC_CLK_N[2]),
.adc3_clk_clk_p (ADC_CLK_P[2]),
.m_axi_app_awaddr (m_axi_app_awaddr),
.m_axi_app_awprot (m_axi_app_awprot),
.m_axi_app_awvalid (m_axi_app_awvalid),
.m_axi_app_awready (m_axi_app_awready),
.m_axi_app_wdata (m_axi_app_wdata),
.m_axi_app_wstrb (m_axi_app_wstrb),
.m_axi_app_wvalid (m_axi_app_wvalid),
.m_axi_app_wready (m_axi_app_wready),
.m_axi_app_bresp (m_axi_app_bresp),
.m_axi_app_bvalid (m_axi_app_bvalid),
.m_axi_app_bready (m_axi_app_bready),
.m_axi_app_araddr (m_axi_app_araddr),
.m_axi_app_arprot (m_axi_app_arprot),
.m_axi_app_arvalid (m_axi_app_arvalid),
.m_axi_app_arready (m_axi_app_arready),
.m_axi_app_rdata (m_axi_app_rdata),
.m_axi_app_rresp (m_axi_app_rresp),
.m_axi_app_rvalid (m_axi_app_rvalid),
.m_axi_app_rready (m_axi_app_rready),
.dac0_clk_clk_n (DAC_CLK_N[0]),
.dac0_clk_clk_p (DAC_CLK_P[0]),
.dac1_clk_clk_n (DAC_CLK_N[1]),
.dac1_clk_clk_p (DAC_CLK_P[1]),
.gpio_0_tri_i (gpio_0_tri_i),
.gpio_0_tri_o (gpio_0_tri_o),
.gpio_0_tri_t (gpio_0_tri_t),
.m_axi_eth_internal_awaddr (axi_eth_internal_awaddr),
.m_axi_eth_internal_awprot (),
.m_axi_eth_internal_awvalid (axi_eth_internal_awvalid),
.m_axi_eth_internal_awready (axi_eth_internal_awready),
.m_axi_eth_internal_wdata (axi_eth_internal_wdata),
.m_axi_eth_internal_wstrb (axi_eth_internal_wstrb),
.m_axi_eth_internal_wvalid (axi_eth_internal_wvalid),
.m_axi_eth_internal_wready (axi_eth_internal_wready),
.m_axi_eth_internal_bresp (axi_eth_internal_bresp),
.m_axi_eth_internal_bvalid (axi_eth_internal_bvalid),
.m_axi_eth_internal_bready (axi_eth_internal_bready),
.m_axi_eth_internal_araddr (axi_eth_internal_araddr),
.m_axi_eth_internal_arprot (),
.m_axi_eth_internal_arvalid (axi_eth_internal_arvalid),
.m_axi_eth_internal_arready (axi_eth_internal_arready),
.m_axi_eth_internal_rdata (axi_eth_internal_rdata),
.m_axi_eth_internal_rresp (axi_eth_internal_rresp),
.m_axi_eth_internal_rvalid (axi_eth_internal_rvalid),
.m_axi_eth_internal_rready (axi_eth_internal_rready),
.m_axis_eth_dma_tdata (h2e_dma_tdata),
.m_axis_eth_dma_tkeep (h2e_dma_tkeep),
.m_axis_eth_dma_tlast (h2e_dma_tlast),
.m_axis_eth_dma_tready (h2e_dma_tready),
.m_axis_eth_dma_tvalid (h2e_dma_tvalid),
.m_axi_rpu_awaddr (),
.m_axi_rpu_awprot (),
.m_axi_rpu_awvalid (),
.m_axi_rpu_awready (),
.m_axi_rpu_wdata (),
.m_axi_rpu_wstrb (),
.m_axi_rpu_wvalid (),
.m_axi_rpu_wready (),
.m_axi_rpu_bresp (),
.m_axi_rpu_bvalid (),
.m_axi_rpu_bready (),
.m_axi_rpu_araddr (),
.m_axi_rpu_arprot (),
.m_axi_rpu_arvalid (),
.m_axi_rpu_arready (),
.m_axi_rpu_rdata (),
.m_axi_rpu_rresp (),
.m_axi_rpu_rvalid (),
.m_axi_rpu_rready (),
.m_axi_core_awaddr (axi_core_awaddr),
.m_axi_core_awprot (),
.m_axi_core_awvalid (axi_core_awvalid),
.m_axi_core_awready (axi_core_awready),
.m_axi_core_wdata (axi_core_wdata),
.m_axi_core_wstrb (axi_core_wstrb),
.m_axi_core_wvalid (axi_core_wvalid),
.m_axi_core_wready (axi_core_wready),
.m_axi_core_bresp (axi_core_bresp),
.m_axi_core_bvalid (axi_core_bvalid),
.m_axi_core_bready (axi_core_bready),
.m_axi_core_araddr (axi_core_araddr),
.m_axi_core_arprot (),
.m_axi_core_arvalid (axi_core_arvalid),
.m_axi_core_arready (axi_core_arready),
.m_axi_core_rdata (axi_core_rdata),
.m_axi_core_rresp (axi_core_rresp),
.m_axi_core_rvalid (axi_core_rvalid),
.m_axi_core_rready (axi_core_rready),
.m_axi_mpm_ep_awaddr (m_axi_mpm_ep_awaddr),
.m_axi_mpm_ep_awprot (),
.m_axi_mpm_ep_awvalid (m_axi_mpm_ep_awvalid),
.m_axi_mpm_ep_awready (m_axi_mpm_ep_awready),
.m_axi_mpm_ep_wdata (m_axi_mpm_ep_wdata),
.m_axi_mpm_ep_wstrb (m_axi_mpm_ep_wstrb),
.m_axi_mpm_ep_wvalid (m_axi_mpm_ep_wvalid),
.m_axi_mpm_ep_wready (m_axi_mpm_ep_wready),
.m_axi_mpm_ep_bresp (m_axi_mpm_ep_bresp),
.m_axi_mpm_ep_bvalid (m_axi_mpm_ep_bvalid),
.m_axi_mpm_ep_bready (m_axi_mpm_ep_bready),
.m_axi_mpm_ep_araddr (m_axi_mpm_ep_araddr),
.m_axi_mpm_ep_arprot (),
.m_axi_mpm_ep_arvalid (m_axi_mpm_ep_arvalid),
.m_axi_mpm_ep_arready (m_axi_mpm_ep_arready),
.m_axi_mpm_ep_rdata (m_axi_mpm_ep_rdata),
.m_axi_mpm_ep_rresp (m_axi_mpm_ep_rresp),
.m_axi_mpm_ep_rvalid (m_axi_mpm_ep_rvalid),
.m_axi_mpm_ep_rready (m_axi_mpm_ep_rready),
.adc_tile224_ch0_dout_i_tdata (adc_tile_dout_i_tdata[0]),
.adc_tile224_ch0_dout_i_tready (adc_tile_dout_i_tready[0]),
.adc_tile224_ch0_dout_i_tvalid (adc_tile_dout_i_tvalid[0]),
.adc_tile224_ch0_dout_q_tdata (adc_tile_dout_q_tdata[0]),
.adc_tile224_ch0_dout_q_tready (adc_tile_dout_q_tready[0]),
.adc_tile224_ch0_dout_q_tvalid (adc_tile_dout_q_tvalid[0]),
.adc_tile224_ch1_dout_i_tdata (adc_tile_dout_i_tdata[1]),
.adc_tile224_ch1_dout_i_tready (adc_tile_dout_i_tready[1]),
.adc_tile224_ch1_dout_i_tvalid (adc_tile_dout_i_tvalid[1]),
.adc_tile224_ch1_dout_q_tdata (adc_tile_dout_q_tdata[1]),
.adc_tile224_ch1_dout_q_tready (adc_tile_dout_q_tready[1]),
.adc_tile224_ch1_dout_q_tvalid (adc_tile_dout_q_tvalid[1]),
.adc_tile225_ch0_dout_i_tdata (adc_tile_dout_i_tdata[2]),
.adc_tile225_ch0_dout_i_tready (adc_tile_dout_i_tready[2]),
.adc_tile225_ch0_dout_i_tvalid (adc_tile_dout_i_tvalid[2]),
.adc_tile225_ch0_dout_q_tdata (adc_tile_dout_q_tdata[2]),
.adc_tile225_ch0_dout_q_tready (adc_tile_dout_q_tready[2]),
.adc_tile225_ch0_dout_q_tvalid (adc_tile_dout_q_tvalid[2]),
.adc_tile225_ch1_dout_i_tdata (adc_tile_dout_i_tdata[3]),
.adc_tile225_ch1_dout_i_tready (adc_tile_dout_i_tready[3]),
.adc_tile225_ch1_dout_i_tvalid (adc_tile_dout_i_tvalid[3]),
.adc_tile225_ch1_dout_q_tdata (adc_tile_dout_q_tdata[3]),
.adc_tile225_ch1_dout_q_tready (adc_tile_dout_q_tready[3]),
.adc_tile225_ch1_dout_q_tvalid (adc_tile_dout_q_tvalid[3]),
.adc_tile226_ch0_dout_i_tdata (adc_tile_dout_i_tdata[4]),
.adc_tile226_ch0_dout_i_tready (adc_tile_dout_i_tready[4]),
.adc_tile226_ch0_dout_i_tvalid (adc_tile_dout_i_tvalid[4]),
.adc_tile226_ch0_dout_q_tdata (adc_tile_dout_q_tdata[4]),
.adc_tile226_ch0_dout_q_tready (adc_tile_dout_q_tready[4]),
.adc_tile226_ch0_dout_q_tvalid (adc_tile_dout_q_tvalid[4]),
.adc_tile226_ch1_dout_i_tdata (adc_tile_dout_i_tdata[5]),
.adc_tile226_ch1_dout_i_tready (adc_tile_dout_i_tready[5]),
.adc_tile226_ch1_dout_i_tvalid (adc_tile_dout_i_tvalid[5]),
.adc_tile226_ch1_dout_q_tdata (adc_tile_dout_q_tdata[5]),
.adc_tile226_ch1_dout_q_tready (adc_tile_dout_q_tready[5]),
.adc_tile226_ch1_dout_q_tvalid (adc_tile_dout_q_tvalid[5]),
.adc_tile227_ch0_dout_i_tdata (adc_tile_dout_i_tdata[6]),
.adc_tile227_ch0_dout_i_tready (adc_tile_dout_i_tready[6]),
.adc_tile227_ch0_dout_i_tvalid (adc_tile_dout_i_tvalid[6]),
.adc_tile227_ch0_dout_q_tdata (adc_tile_dout_q_tdata[6]),
.adc_tile227_ch0_dout_q_tready (adc_tile_dout_q_tready[6]),
.adc_tile227_ch0_dout_q_tvalid (adc_tile_dout_q_tvalid[6]),
.adc_tile227_ch1_dout_i_tdata (adc_tile_dout_i_tdata[7]),
.adc_tile227_ch1_dout_i_tready (adc_tile_dout_i_tready[7]),
.adc_tile227_ch1_dout_i_tvalid (adc_tile_dout_i_tvalid[7]),
.adc_tile227_ch1_dout_q_tdata (adc_tile_dout_q_tdata[7]),
.adc_tile227_ch1_dout_q_tready (adc_tile_dout_q_tready[7]),
.adc_tile227_ch1_dout_q_tvalid (adc_tile_dout_q_tvalid[7]),
.dac_tile228_ch0_vout_v_n (DB0_TX_N[0]),
.dac_tile228_ch0_vout_v_p (DB0_TX_P[0]),
.dac_tile228_ch1_vout_v_n (DB0_TX_N[1]),
.dac_tile228_ch1_vout_v_p (DB0_TX_P[1]),
.dac_tile228_ch2_vout_v_n (DB0_TX_N[2]),
.dac_tile228_ch2_vout_v_p (DB0_TX_P[2]),
.dac_tile228_ch3_vout_v_n (DB0_TX_N[3]),
.dac_tile228_ch3_vout_v_p (DB0_TX_P[3]),
.dac_tile229_ch0_vout_v_n (DB1_TX_N[0]),
.dac_tile229_ch0_vout_v_p (DB1_TX_P[0]),
.dac_tile229_ch1_vout_v_n (DB1_TX_N[1]),
.dac_tile229_ch1_vout_v_p (DB1_TX_P[1]),
.dac_tile229_ch2_vout_v_n (DB1_TX_N[2]),
.dac_tile229_ch2_vout_v_p (DB1_TX_P[2]),
.dac_tile229_ch3_vout_v_n (DB1_TX_N[3]),
.dac_tile229_ch3_vout_v_p (DB1_TX_P[3]),
.dac_tile228_ch0_din_tdata (dac_tile_din_tdata[0]),
.dac_tile228_ch0_din_tvalid (dac_tile_din_tvalid[0]),
.dac_tile228_ch0_din_tready (dac_tile_din_tready[0]),
.dac_tile228_ch1_din_tdata (dac_tile_din_tdata[1]),
.dac_tile228_ch1_din_tvalid (dac_tile_din_tvalid[1]),
.dac_tile228_ch1_din_tready (dac_tile_din_tready[1]),
.dac_tile228_ch2_din_tdata (dac_tile_din_tdata[2]),
.dac_tile228_ch2_din_tvalid (dac_tile_din_tvalid[2]),
.dac_tile228_ch2_din_tready (dac_tile_din_tready[2]),
.dac_tile228_ch3_din_tdata (dac_tile_din_tdata[3]),
.dac_tile228_ch3_din_tvalid (dac_tile_din_tvalid[3]),
.dac_tile228_ch3_din_tready (dac_tile_din_tready[3]),
.dac_tile229_ch0_din_tdata (dac_tile_din_tdata[4]),
.dac_tile229_ch0_din_tvalid (dac_tile_din_tvalid[4]),
.dac_tile229_ch0_din_tready (dac_tile_din_tready[4]),
.dac_tile229_ch1_din_tdata (dac_tile_din_tdata[5]),
.dac_tile229_ch1_din_tvalid (dac_tile_din_tvalid[5]),
.dac_tile229_ch1_din_tready (dac_tile_din_tready[5]),
.dac_tile229_ch2_din_tdata (dac_tile_din_tdata[6]),
.dac_tile229_ch2_din_tvalid (dac_tile_din_tvalid[6]),
.dac_tile229_ch2_din_tready (dac_tile_din_tready[6]),
.dac_tile229_ch3_din_tdata (dac_tile_din_tdata[7]),
.dac_tile229_ch3_din_tvalid (dac_tile_din_tvalid[7]),
.dac_tile229_ch3_din_tready (dac_tile_din_tready[7]),
.s_axi_hpc1_awid (),
.s_axi_hpc1_awaddr (),
.s_axi_hpc1_awlen (),
.s_axi_hpc1_awsize (),
.s_axi_hpc1_awburst (),
.s_axi_hpc1_awlock (),
.s_axi_hpc1_awcache (),
.s_axi_hpc1_awprot (),
.s_axi_hpc1_awqos (),
.s_axi_hpc1_awvalid (),
.s_axi_hpc1_awready (),
.s_axi_hpc1_wdata (),
.s_axi_hpc1_wstrb (),
.s_axi_hpc1_wlast (),
.s_axi_hpc1_wvalid (),
.s_axi_hpc1_wready (),
.s_axi_hpc1_bid (),
.s_axi_hpc1_bresp (),
.s_axi_hpc1_bvalid (),
.s_axi_hpc1_bready (),
.s_axi_hpc1_arid (),
.s_axi_hpc1_araddr (),
.s_axi_hpc1_arlen (),
.s_axi_hpc1_arsize (),
.s_axi_hpc1_arburst (),
.s_axi_hpc1_arlock (),
.s_axi_hpc1_arcache (),
.s_axi_hpc1_arprot (),
.s_axi_hpc1_arqos (),
.s_axi_hpc1_arvalid (),
.s_axi_hpc1_arready (),
.s_axi_hpc1_rid (),
.s_axi_hpc1_rdata (),
.s_axi_hpc1_rresp (),
.s_axi_hpc1_rlast (),
.s_axi_hpc1_rvalid (),
.s_axi_hpc1_rready (),
.sysref_rf_in_diff_n (SYSREF_RF_N),
.sysref_rf_in_diff_p (SYSREF_RF_P),
.adc_tile224_ch0_vin_v_n (DB0_RX_N[0]),
.adc_tile224_ch0_vin_v_p (DB0_RX_P[0]),
.adc_tile224_ch1_vin_v_n (DB0_RX_N[1]),
.adc_tile224_ch1_vin_v_p (DB0_RX_P[1]),
.adc_tile225_ch0_vin_v_n (DB0_RX_N[2]),
.adc_tile225_ch0_vin_v_p (DB0_RX_P[2]),
.adc_tile225_ch1_vin_v_n (DB0_RX_N[3]),
.adc_tile225_ch1_vin_v_p (DB0_RX_P[3]),
.adc_tile226_ch0_vin_v_n (DB1_RX_N[0]),
.adc_tile226_ch0_vin_v_p (DB1_RX_P[0]),
.adc_tile226_ch1_vin_v_n (DB1_RX_N[1]),
.adc_tile226_ch1_vin_v_p (DB1_RX_P[1]),
.adc_tile227_ch0_vin_v_n (DB1_RX_N[2]),
.adc_tile227_ch0_vin_v_p (DB1_RX_P[2]),
.adc_tile227_ch1_vin_v_n (DB1_RX_N[3]),
.adc_tile227_ch1_vin_v_p (DB1_RX_P[3]),
.s_axi_hpc1_aruser (),
.s_axi_hpc1_awuser (),
.clk_adc0 ()
);
`endif
@@ -1672,7 +2164,152 @@ module x4xx (
end // gen_rf_core_full
end // gen_rf_cores
`ifdef X410
`ifdef X440
wire [NUM_DBOARDS-1:0] sync_clk;
// Import LED register offsets in MB CPLD
`include "cpld/regmap/x440/mb_cpld_pl_regmap_utils.vh"
`include "regmap/pl_cpld_regmap_utils.vh"
for ( db_i = 0; db_i < (NUM_DBOARDS); db_i = db_i + 1) begin : db_gpio_gen
localparam LED_REGISTER_ADDRESS = (db_i == 0) ? MB_CPLD + PL_DB0_LED_REGISTERS
: (db_i == 1) ? MB_CPLD + PL_DB1_LED_REGISTERS
: 0;
db_gpio_interface#(
.LED_REGISTER_ADDRESS (LED_REGISTER_ADDRESS)
) db_gpio_interface_i (
.radio_clk (radio_clk[db_i]),
.pll_ref_clk (pll_ref_clk),
.db_state (db_state[db_i]),
.in_sync_clk (clk5),
.out_sync_clk (sync_clk[db_i]),
.ctrlport_rst (radio_rst[db_i]),
.s_ctrlport_req_wr (db_ctrlport_req_wr[db_i]),
.s_ctrlport_req_rd (db_ctrlport_req_rd[db_i]),
.s_ctrlport_req_addr (db_ctrlport_req_addr[db_i]),
.s_ctrlport_req_data (db_ctrlport_req_data[db_i]),
.s_ctrlport_resp_ack (db_ctrlport_resp_ack[db_i]),
.s_ctrlport_resp_status (db_ctrlport_resp_status[db_i]),
.s_ctrlport_resp_data (db_ctrlport_resp_data[db_i]),
.m_ctrlport_req_wr (db_to_cpld_ctrlport_req_wr[db_i]),
.m_ctrlport_req_rd (db_to_cpld_ctrlport_req_rd[db_i]),
.m_ctrlport_req_addr (db_to_cpld_ctrlport_req_addr[db_i]),
.m_ctrlport_req_data (db_to_cpld_ctrlport_req_data[db_i]),
.m_ctrlport_req_byte_en (db_to_cpld_ctrlport_req_byte_en[db_i]),
.m_ctrlport_resp_ack (db_to_cpld_ctrlport_resp_ack[db_i]),
.m_ctrlport_resp_status (db_to_cpld_ctrlport_resp_status[db_i]),
.m_ctrlport_resp_data (db_to_cpld_ctrlport_resp_data[db_i]),
.gpio_in (db_gpio_in_int[db_i]),
.gpio_out (db_gpio_out_int[db_i]),
.gpio_out_en (db_gpio_out_en_int[db_i]),
.version_info (db_gpio_ifc_version[db_i])
);
end
// The sync_clk flip-flop is driven in single-ended mode. The _n side is
// set statically via a voltage divider with DB0_GPIO[12] and
// DB1_GPIO[16] providing the source voltages.
assign DB0_GPIO[12] = 1'b1;
assign DB0_GPIO[13] = sync_clk[0];
assign DB1_GPIO[16] = 1'b1;
assign DB1_GPIO[17] = sync_clk[1];
// GPIO to CPLD ctrlport interface for db1 and radio_clk[0]
wire db1_to_cpld_radio0_ctrlport_req_rd;
wire db1_to_cpld_radio0_ctrlport_req_wr;
wire [19:0] db1_to_cpld_radio0_ctrlport_req_addr;
wire [31:0] db1_to_cpld_radio0_ctrlport_req_data;
wire [ 3:0] db1_to_cpld_radio0_ctrlport_req_byte_en;
wire db1_to_cpld_radio0_ctrlport_req_has_time;
wire [63:0] db1_to_cpld_radio0_ctrlport_req_time;
wire db1_to_cpld_radio0_ctrlport_resp_ack;
wire [31:0] db1_to_cpld_radio0_ctrlport_resp_data;
wire [ 1:0] db1_to_cpld_radio0_ctrlport_resp_status;
// Need to cross clocks from radio_clk[1] to radio_clk[0] to combine the
// ctrlport buses.
ctrlport_clk_cross ctrlport_clk_cross_i (
.rst (radio_rst[1]),
.s_ctrlport_clk (radio_clk[1]),
.s_ctrlport_req_wr (db_to_cpld_ctrlport_req_wr[1]),
.s_ctrlport_req_rd (db_to_cpld_ctrlport_req_rd[1]),
.s_ctrlport_req_addr (db_to_cpld_ctrlport_req_addr[1]),
.s_ctrlport_req_portid (),
.s_ctrlport_req_rem_epid (),
.s_ctrlport_req_rem_portid (),
.s_ctrlport_req_data (db_to_cpld_ctrlport_req_data[1]),
.s_ctrlport_req_byte_en (db_to_cpld_ctrlport_req_byte_en[1]),
.s_ctrlport_req_has_time (),
.s_ctrlport_req_time (),
.s_ctrlport_resp_ack (db_to_cpld_ctrlport_resp_ack[1]),
.s_ctrlport_resp_status (db_to_cpld_ctrlport_resp_status[1]),
.s_ctrlport_resp_data (db_to_cpld_ctrlport_resp_data[1]),
.m_ctrlport_clk (radio_clk[0]),
.m_ctrlport_req_wr (db1_to_cpld_radio0_ctrlport_req_wr),
.m_ctrlport_req_rd (db1_to_cpld_radio0_ctrlport_req_rd),
.m_ctrlport_req_addr (db1_to_cpld_radio0_ctrlport_req_addr),
.m_ctrlport_req_portid (),
.m_ctrlport_req_rem_epid (),
.m_ctrlport_req_rem_portid (),
.m_ctrlport_req_data (db1_to_cpld_radio0_ctrlport_req_data),
.m_ctrlport_req_byte_en (db1_to_cpld_radio0_ctrlport_req_byte_en),
.m_ctrlport_req_has_time (),
.m_ctrlport_req_time (),
.m_ctrlport_resp_ack (db1_to_cpld_radio0_ctrlport_resp_ack),
.m_ctrlport_resp_status (db1_to_cpld_radio0_ctrlport_resp_status),
.m_ctrlport_resp_data (db1_to_cpld_radio0_ctrlport_resp_data)
);
// after both ctrlport buses are on radio_clk[0], combine them to go
// into cpld_interface
ctrlport_combiner #(
.NUM_MASTERS (NUM_DBOARDS),
.PRIORITY (0)
) ctrlport_combiner_db_i (
.ctrlport_clk (radio_clk[0]),
.ctrlport_rst (radio_rst[0]),
.s_ctrlport_req_wr ({db1_to_cpld_radio0_ctrlport_req_wr,db_to_cpld_ctrlport_req_wr[0]}),
.s_ctrlport_req_rd ({db1_to_cpld_radio0_ctrlport_req_rd,db_to_cpld_ctrlport_req_rd[0]}),
.s_ctrlport_req_addr ({db1_to_cpld_radio0_ctrlport_req_addr,db_to_cpld_ctrlport_req_addr[0]}),
.s_ctrlport_req_portid (),
.s_ctrlport_req_rem_epid (),
.s_ctrlport_req_rem_portid (),
.s_ctrlport_req_data ({db1_to_cpld_radio0_ctrlport_req_data,db_to_cpld_ctrlport_req_data[0]}),
.s_ctrlport_req_byte_en ({db1_to_cpld_radio0_ctrlport_req_byte_en,db_to_cpld_ctrlport_req_byte_en[0]}),
.s_ctrlport_req_has_time (),
.s_ctrlport_req_time (),
.s_ctrlport_resp_ack ({db1_to_cpld_radio0_ctrlport_resp_ack,db_to_cpld_ctrlport_resp_ack[0]}),
.s_ctrlport_resp_status ({db1_to_cpld_radio0_ctrlport_resp_status,db_to_cpld_ctrlport_resp_status[0]}),
.s_ctrlport_resp_data ({db1_to_cpld_radio0_ctrlport_resp_data,db_to_cpld_ctrlport_resp_data[0]}),
.m_ctrlport_req_wr (db_to_cpld_comb_ctrlport_req_wr),
.m_ctrlport_req_rd (db_to_cpld_comb_ctrlport_req_rd),
.m_ctrlport_req_addr (db_to_cpld_comb_ctrlport_req_addr),
.m_ctrlport_req_portid (),
.m_ctrlport_req_rem_epid (),
.m_ctrlport_req_rem_portid (),
.m_ctrlport_req_data (db_to_cpld_comb_ctrlport_req_data),
.m_ctrlport_req_byte_en (db_to_cpld_comb_ctrlport_req_byte_en),
.m_ctrlport_req_has_time (db_to_cpld_comb_ctrlport_req_has_time),
.m_ctrlport_req_time (db_to_cpld_comb_ctrlport_req_time),
.m_ctrlport_resp_ack (db_to_cpld_comb_ctrlport_resp_ack),
.m_ctrlport_resp_status (db_to_cpld_comb_ctrlport_resp_status),
.m_ctrlport_resp_data (db_to_cpld_comb_ctrlport_resp_data)
);
// on X440, some gpio are used to drive sync clk, and not tri-state.
for (db_gpio_i = 0; db_gpio_i < 20; db_gpio_i = db_gpio_i + 1) begin: db_gpio_tristate_gen
if (db_gpio_i != 12 || db_gpio_i != 13) begin
assign DB0_GPIO[db_gpio_i] = (db_gpio_out_en_ext[0][db_gpio_i]) ? db_gpio_out_ext[0][db_gpio_i] : 1'bz;
end
if (db_gpio_i != 16 || db_gpio_i != 17) begin
assign DB1_GPIO[db_gpio_i] = (db_gpio_out_en_ext[1][db_gpio_i]) ? db_gpio_out_ext[1][db_gpio_i] : 1'bz;
end
end
`else // X410
for ( db_i = 0; db_i < (NUM_DBOARDS); db_i = db_i + 1) begin : db_gpio_gen
db_gpio_interface db_gpio_interface_i (
@@ -2213,7 +2850,38 @@ module x4xx (
wire mfg_test_en_gty_rcv_clk;
// Map RFDC ports to x4xx_core ports
`ifdef X410
`ifdef X440
`include "regmap/x440/rfdc_mapping_regmap_utils.vh"
assign rx_data_qi = { adc_data_out_tdata [CH7_RX_MAPPING], adc_data_out_tdata [CH6_RX_MAPPING],
adc_data_out_tdata [CH5_RX_MAPPING], adc_data_out_tdata [CH4_RX_MAPPING],
adc_data_out_tdata [CH3_RX_MAPPING], adc_data_out_tdata [CH2_RX_MAPPING],
adc_data_out_tdata [CH1_RX_MAPPING], adc_data_out_tdata [CH0_RX_MAPPING] };
assign rx_stb = { adc_data_out_tvalid[CH7_RX_MAPPING], adc_data_out_tvalid[CH6_RX_MAPPING],
adc_data_out_tvalid[CH5_RX_MAPPING], adc_data_out_tvalid[CH4_RX_MAPPING],
adc_data_out_tvalid[CH3_RX_MAPPING], adc_data_out_tvalid[CH2_RX_MAPPING],
adc_data_out_tvalid[CH1_RX_MAPPING], adc_data_out_tvalid[CH0_RX_MAPPING] };
assign { dac_data_in_tdata[CH7_TX_MAPPING], dac_data_in_tdata[CH6_TX_MAPPING],
dac_data_in_tdata[CH5_TX_MAPPING], dac_data_in_tdata[CH4_TX_MAPPING],
dac_data_in_tdata[CH3_TX_MAPPING], dac_data_in_tdata[CH2_TX_MAPPING],
dac_data_in_tdata[CH1_TX_MAPPING], dac_data_in_tdata[CH0_TX_MAPPING] } = tx_data_qi;
assign { tx_stb [CH7_TX_MAPPING], tx_stb [CH6_TX_MAPPING],
tx_stb [CH5_TX_MAPPING], tx_stb [CH4_TX_MAPPING],
tx_stb [CH3_TX_MAPPING], tx_stb [CH2_TX_MAPPING],
tx_stb [CH1_TX_MAPPING], tx_stb [CH0_TX_MAPPING] } = dac_data_in_tready;
assign { swapped_invert_adc_iq_rclk2[CH7_RX_MAPPING], swapped_invert_adc_iq_rclk2[CH6_RX_MAPPING],
swapped_invert_adc_iq_rclk2[CH5_RX_MAPPING], swapped_invert_adc_iq_rclk2[CH4_RX_MAPPING],
swapped_invert_adc_iq_rclk2[CH3_RX_MAPPING], swapped_invert_adc_iq_rclk2[CH2_RX_MAPPING],
swapped_invert_adc_iq_rclk2[CH1_RX_MAPPING], swapped_invert_adc_iq_rclk2[CH0_RX_MAPPING] } = invert_adc_iq_rclk2;
assign { swapped_invert_dac_iq_rclk2[CH7_TX_MAPPING], swapped_invert_dac_iq_rclk2[CH6_TX_MAPPING],
swapped_invert_dac_iq_rclk2[CH5_TX_MAPPING], swapped_invert_dac_iq_rclk2[CH4_TX_MAPPING],
swapped_invert_dac_iq_rclk2[CH3_TX_MAPPING], swapped_invert_dac_iq_rclk2[CH2_TX_MAPPING],
swapped_invert_dac_iq_rclk2[CH1_TX_MAPPING], swapped_invert_dac_iq_rclk2[CH0_TX_MAPPING] } = invert_dac_iq_rclk2;
`else // X410
// IMPORTANT! For ZBX RevB, there is a RX channel swap in layout
// that we need to correct for here in HDL.
assign rx_data_qi = { adc_data_out_tdata [2], adc_data_out_tdata [3],
@@ -2507,6 +3175,13 @@ endmodule
// </info>
//</top>
//
//<top name="X440_FPGA">
// <info>
// This map contains register windows for controlling the different sources
// that drive the state of FBX control lines.
// </info>
//</top>
//
//<regmap name="VERSIONING_REGS_REGMAP">
// <group name="VERSIONING_CONSTANTS">
// <enumeratedtype name="FPGA_VERSION" showhex="true">