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fpga: Add X440/FBX support

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Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>


Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
This commit is contained in:
Javier Valenzuela
2023-06-12 10:27:29 -05:00
committed by Aki Tomita
co-authored by Martin Braun Wade Fife Ryan Marlow
parent a405111ce7
commit 5cadf901c7
121 changed files with 20670 additions and 8739 deletions
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top/x400/rf/x440/x440_rfdc_tx_control_remap.v
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//
// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: x440_rfdc_tx_control_remap.v
// Description:
// Allows for remapping control signals to the correct tile on X440.
// This file targets the DAC tiles specifically
//
`default_nettype none
module x440_rfdc_tx_control_remap (
// Input control (Front-Panel ordering)
input wire [7:0] input_controls,
// output_control (DAC Tile ordering)
output wire [7:0] output_controls
);
`include "../../regmap/x440/rfdc_mapping_regmap_utils.vh"
// Decode TX Channel mapping
assign output_controls[CH0_TX_MAPPING] = input_controls[0];
assign output_controls[CH1_TX_MAPPING] = input_controls[1];
assign output_controls[CH2_TX_MAPPING] = input_controls[2];
assign output_controls[CH3_TX_MAPPING] = input_controls[3];
assign output_controls[CH4_TX_MAPPING] = input_controls[4];
assign output_controls[CH5_TX_MAPPING] = input_controls[5];
assign output_controls[CH6_TX_MAPPING] = input_controls[6];
assign output_controls[CH7_TX_MAPPING] = input_controls[7];
endmodule
`default_nettype wire