fpga: Add X440/FBX support
Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
This commit is contained in:
Javier Valenzuela
committed by
Aki Tomita
Aki Tomita
co-authored by
Martin Braun
Wade Fife
Ryan Marlow
Martin Braun
Wade Fife
Ryan Marlow
parent
a405111ce7
commit
5cadf901c7
@@ -0,0 +1,261 @@
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--
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-- Copyright 2022 Ettus Research, a National Instruments Brand
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--
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-- SPDX-License-Identifier: LGPL-3.0-or-later
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--
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-- Module: x440_clock_gates
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--
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-- Description:
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--
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-- Gate propagation of RfdcClk instances until the PLL lock
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-- status signal is stable and software has acknowledged it by asserting the
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-- pertinent controls.
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--
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-- RfdcClks are used on other Xilinx IP components in the Board Design, and
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-- Vivado fails to detect their frequency correctly their buffer is
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-- explicitly instantiated in the Block Design. Therefore, we only generate
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-- the buffer enable signals for these clocks within this component.
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--
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-- This file heavily leverages the code from '../x410/x410_clock_gates.vhd'.
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-- The main changes when comparing against that file are:
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-- - One RFDC Clock pair per radio.
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-- - No DataClk buffer instantiations (since DataClk is removed from BD).
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--
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-- Parameters:
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--
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-- kReliableClkPeriodNs: Clock period (ns) for ReliableClk.
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--
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library IEEE;
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use IEEE.std_logic_1164.ALL;
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use IEEE.numeric_std.ALL;
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library UNISIM;
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use UNISIM.Vcomponents.ALL;
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library WORK;
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use WORK.PkgRFDC_REGS_REGMAP.all;
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entity x440_clock_gates is
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generic (
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kReliableClkPeriodNs : integer := 25
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);
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port (
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-- MMCM reset
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-- This clock will be asserted via AXI access before any clocking
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-- configuration done, signals coming into this component will not change
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-- immediately after this reset is de-asserted.
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rPllReset_n : in std_logic;
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aPllLocked : in std_logic;
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-- Input Clocks (from MMCM)
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ReliableClk : in std_logic;
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-- Buffers for these signals must be instantiated on Block design for clock
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-- rates to be identified. The Utility Buffers instantiated on the Block
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-- Design require signals to be of type std_logic_vector.
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aEnableRf0Bufg1x : out std_logic_vector(0 downto 0);
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aEnableRf0Bufg2x : out std_logic_vector(0 downto 0);
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aEnableRf1Bufg1x : out std_logic_vector(0 downto 0);
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aEnableRf1Bufg2x : out std_logic_vector(0 downto 0);
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-- PLL Status Signals
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rPllLocked : out std_logic;
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-- Window Interface
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rSafeToEnableGatedClks : in std_logic;
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rGatedBaseClksValid : out std_logic;
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-- AXI GPIO interface
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rSoftwareControl : in std_logic_vector(31 downto 0);
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rSoftwareStatus : out std_logic_vector(31 downto 0)
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);
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end x440_clock_gates;
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architecture STRUCT of x440_clock_gates is
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component sync_wrapper
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generic (
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WIDTH : integer := 1;
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STAGES : integer := 2;
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INITIAL_VAL : integer := 0;
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FALSE_PATH_TO_IN : integer := 1);
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port (
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clk : in std_logic;
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rst : in std_logic;
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signal_in : in std_logic_vector((WIDTH-1) downto 0);
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signal_out : out std_logic_vector((WIDTH-1) downto 0));
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end component;
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-- UltraScale MMCM max lock time = 100 us / 25 ns = 4,000 clk cycles. If the
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-- division kPllLockTimeNs / kReliableClkPeriodNs does not evaluate to an
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-- integer, Vivado could either round up or down. In case they round down, we
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-- add '1' to the result to ensure we have the full lock time accounted for.
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-- In this case, it is better to count 1 more than necessary than kill the
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-- process prematurely.
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constant kPllLockTimeNs : integer := 100000;
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constant kMaxPllLockCount : integer := kPllLockTimeNs / kReliableClkPeriodNs + 1;
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signal rLockedFilterCount : integer range 0 to kMaxPllLockCount-1 := kMaxPllLockCount-1;
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signal rClearDataClkUnlockedSticky : std_logic;
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-----------------------------------------------------------------------------
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-- PLL locked signals
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-----------------------------------------------------------------------------
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-- Synchronizer signals
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signal aPllLockedLcl : std_logic_vector(0 downto 0);
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signal rPllLockedDs : std_logic_vector(0 downto 0) := (others => '0');
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-- Lock status indicators
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signal rPllLockedLcl : std_logic := '0';
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signal rPllUnlockedSticky : std_logic := '0';
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-- Safe BUFG enable signals
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signal rEnableRfdc0Clk1x,
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rEnableRfdc0Clk2x,
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rEnableRfdc1Clk1x,
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rEnableRfdc1Clk2x : std_logic;
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signal rEnableRfdc0Bufg1xLcl : std_logic := '0';
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signal rEnableRfdc0Bufg2xLcl : std_logic := '0';
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signal rEnableRfdc1Bufg1xLcl : std_logic := '0';
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signal rEnableRfdc1Bufg2xLcl : std_logic := '0';
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-- Active high version of reset required for synchronizer blocks.
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signal rPllReset : std_logic;
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-- Since these signals control sensitive components (clock enables), we apply
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-- a dont_touch attribute to preserve the signals through both synthesis and
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-- P&R. Implementation of "dont_touch" has been confirmed after P&R.
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attribute dont_touch : string;
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attribute dont_touch of aEnableRf0Bufg1x : signal is "TRUE";
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attribute dont_touch of aEnableRf0Bufg2x : signal is "TRUE";
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attribute dont_touch of aEnableRf1Bufg1x : signal is "TRUE";
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attribute dont_touch of aEnableRf1Bufg2x : signal is "TRUE";
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begin
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rPllReset <= not rPllReset_n;
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-- Assert rGatedBaseClksValid once the PLL has been locked for the specified
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-- time.
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rGatedBaseClksValid <= rPllLockedLcl;
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DataClkEnables : process(ReliableClk)
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begin
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if rising_edge(ReliableClk) then
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if rPllReset_n = '0' then
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rEnableRfdc0Bufg1xLcl <= '0';
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rEnableRfdc0Bufg2xLcl <= '0';
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rEnableRfdc1Bufg1xLcl <= '0';
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rEnableRfdc1Bufg2xLcl <= '0';
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else
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rEnableRfdc0Bufg1xLcl <=
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rSafeToEnableGatedClks and
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rEnableRfdc0Clk1x and
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(not rPllUnlockedSticky);
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rEnableRfdc0Bufg2xLcl <=
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rSafeToEnableGatedClks and
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rEnableRfdc0Clk2x and
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(not rPllUnlockedSticky);
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rEnableRfdc1Bufg1xLcl <=
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rSafeToEnableGatedClks and
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rEnableRfdc1Clk1x and
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(not rPllUnlockedSticky);
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rEnableRfdc1Bufg2xLcl <=
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rSafeToEnableGatedClks and
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rEnableRfdc1Clk2x and
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(not rPllUnlockedSticky);
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end if;
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end if;
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end process DataClkEnables;
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aEnableRf0Bufg1x(0) <= rEnableRfdc0Bufg1xLcl;
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aEnableRf0Bufg2x(0) <= rEnableRfdc0Bufg2xLcl;
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aEnableRf1Bufg1x(0) <= rEnableRfdc1Bufg1xLcl;
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aEnableRf1Bufg2x(0) <= rEnableRfdc1Bufg2xLcl;
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-----------------------------------------------------------------------------
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-- Create PLL Lock Signal
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-----------------------------------------------------------------------------
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-- Double-sync the incoming aPllLocked signal from the PLL.
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aPllLockedLcl(0) <= aPllLocked;
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DataClkPllLockedDS: sync_wrapper
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generic map (
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WIDTH => 1,
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STAGES => open,
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INITIAL_VAL => open,
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FALSE_PATH_TO_IN => open)
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port map (
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clk => ReliableClk,
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rst => rPllReset,
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signal_in => aPllLockedLcl,
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signal_out => rPllLockedDs
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);
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-- Filter the Lock signal. Assert a lock when the PLL lock signal has been
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-- asserted for kPllLockTimeNs
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--
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-- !!! SAFE COUNTER STARTUP !!!
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-- rLockedFilterCount cannot start incrementing until rPllReset_n is
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-- de-asserted. Once rPllReset_n is de-asserted through a AXI access, input
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-- values for the registers in this state machine will not change until the
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-- MMCM locks and the double synchronizer reflects a locked status, making
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-- this start-up safe.
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PllLockFilter: process (ReliableClk)
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begin
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if rising_edge(ReliableClk) then
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if rPllReset_n = '0' then
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rLockedFilterCount <= kMaxPllLockCount-1;
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rPllLockedLcl <= '0';
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else
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if rPllLockedDs(0) = '1' then
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if rLockedFilterCount = 0 then
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rPllLockedLcl <= '1';
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else
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rPllLockedLcl <= '0';
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rLockedFilterCount <= rLockedFilterCount - 1;
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end if;
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else
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rLockedFilterCount <= kMaxPllLockCount-1;
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rPllLockedLcl <= '0';
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end if;
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end if;
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end if;
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end process PllLockFilter;
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-- Sticky bit to hold '1' if PLL ever comes unlocked
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PllStickyBit: process (ReliableClk)
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begin
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if rising_edge(ReliableClk) then
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if (not rPllReset_n or rClearDataClkUnlockedSticky) = '1' then
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rPllUnlockedSticky <= '0';
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else
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if rPllLockedLcl = '1' and rPllLockedDs(0) = '0' then
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rPllUnlockedSticky <= '1';
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end if;
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end if;
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end if;
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end process;
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rPllLocked <= rPllLockedLcl;
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-- AXI transaction decoding
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rClearDataClkUnlockedSticky <= rSoftwareControl(kCLEAR_DATA_CLK_UNLOCKED);
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rEnableRfdc0Clk1x <= rSoftwareControl(kENABLE_RF0_CLK);
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rEnableRfdc0Clk2x <= rSoftwareControl(kENABLE_RF0_CLK_2X);
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rEnableRfdc1Clk1x <= rSoftwareControl(kENABLE_RF1_CLK);
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rEnableRfdc1Clk2x <= rSoftwareControl(kENABLE_RF1_CLK_2X);
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rSoftwareStatus(kDATA_CLK_PLL_LOCKED) <= rPllLockedLcl;
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rSoftwareStatus(kDATA_CLK_PLL_UNLOCKED_STICKY) <= rPllUnlockedSticky;
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end STRUCT;
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@@ -0,0 +1,189 @@
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--
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-- Copyright 2022 Ettus Research, a National Instruments Brand
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--
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-- SPDX-License-Identifier: LGPL-3.0-or-later
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--
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-- Module: x440_rf_reset_controller
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--
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-- Description:
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--
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-- Control RFDC, ADC, and DAC resets.
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-- This file contains a similar structure to '../x410/x410_rf_reset_controller',
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-- with the main difference of not having to support a complex reset chain.
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-- This means that the instantiations of 'rf_reset' can be taken out in favor
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-- having a simple combination of the incoming pulses and the software triggers
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-- to generate the different outputs.
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library WORK;
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use WORK.PkgRFDC_REGS_REGMAP.all;
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entity x440_rf_reset_controller is
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port(
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-- Clocks
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-- Config clock is async to all the others.
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ConfigClk : in std_logic;
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PllRefClk : in std_logic;
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RfClk : in std_logic;
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RfClk2x : in std_logic;
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-- Master resets from the Radio
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rAdcResetPulse : in std_logic;
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rDacResetPulse : in std_logic;
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-- ADC Resets
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r2AdcReset_n : out std_logic;
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rAdcEnableData : out std_logic;
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rAdcReset_n : out std_logic;
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-- DAC Resets
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r2DacReset_n : out std_logic;
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rDacReset_n : out std_logic;
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-- SW Control and Status
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-- Control to initiate resets to RFDC.
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-- The reset status is a sticky status of both ADC and DAC.
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cSoftwareControl : in std_logic_vector(31 downto 0);
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cSoftwareStatus : out std_logic_vector(31 downto 0)
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);
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end x440_rf_reset_controller;
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architecture RTL of x440_rf_reset_controller is
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-- POR value for all resets are high.
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signal cTriggerAdcReset : std_logic := '1';
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signal cTriggerAdcResetDlyd : std_logic := '1';
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signal cTriggerDacReset : std_logic := '1';
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signal cTriggerDacResetDlyd : std_logic := '1';
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signal rTriggerAdcReset_ms : std_logic := '1';
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signal rTriggerAdcReset : std_logic := '1';
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signal rTriggerDacReset_ms : std_logic := '1';
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signal rTriggerDacReset : std_logic := '1';
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-- POR value of all reset done signals are set to low.
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signal cTriggerAdcResetDone_ms : std_logic := '0';
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signal cTriggerAdcResetDone : std_logic := '0';
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signal cAdcResetDoneSticky : std_logic := '0';
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signal cTriggerDacResetDone_ms : std_logic := '0';
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signal cTriggerDacResetDone : std_logic := '0';
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signal cDacResetDoneSticky : std_logic := '0';
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attribute ASYNC_REG : string;
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attribute ASYNC_REG of rTriggerAdcReset : signal is "TRUE";
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attribute ASYNC_REG of rTriggerDacReset : signal is "TRUE";
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attribute ASYNC_REG of cTriggerAdcResetDone : signal is "TRUE";
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attribute ASYNC_REG of cTriggerDacResetDone : signal is "TRUE";
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attribute ASYNC_REG of rTriggerAdcReset_ms : signal is "TRUE";
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attribute ASYNC_REG of rTriggerDacReset_ms : signal is "TRUE";
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attribute ASYNC_REG of cTriggerAdcResetDone_ms : signal is "TRUE";
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attribute ASYNC_REG of cTriggerDacResetDone_ms : signal is "TRUE";
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begin
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-- rAdcEnableData is set to '1' as we don't control the flow of RX data.
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rAdcEnableData <= '1';
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cTriggerAdcReset <= cSoftwareControl(kADC_RESET);
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cTriggerDacReset <= cSoftwareControl(kDAC_RESET);
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cSoftwareStatus <= (
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kADC_SEQ_DONE => cAdcResetDoneSticky,
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kDAC_SEQ_DONE => cDacResetDoneSticky,
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others => '0'
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);
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-----------------------------------------------------------------------------
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-- High-Level Resets Using ConfigClk
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-----------------------------------------------------------------------------
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-- Pass the master FSM reset around to the other clock domains and then
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-- return them back to the ConfigClk domain. This is also a handy way to
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-- prove all your clocks are toggling to some extent.
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-----------------------------------------------------------------------------
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SeqResetRfClk : process(RfClk)
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begin
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if rising_edge(RfClk) then
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-- double-syncs have no sync reset!
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rTriggerAdcReset_ms <= cTriggerAdcReset;
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rTriggerAdcReset <= rTriggerAdcReset_ms;
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rTriggerDacReset_ms <= cTriggerDacReset;
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rTriggerDacReset <= rTriggerDacReset_ms;
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end if;
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end process;
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-----------------------------------------------------------------------------
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-- Reset Sequence Done Status
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-----------------------------------------------------------------------------
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-- Now back to ConfigClk! We provide the status for all software controlled
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-- resets. We move the signal from ConfigClk to RfClk domain and move it
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-- back to ConfigClk domain. This just proves that RfClk is toggling and
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-- the reset requested by software is sampled in the RfClk.
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-----------------------------------------------------------------------------
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SeqResetDone : process(ConfigClk)
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begin
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if rising_edge(ConfigClk) then
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-- double-syncs have no sync reset!
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cTriggerAdcResetDone_ms <= rTriggerAdcReset;
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cTriggerAdcResetDone <= cTriggerAdcResetDone_ms;
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cTriggerDacResetDone_ms <= rTriggerDacReset;
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cTriggerDacResetDone <= cTriggerDacResetDone_ms;
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end if;
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end process;
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-- ADC reset done
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SwAdcResetDone: process(ConfigClk)
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begin
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if rising_edge(ConfigClk) then
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cTriggerAdcResetDlyd <= cTriggerAdcReset;
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-- De-assert reset status on the rising edge of SW ADC reset.
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if cTriggerAdcReset = '1' and cTriggerAdcResetDlyd = '0' then
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cAdcResetDoneSticky <= '0';
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-- Assert and hold the ADC reset status on ADC reset strobe.
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elsif cTriggerAdcResetDone = '1' then
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cAdcResetDoneSticky <= '1';
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end if;
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end if;
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end process SwAdcResetDone;
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-- DAC reset done
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SwDacResetDone: process(ConfigClk)
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begin
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if rising_edge(ConfigClk) then
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cTriggerDacResetDlyd <= cTriggerDacReset;
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-- De-assert reset status on the rising edge of SW DAC reset.
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if cTriggerDacReset = '1' and cTriggerDacResetDlyd = '0' then
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cDacResetDoneSticky <= '0';
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-- Assert and hold the DAC reset status on DAC reset strobe.
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elsif cTriggerDacResetDone = '1' then
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cDacResetDoneSticky <= '1';
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end if;
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end if;
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end process SwDacResetDone;
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-----------------------------------------------------------------------------
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-- rf_reset Instances
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-----------------------------------------------------------------------------
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RfClkResets: process(RfClk)
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begin
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if rising_edge(RfClk) then
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rAdcReset_n <= not (rAdcResetPulse or rTriggerAdcReset);
|
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rDacReset_n <= not (rDacResetPulse or rTriggerDacReset);
|
||||
end if;
|
||||
end process RfClkResets;
|
||||
|
||||
RfClk2xResets: process(RfClk2x)
|
||||
begin
|
||||
if rising_edge(RfClk2x) then
|
||||
r2AdcReset_n <= not (rAdcResetPulse or rTriggerAdcReset);
|
||||
r2DacReset_n <= not (rDacResetPulse or rTriggerDacReset);
|
||||
end if;
|
||||
end process RfClk2xResets;
|
||||
|
||||
end RTL;
|
||||
@@ -0,0 +1,35 @@
|
||||
//
|
||||
// Copyright 2022 Ettus Research, A National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: x440_rfdc_tx_control_remap.v
|
||||
// Description:
|
||||
// Allows for remapping control signals to the correct tile on X440.
|
||||
// This file targets the DAC tiles specifically
|
||||
//
|
||||
|
||||
`default_nettype none
|
||||
|
||||
module x440_rfdc_tx_control_remap (
|
||||
// Input control (Front-Panel ordering)
|
||||
input wire [7:0] input_controls,
|
||||
// output_control (DAC Tile ordering)
|
||||
output wire [7:0] output_controls
|
||||
);
|
||||
|
||||
`include "../../regmap/x440/rfdc_mapping_regmap_utils.vh"
|
||||
|
||||
// Decode TX Channel mapping
|
||||
assign output_controls[CH0_TX_MAPPING] = input_controls[0];
|
||||
assign output_controls[CH1_TX_MAPPING] = input_controls[1];
|
||||
assign output_controls[CH2_TX_MAPPING] = input_controls[2];
|
||||
assign output_controls[CH3_TX_MAPPING] = input_controls[3];
|
||||
assign output_controls[CH4_TX_MAPPING] = input_controls[4];
|
||||
assign output_controls[CH5_TX_MAPPING] = input_controls[5];
|
||||
assign output_controls[CH6_TX_MAPPING] = input_controls[6];
|
||||
assign output_controls[CH7_TX_MAPPING] = input_controls[7];
|
||||
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
Reference in New Issue
Block a user