fpga: Add X440/FBX support
Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
This commit is contained in:
Javier Valenzuela
committed by
Aki Tomita
Aki Tomita
co-authored by
Martin Braun
Wade Fife
Ryan Marlow
Martin Braun
Wade Fife
Ryan Marlow
parent
a405111ce7
commit
5cadf901c7
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#
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# Copyright 2023 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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RF_FULL_SRCS = $(abspath $(addprefix $(BASE_DIR)/../top/x400/rf/full/, \
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rf_core_full.v \
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))
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//
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// Copyright 2023 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: rf_core_full
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//
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// Description:
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//
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// Top-level wrapper for the ADC/DAC processing logic. One of these wrappers
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// exists for every supported Data Rate. An instance of this core should
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// exist per dboard.
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//
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// Data/RF Specs:
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// DBs: 1
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// RX/DB: 4
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// TX/DB: 4
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// Data Rate: rfdc_clk @ 8 SPC
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//
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// Input Clocks, all aligned to one another and coming from same MMCM
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// rfdc_clk: 15.625 to 250 MHz
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// rfdc_clk_2x: 2 * rfdc_clk
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//
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`default_nettype none
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module rf_core_full # (
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parameter NUM_ADC_CHANNELS = 4,
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parameter NUM_DAC_CHANNELS = 4
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) (
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//---------------------------------------------------------------------------
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// Clocking
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//---------------------------------------------------------------------------
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// Main Clock Inputs
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input wire rfdc_clk,
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input wire rfdc_clk_2x,
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// AXI4-Lite Config Clock
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// This clock is used to synchronize status bits for the RFDC
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// registers in the AXI-S clock domain.
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input wire s_axi_config_clk,
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//---------------------------------------------------------------------------
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// RFDC Data Interfaces
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//---------------------------------------------------------------------------
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// All ports here are in the rfdc_clk domain.
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// ADC
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input wire [127:0] adc_data_in_i_tdata_0,
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output wire adc_data_in_i_tready_0,
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input wire adc_data_in_i_tvalid_0,
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input wire [127:0] adc_data_in_q_tdata_0,
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output wire adc_data_in_q_tready_0,
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input wire adc_data_in_q_tvalid_0,
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input wire [127:0] adc_data_in_i_tdata_1,
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output wire adc_data_in_i_tready_1,
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input wire adc_data_in_i_tvalid_1,
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input wire [127:0] adc_data_in_q_tdata_1,
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output wire adc_data_in_q_tready_1,
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input wire adc_data_in_q_tvalid_1,
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input wire [127:0] adc_data_in_i_tdata_2,
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output wire adc_data_in_i_tready_2,
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input wire adc_data_in_i_tvalid_2,
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input wire [127:0] adc_data_in_q_tdata_2,
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output wire adc_data_in_q_tready_2,
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input wire adc_data_in_q_tvalid_2,
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input wire [127:0] adc_data_in_i_tdata_3,
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output wire adc_data_in_i_tready_3,
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input wire adc_data_in_i_tvalid_3,
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input wire [127:0] adc_data_in_q_tdata_3,
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output wire adc_data_in_q_tready_3,
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input wire adc_data_in_q_tvalid_3,
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// DAC
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output wire [255:0] dac_data_out_tdata_0,
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input wire dac_data_out_tready_0,
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output wire dac_data_out_tvalid_0,
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output wire [255:0] dac_data_out_tdata_1,
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input wire dac_data_out_tready_1,
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output wire dac_data_out_tvalid_1,
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output wire [255:0] dac_data_out_tdata_2,
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input wire dac_data_out_tready_2,
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output wire dac_data_out_tvalid_2,
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output wire [255:0] dac_data_out_tdata_3,
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input wire dac_data_out_tready_3,
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output wire dac_data_out_tvalid_3,
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//---------------------------------------------------------------------------
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// User Data Interfaces
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//---------------------------------------------------------------------------
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// All ports here are in the rfdc_clk domain on the X440.
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// ADC
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output wire [255:0] adc_data_out_tdata_0, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs
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output wire adc_data_out_tvalid_0,
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output wire [255:0] adc_data_out_tdata_1, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs
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output wire adc_data_out_tvalid_1,
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output wire [255:0] adc_data_out_tdata_2, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs
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output wire adc_data_out_tvalid_2,
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output wire [255:0] adc_data_out_tdata_3, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs
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output wire adc_data_out_tvalid_3,
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// DAC
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input wire [255:0] dac_data_in_tdata_0, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs
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output wire dac_data_in_tready_0,
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input wire dac_data_in_tvalid_0,
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input wire [255:0] dac_data_in_tdata_1, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs
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output wire dac_data_in_tready_1,
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input wire dac_data_in_tvalid_1,
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input wire [255:0] dac_data_in_tdata_2, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs
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output wire dac_data_in_tready_2,
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input wire dac_data_in_tvalid_2,
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input wire [255:0] dac_data_in_tdata_3, // Packed [Q7,I7, ... , Q0,I0] with Q in MSBs
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output wire dac_data_in_tready_3,
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input wire dac_data_in_tvalid_3,
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//---------------------------------------------------------------------------
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// Miscellaneous
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//---------------------------------------------------------------------------
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// Invert I/Q control signals from RFDC to DSP chain.
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input wire [3:0] invert_adc_iq_rclk2,
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input wire [3:0] invert_dac_iq_rclk2,
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// Control/status vectors from/to RFDC.
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// Notice these are all in the s_axi_config_clk domain.
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output wire [9:0] dsp_info_sclk,
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output wire [15:0] axi_status_sclk,
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output wire [15:0] rfdc_info_sclk,
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// Resets.
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input wire adc_enable_data_rclk,
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input wire adc_rfdc_axi_resetn_rclk,
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// Version (Constant)
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output wire [95:0] version_info
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);
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`include "../../regmap/x440/rfdc_regs_regmap_utils.vh"
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`include "../../regmap/x440/versioning_regs_regmap_utils.vh"
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`include "../../regmap/versioning_utils.vh"
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// ADC data interface from RFDC.
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wire [127:0] adc_data_in_i_tdata [0:NUM_ADC_CHANNELS-1]; // 8 SPC (I)
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wire [127:0] adc_data_in_q_tdata [0:NUM_ADC_CHANNELS-1]; // 8 SPC (Q)
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wire [NUM_ADC_CHANNELS-1:0] adc_data_in_i_tready;
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wire [NUM_ADC_CHANNELS-1:0] adc_data_in_q_tready;
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wire [NUM_ADC_CHANNELS-1:0] adc_data_in_i_tvalid;
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wire [NUM_ADC_CHANNELS-1:0] adc_data_in_q_tvalid;
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// DAC data interface to RFDC.
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wire [255:0] dac_data_out_tdata [0:NUM_DAC_CHANNELS-1]; // 8 SPC (I + Q)
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wire [NUM_DAC_CHANNELS-1:0] dac_data_out_tready;
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wire [NUM_DAC_CHANNELS-1:0] dac_data_out_tvalid;
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// ADC data interface to user.
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wire [255:0] adc_data_out_tdata [0:NUM_ADC_CHANNELS-1]; // 8 SPC (I + Q)
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wire [NUM_ADC_CHANNELS-1:0] adc_data_out_tready;
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wire [NUM_ADC_CHANNELS-1:0] adc_data_out_tvalid;
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// DAC data interface from user.
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wire [255:0] dac_data_in_tdata_preswap [0:NUM_DAC_CHANNELS-1]; // 8 SPC (I + Q)
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wire [255:0] dac_data_in_tdata [0:NUM_DAC_CHANNELS-1]; // 8 SPC (I + Q)
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wire [NUM_DAC_CHANNELS-1:0] dac_data_in_tready;
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wire [NUM_DAC_CHANNELS-1:0] dac_data_in_tvalid;
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wire [15:0] axi_status;
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//---------------------------------------------------------------------------
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// Resets, Debug and Misc.
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//---------------------------------------------------------------------------
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// Group all these status bits together. They don't toggle frequently so data
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// coherency is not an issue here.
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// Using constants for DB0 since the bits are the 16 LSBs in a 32-bit vector.
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// DB1 simply uses the 16 MSBs when wiring the status vector.
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assign axi_status[USER_ADC_TREADY_MSB :USER_ADC_TREADY ] = adc_data_out_tready[1:0];
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assign axi_status[USER_ADC_TVALID_MSB :USER_ADC_TVALID ] = adc_data_out_tvalid[1:0];
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assign axi_status[RFDC_ADC_I_TVALID_MSB:RFDC_ADC_I_TVALID] = adc_data_in_i_tvalid[1:0];
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assign axi_status[RFDC_ADC_Q_TVALID_MSB:RFDC_ADC_Q_TVALID] = adc_data_in_q_tvalid[1:0];
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assign axi_status[RFDC_ADC_I_TREADY_MSB:RFDC_ADC_I_TREADY] = adc_data_in_i_tready[1:0];
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assign axi_status[RFDC_ADC_Q_TREADY_MSB:RFDC_ADC_Q_TREADY] = adc_data_in_q_tready[1:0];
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assign axi_status[RFDC_DAC_TVALID_MSB :RFDC_DAC_TVALID ] = dac_data_out_tvalid[1:0];
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assign axi_status[RFDC_DAC_TREADY_MSB :RFDC_DAC_TREADY ] = dac_data_out_tready[1:0];
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synchronizer #(
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.WIDTH (16),
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.STAGES (2),
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.INITIAL_VAL (0),
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.FALSE_PATH_TO_IN (1)
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) synchronizer_axis_status (
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.clk (s_axi_config_clk),
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.rst (1'b0),
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.in (axi_status),
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.out (axi_status_sclk)
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);
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// Drive the DSP info vector with information on this specific DSP chain.
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assign dsp_info_sclk[FABRIC_DSP_RX_CNT_MSB:FABRIC_DSP_RX_CNT] = NUM_ADC_CHANNELS;
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assign dsp_info_sclk[FABRIC_DSP_TX_CNT_MSB:FABRIC_DSP_TX_CNT] = NUM_DAC_CHANNELS;
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// This RF core always consumes 8 SPC from the gearbox per I/Q signal
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assign rfdc_info_sclk[RFDC_INFO_SPC_RX_MSB:RFDC_INFO_SPC_RX] = $clog2(8);
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assign rfdc_info_sclk[RFDC_INFO_SPC_TX_MSB:RFDC_INFO_SPC_TX] = $clog2(16);
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// This RF core module contains no additional resampling
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assign rfdc_info_sclk[RFDC_INFO_XTRA_RESAMP_MSB:RFDC_INFO_XTRA_RESAMP] = 4'd1;
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//---------------------------------------------------------------------------
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// ADC Post-Processing
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//---------------------------------------------------------------------------
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// Data comes from the RFDC as 8 SPC, separate streams for each channel and
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// I/Q.
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assign adc_data_in_i_tdata[0] = adc_data_in_i_tdata_0;
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assign adc_data_in_q_tdata[0] = adc_data_in_q_tdata_0;
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assign adc_data_in_i_tdata[1] = adc_data_in_i_tdata_1;
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assign adc_data_in_q_tdata[1] = adc_data_in_q_tdata_1;
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assign adc_data_in_i_tdata[2] = adc_data_in_i_tdata_2;
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assign adc_data_in_q_tdata[2] = adc_data_in_q_tdata_2;
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assign adc_data_in_i_tdata[3] = adc_data_in_i_tdata_3;
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assign adc_data_in_q_tdata[3] = adc_data_in_q_tdata_3;
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assign adc_data_in_i_tready_0 = adc_data_in_i_tready[0];
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assign adc_data_in_i_tvalid[0] = adc_data_in_i_tvalid_0;
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assign adc_data_in_q_tready_0 = adc_data_in_q_tready[0];
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assign adc_data_in_q_tvalid[0] = adc_data_in_q_tvalid_0;
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assign adc_data_in_i_tready_1 = adc_data_in_i_tready[1];
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assign adc_data_in_i_tvalid[1] = adc_data_in_i_tvalid_1;
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assign adc_data_in_q_tready_1 = adc_data_in_q_tready[1];
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assign adc_data_in_q_tvalid[1] = adc_data_in_q_tvalid_1;
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assign adc_data_in_i_tready_2 = adc_data_in_i_tready[2];
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assign adc_data_in_i_tvalid[2] = adc_data_in_i_tvalid_2;
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assign adc_data_in_q_tready_2 = adc_data_in_q_tready[2];
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assign adc_data_in_q_tvalid[2] = adc_data_in_q_tvalid_2;
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assign adc_data_in_i_tready_3 = adc_data_in_i_tready[3];
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assign adc_data_in_i_tvalid[3] = adc_data_in_i_tvalid_3;
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assign adc_data_in_q_tready_3 = adc_data_in_q_tready[3];
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assign adc_data_in_q_tvalid[3] = adc_data_in_q_tvalid_3;
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// ADC Data from the RFDC arrives here as 8 SPC with separate I and Q
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// streams. It leaves the adc_full_rate_bd as 8 SPC with I and Q packed into
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// a single 256 bit word.
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genvar adc_num;
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generate
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for (adc_num=0; adc_num < (NUM_ADC_CHANNELS); adc_num = adc_num + 1)
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begin : adc_gen
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adc_full_bd adc_full_bd_gen (
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.enable_data_to_repacker_rclk (adc_enable_data_rclk),
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.rfdc_adc_axi_resetn_rclk (adc_rfdc_axi_resetn_rclk),
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.rfdc_clk (rfdc_clk),
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.swap_iq_rclk (invert_adc_iq_rclk2 [adc_num]),
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.adc_q_data_in_tvalid (adc_data_in_q_tvalid[adc_num]),
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.adc_q_data_in_tready (adc_data_in_q_tready[adc_num]),
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.adc_q_data_in_tdata (adc_data_in_q_tdata [adc_num]),
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.adc_i_data_in_tvalid (adc_data_in_i_tvalid[adc_num]),
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.adc_i_data_in_tready (adc_data_in_i_tready[adc_num]),
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.adc_i_data_in_tdata (adc_data_in_i_tdata [adc_num]),
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.adc_data_out_tvalid (adc_data_out_tvalid [adc_num]),
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.adc_data_out_tdata (adc_data_out_tdata [adc_num])
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);
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end
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endgenerate
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// Data is released to the user as 8 SPC, separate streams for each channel.
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assign adc_data_out_tdata_0 = adc_data_out_tdata[0];
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assign adc_data_out_tdata_1 = adc_data_out_tdata[1];
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assign adc_data_out_tdata_2 = adc_data_out_tdata[2];
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assign adc_data_out_tdata_3 = adc_data_out_tdata[3];
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// There is no tready going to the ADC (one has to be always ready for ADC
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// data), but it is still a component of the axi_status vector as a generic
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// AXI stream status. Report 1'b1 to the status vector consistent with being
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// always ready
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assign adc_data_out_tready[0] = 1'b1;
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assign adc_data_out_tvalid_0 = adc_data_out_tvalid[0];
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assign adc_data_out_tready[1] = 1'b1;
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assign adc_data_out_tvalid_1 = adc_data_out_tvalid[1];
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assign adc_data_out_tready[2] = 1'b1;
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assign adc_data_out_tvalid_2 = adc_data_out_tvalid[2];
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assign adc_data_out_tready[3] = 1'b1;
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assign adc_data_out_tvalid_3 = adc_data_out_tvalid[3];
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//---------------------------------------------------------------------------
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// DAC Pre-Processing
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//---------------------------------------------------------------------------
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// Data comes from the user as 8 SPC, separate streams for each channel.
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assign dac_data_in_tdata_preswap[0] = dac_data_in_tdata_0;
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assign dac_data_in_tdata_preswap[1] = dac_data_in_tdata_1;
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assign dac_data_in_tdata_preswap[2] = dac_data_in_tdata_2;
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assign dac_data_in_tdata_preswap[3] = dac_data_in_tdata_3;
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assign dac_data_in_tready_0 = dac_data_in_tready[0];
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assign dac_data_in_tvalid[0] = dac_data_in_tvalid_0;
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assign dac_data_in_tready_1 = dac_data_in_tready[1];
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assign dac_data_in_tvalid[1] = dac_data_in_tvalid_1;
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assign dac_data_in_tready_2 = dac_data_in_tready[2];
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assign dac_data_in_tvalid[2] = dac_data_in_tvalid_2;
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assign dac_data_in_tready_3 = dac_data_in_tready[3];
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assign dac_data_in_tvalid[3] = dac_data_in_tvalid_3;
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genvar dac_num;
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generate
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for (dac_num=0; dac_num < (NUM_DAC_CHANNELS); dac_num = dac_num + 1)
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begin : dac_swap_gen
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//IO and Q0 swap
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assign dac_data_in_tdata[dac_num][15:00] = invert_dac_iq_rclk2[dac_num] ?
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(dac_data_in_tdata_preswap[dac_num][31:16]) : (dac_data_in_tdata_preswap[dac_num][15:0]);
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assign dac_data_in_tdata[dac_num][31:16] = invert_dac_iq_rclk2[dac_num] ?
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(dac_data_in_tdata_preswap[dac_num][15:00]) : (dac_data_in_tdata_preswap[dac_num][31:16]);
|
||||
|
||||
//I1 and Q1 swap
|
||||
assign dac_data_in_tdata[dac_num][47:32] = invert_dac_iq_rclk2[dac_num] ?
|
||||
(dac_data_in_tdata_preswap[dac_num][63:48]) : (dac_data_in_tdata_preswap[dac_num][47:32]);
|
||||
assign dac_data_in_tdata[dac_num][63:48] = invert_dac_iq_rclk2[dac_num] ?
|
||||
(dac_data_in_tdata_preswap[dac_num][47:32]) : (dac_data_in_tdata_preswap[dac_num][63:48]);
|
||||
|
||||
//I2 and Q2 swap
|
||||
assign dac_data_in_tdata[dac_num][79:64] = invert_dac_iq_rclk2[dac_num] ?
|
||||
(dac_data_in_tdata_preswap[dac_num][95:80]) : (dac_data_in_tdata_preswap[dac_num][79:64]);
|
||||
assign dac_data_in_tdata[dac_num][95:80] = invert_dac_iq_rclk2[dac_num] ?
|
||||
(dac_data_in_tdata_preswap[dac_num][79:64]) : (dac_data_in_tdata_preswap[dac_num][95:80]);
|
||||
|
||||
//I3 and Q3 swap
|
||||
assign dac_data_in_tdata[dac_num][111:96] = invert_dac_iq_rclk2[dac_num] ?
|
||||
(dac_data_in_tdata_preswap[dac_num][127:112]) : (dac_data_in_tdata_preswap[dac_num][111:96]);
|
||||
assign dac_data_in_tdata[dac_num][127:112] = invert_dac_iq_rclk2[dac_num] ?
|
||||
(dac_data_in_tdata_preswap[dac_num][111:96]) : (dac_data_in_tdata_preswap[dac_num][127:112]);
|
||||
|
||||
//I4 and Q4 swap
|
||||
assign dac_data_in_tdata[dac_num][143:128] = invert_dac_iq_rclk2[dac_num] ?
|
||||
(dac_data_in_tdata_preswap[dac_num][159:144]) : (dac_data_in_tdata_preswap[dac_num][143:128]);
|
||||
assign dac_data_in_tdata[dac_num][159:144] = invert_dac_iq_rclk2[dac_num] ?
|
||||
(dac_data_in_tdata_preswap[dac_num][143:128]) : (dac_data_in_tdata_preswap[dac_num][159:144]);
|
||||
|
||||
//I5 and Q5 swap
|
||||
assign dac_data_in_tdata[dac_num][175:160] = invert_dac_iq_rclk2[dac_num] ?
|
||||
(dac_data_in_tdata_preswap[dac_num][191:176]) : (dac_data_in_tdata_preswap[dac_num][175:160]);
|
||||
assign dac_data_in_tdata[dac_num][191:176] = invert_dac_iq_rclk2[dac_num] ?
|
||||
(dac_data_in_tdata_preswap[dac_num][175:160]) : (dac_data_in_tdata_preswap[dac_num][191:176]);
|
||||
|
||||
//I6 and Q6 swap
|
||||
assign dac_data_in_tdata[dac_num][207:192] = invert_dac_iq_rclk2[dac_num] ?
|
||||
(dac_data_in_tdata_preswap[dac_num][223:208]) : (dac_data_in_tdata_preswap[dac_num][207:192]);
|
||||
assign dac_data_in_tdata[dac_num][223:208] = invert_dac_iq_rclk2[dac_num] ?
|
||||
(dac_data_in_tdata_preswap[dac_num][207:192]) : (dac_data_in_tdata_preswap[dac_num][223:208]);
|
||||
|
||||
//I7 and Q7 swap
|
||||
assign dac_data_in_tdata[dac_num][239:224] = invert_dac_iq_rclk2[dac_num] ?
|
||||
(dac_data_in_tdata_preswap[dac_num][255:240]) : (dac_data_in_tdata_preswap[dac_num][239:224]);
|
||||
assign dac_data_in_tdata[dac_num][255:240] = invert_dac_iq_rclk2[dac_num] ?
|
||||
(dac_data_in_tdata_preswap[dac_num][239:224]) : (dac_data_in_tdata_preswap[dac_num][255:240]);
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// These streams are then connected to data out, no need for a bd, and form a single
|
||||
// stream per channel, 8 SPC, packed: MSB [Sample7Q, Sample7I, ... ,
|
||||
// Sample0Q, Sample0I] LSB.
|
||||
generate
|
||||
for (dac_num=0; dac_num < (NUM_DAC_CHANNELS); dac_num = dac_num + 1)
|
||||
begin : dac_gen
|
||||
assign dac_data_out_tdata[dac_num] = dac_data_in_tdata[dac_num];
|
||||
assign dac_data_out_tvalid[dac_num] = dac_data_in_tvalid[dac_num];
|
||||
assign dac_data_in_tready[dac_num] = dac_data_out_tready[dac_num];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// Data is released to the RFDC as 8 SPC, separate streams per channel (I/Q
|
||||
// together).
|
||||
assign dac_data_out_tdata_0 = dac_data_out_tdata[0];
|
||||
assign dac_data_out_tdata_1 = dac_data_out_tdata[1];
|
||||
assign dac_data_out_tdata_2 = dac_data_out_tdata[2];
|
||||
assign dac_data_out_tdata_3 = dac_data_out_tdata[3];
|
||||
|
||||
assign dac_data_out_tready[0] = dac_data_out_tready_0;
|
||||
assign dac_data_out_tvalid_0 = dac_data_out_tvalid[0];
|
||||
assign dac_data_out_tready[1] = dac_data_out_tready_1;
|
||||
assign dac_data_out_tvalid_1 = dac_data_out_tvalid[1];
|
||||
assign dac_data_out_tready[2] = dac_data_out_tready_2;
|
||||
assign dac_data_out_tvalid_2 = dac_data_out_tvalid[2];
|
||||
assign dac_data_out_tready[3] = dac_data_out_tready_3;
|
||||
assign dac_data_out_tvalid_3 = dac_data_out_tvalid[3];
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Version
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
// Version metadata, constants come from auto-generated
|
||||
// versioning_regs_regmap_utils.vh
|
||||
assign version_info = build_component_versions(
|
||||
RF_CORE_FULL_VERSION_LAST_MODIFIED_TIME,
|
||||
build_version(
|
||||
RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MAJOR,
|
||||
RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MINOR,
|
||||
RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_BUILD
|
||||
),
|
||||
build_version(
|
||||
RF_CORE_FULL_CURRENT_VERSION_MAJOR,
|
||||
RF_CORE_FULL_CURRENT_VERSION_MINOR,
|
||||
RF_CORE_FULL_CURRENT_VERSION_BUILD
|
||||
)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
//XmlParse xml_on
|
||||
//<regmap name="VERSIONING_REGS_REGMAP">
|
||||
// <group name="VERSIONING_CONSTANTS">
|
||||
// <enumeratedtype name="RF_CORE_FULL_VERSION" showhex="true">
|
||||
// <info>
|
||||
// Full BW RF core.{BR/}
|
||||
// For guidance on when to update these revision numbers,
|
||||
// please refer to the register map documentation accordingly:
|
||||
// <li> Current version: @.VERSIONING_REGS_REGMAP..CURRENT_VERSION
|
||||
// <li> Oldest compatible version: @.VERSIONING_REGS_REGMAP..OLDEST_COMPATIBLE_VERSION
|
||||
// <li> Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED
|
||||
// </info>
|
||||
// <value name="RF_CORE_FULL_CURRENT_VERSION_MAJOR" integer="1"/>
|
||||
// <value name="RF_CORE_FULL_CURRENT_VERSION_MINOR" integer="0"/>
|
||||
// <value name="RF_CORE_FULL_CURRENT_VERSION_BUILD" integer="0"/>
|
||||
// <value name="RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MAJOR" integer="1"/>
|
||||
// <value name="RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MINOR" integer="0"/>
|
||||
// <value name="RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_BUILD" integer="0"/>
|
||||
// <value name="RF_CORE_FULL_VERSION_LAST_MODIFIED_TIME" integer="0x22062900"/>
|
||||
// </enumeratedtype>
|
||||
// </group>
|
||||
//</regmap>
|
||||
//XmlParse xml_off
|
||||
Reference in New Issue
Block a user