fpga: Add X440/FBX support
Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
This commit is contained in:
Javier Valenzuela
committed by
Aki Tomita
Aki Tomita
co-authored by
Martin Braun
Wade Fife
Ryan Marlow
Martin Braun
Wade Fife
Ryan Marlow
parent
a405111ce7
commit
5cadf901c7
@@ -6,6 +6,7 @@
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RF_COMMON_SRCS = $(abspath $(addprefix $(BASE_DIR)/../top/x400/rf/common/, \
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PkgRf.vhd \
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adc_iq_repacker.v \
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axis_mux.vhd \
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capture_sysref.v \
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gpio_to_axis_mux.vhd \
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@@ -0,0 +1,115 @@
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//
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// Copyright 2022 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: adc_iq_repacker
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//
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// Description:
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//
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// This component repacks IQ from independent vectors into a single
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// output signal, and implements data swapping when requested.
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//
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// The parameters for this component describe the expected amount of
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// data to be received as well as the data to be generated.
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//
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// - SPC = Samples per cycle: amount of samples to be expected
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// on each I and Q input vector on each "clk" cycle.
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// - SAMPLE_WIDTH = Amount of bits composing each sample
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//
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// This modules incurs in two clk cycles of delay on the data and valid
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// signals from input to output.
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//
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// Example case : SPC = 2, SAMPLE_WIDTH = 16
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//
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// adc_x_in size(for I and Q) = 2 x 16 = 32
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// adc_out size = 2 x 2 x 16 = 64
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//
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// _______ _______ _______ ______
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// clk _| |_______| |_______| |_______|
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// _ _______________ _______________ _______________ ______
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// adc_i_in _X_____I1,I0_____X_____I3,I2_____X____32{'X'}____X______
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// _ _______________ _______________ _______________ ______
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// adc_q_in _X_____Q1,Q0_____X_____Q3,Q2_____X____32{'X'}____X______
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// _______________________________
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// valid_in _| |______________________
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// _ _______________ _______________ _______________ ______
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// adc_out _X____64{'X'}____X____64{'X'}____X__Q1,I1,Q0,I0__X__Q3,..
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// ______________________
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// valid_out _________________________________|
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//
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// When the swap input is high, the order in which Q and I samples
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// appear on the output vector is inverted
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//
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// _______ _______ _______ ______
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// clk _| |_______| |_______| |_______|
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// _ _______________ _______________ _______________ ______
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// adc_i_in _X_____I1,I0_____X_____I3,I2_____X____32{'X'}____X______
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// _ _______________ _______________ _______________ ______
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// adc_q_in _X_____Q1,Q0_____X_____Q3,Q2_____X____32{'X'}____X______
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// _______________________________
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// valid_in _| |______________________
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// _ _______________ _______________ _______________ ______
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// adc_out _X____64{'X'}____X____64{'X'}____X__I1,Q1,I0,Q0__X__I3,..
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// ______________________
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// valid_out _________________________________|
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//
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// Parameters:
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// SPC = Samples per cycle
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// SAMPLE_WIDTH = width of i/q sample inputs. Output will be 2*SAMPLE_WIDTH
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//
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module adc_iq_repacker #(
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parameter SPC = 1,
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parameter SAMPLE_WIDTH = 16
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)
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(
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input wire clk,
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// Data in
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input wire [SPC*SAMPLE_WIDTH-1:0] adc_q_in,
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input wire [SPC*SAMPLE_WIDTH-1:0] adc_i_in,
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input wire valid_in,
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// This signal is currently driven in a related clock, and even though it runs at half the rate is should be fine
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// to handle it in this clock domain(in nature it will also stay high one asserted until the next reset.)
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input wire enable,
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// Data is packed [Q,I] (I in LSBs) when swap_iq is '0', and [I,Q] otherwise
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input wire swap_iq,
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// Data out
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output reg [SPC*SAMPLE_WIDTH*2-1:0] data_out_tdata,
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output reg data_out_tvalid
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);
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localparam IQ_WIDTH = SAMPLE_WIDTH*2;
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reg valid = 1'b0, valid_dly = 1'b0;
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reg [SPC*SAMPLE_WIDTH-1:0] adc_q_data_in = {SPC*SAMPLE_WIDTH{1'b0}};
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reg [SPC*SAMPLE_WIDTH-1:0] adc_i_data_in = {SPC*SAMPLE_WIDTH{1'b0}};
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integer sample_num;
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// It is safe to not reset this domain because all of the input signals will be cleared
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// by a synchronous reset. Safe default values are assigned to all these registers.
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always @(posedge clk) begin
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adc_q_data_in <= adc_q_in;
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adc_i_data_in <= adc_i_in;
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// Place Q in the MSBs, I in the LSBs by default, unless swapped = 1.
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for (sample_num=0; sample_num < (SPC); sample_num = sample_num + 1)
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begin : data_out_gen
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if (swap_iq) begin
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data_out_tdata[sample_num*(IQ_WIDTH) +: IQ_WIDTH] <=
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{adc_i_data_in[sample_num*(SAMPLE_WIDTH) +: SAMPLE_WIDTH],
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adc_q_data_in[sample_num*(SAMPLE_WIDTH) +: SAMPLE_WIDTH]};
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end else begin
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data_out_tdata[sample_num*(IQ_WIDTH) +: IQ_WIDTH] <=
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{adc_q_data_in[sample_num*(SAMPLE_WIDTH) +: SAMPLE_WIDTH],
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adc_i_data_in[sample_num*(SAMPLE_WIDTH) +: SAMPLE_WIDTH]};
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end
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end
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// Valid is simply a transferred version of the 1x clock's valid. Delay it one
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// more cycle to align outputs.
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valid <= valid_in && enable;
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data_out_tvalid <= valid;
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end
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endmodule
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@@ -1,300 +0,0 @@
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--
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-- Copyright 2021 Ettus Research, a National Instruments Brand
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--
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-- SPDX-License-Identifier: LGPL-3.0-or-later
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--
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-- Module: clock_gates
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--
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-- Description:
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--
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-- Gate propagation of DataClk and RfdcClk instances until the PLL lock
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-- status signal is stable and software has acknowledged it by asserting the
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-- pertinent controls.
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--
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-- RfdcClks are used on other Xilinx IP components in the Board Design, and
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-- Vivado fails to detect their frequency correctly their buffer is
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-- explicitly instantiated in the Block Design. Therefore, we only generate
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-- the buffer enable signals for these clocks within this component.
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--
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-- Since DataClk are only used in other Custom IP blocks within the Block
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-- design, it is possible to instantiate the clock buffers within this block
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-- for without running into IP generation failures.
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--
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-- Parameters:
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--
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-- kReliableClkPeriodNs: Clock period (ns) for ReliableClk.
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--
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library IEEE;
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use IEEE.std_logic_1164.ALL;
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use IEEE.numeric_std.ALL;
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library UNISIM;
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use UNISIM.Vcomponents.ALL;
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library WORK;
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use WORK.PkgRFDC_REGS_REGMAP.all;
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entity clock_gates is
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generic (
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kReliableClkPeriodNs : integer := 25
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);
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port (
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-- MMCM reset
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-- This clock will be asserted via AXI access before any clocking
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-- configuration done, signals coming into this component will not change
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-- immediately after this reset is de-asserted.
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rPllReset_n : in std_logic;
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aPllLocked : in std_logic;
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-- Input Clocks (from MMCM)
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ReliableClk : in std_logic;
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DataClk1xPll : in std_logic;
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DataClk2xPll : in std_logic;
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-- Buffered Clock Outputs (to design)
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DataClk1x : out std_logic;
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DataClk2x : out std_logic;
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-- Buffers for these signals must be instantiated on Block design for clock
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-- rates to be identified. The Utility Buffers instantiated on the Block
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-- Design require signals to be of type std_logic_vector.
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aEnableRfBufg1x : out std_logic_vector(0 downto 0);
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aEnableRfBufg2x : out std_logic_vector(0 downto 0);
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-- PLL Status Signals
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rPllLocked : out std_logic;
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-- Window Interface
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rSafeToEnableGatedClks : in std_logic;
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rGatedBaseClksValid : out std_logic;
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-- AXI GPIO interface
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rSoftwareControl : in std_logic_vector(31 downto 0);
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rSoftwareStatus : out std_logic_vector(31 downto 0)
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);
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end clock_gates;
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architecture STRUCT of clock_gates is
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component sync_wrapper
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generic (
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WIDTH : integer := 1;
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STAGES : integer := 2;
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INITIAL_VAL : integer := 0;
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FALSE_PATH_TO_IN : integer := 1);
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port (
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clk : in std_logic;
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rst : in std_logic;
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signal_in : in std_logic_vector((WIDTH-1) downto 0);
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signal_out : out std_logic_vector((WIDTH-1) downto 0));
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end component;
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component BUFGCE
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generic(
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CE_TYPE : string);
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port (
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O : out std_ulogic;
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CE : in std_ulogic;
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I : in std_ulogic);
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end component;
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-- UltraScale MMCM max lock time = 100 us / 25 ns = 4,000 clk cycles. If the
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-- division kPllLockTimeNs / kReliableClkPeriodNs does not evaluate to an
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-- integer, Vivado could either round up or down. In case they round down, we
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-- add '1' to the result to ensure we have the full lock time accounted for.
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-- In this case, it is better to count 1 more than necessary than kill the
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-- process prematurely.
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constant kPllLockTimeNs : integer := 100000;
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constant kMaxPllLockCount : integer := kPllLockTimeNs / kReliableClkPeriodNs + 1;
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signal rLockedFilterCount : integer range 0 to kMaxPllLockCount-1 := kMaxPllLockCount-1;
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signal rClearDataClkUnlockedSticky : std_logic;
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-----------------------------------------------------------------------------
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-- PLL locked signals
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-----------------------------------------------------------------------------
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-- Synchronizer signals
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signal aPllLockedLcl : std_logic_vector(0 downto 0);
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signal rPllLockedDs : std_logic_vector(0 downto 0) := (others => '0');
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-- Lock status indicators
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signal rPllLockedLcl : std_logic := '0';
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signal rPllUnlockedSticky : std_logic := '0';
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-- Safe BUFG enable signals
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signal rEnableDataClk1x,
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rEnableDataClk2x,
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rEnableRfdcClk1x,
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rEnableRfdcClk2x : std_logic;
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signal rEnableDataBufg1x : std_logic := '0';
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signal rEnableDataBufg2x : std_logic := '0';
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signal rEnableRfdcBufg1xLcl : std_logic := '0';
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signal rEnableRfdcBufg2xLcl : std_logic := '0';
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-- Active high version of reset required for synchronizer blocks.
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signal rPllReset : std_logic;
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-- Since these signals control sensitive components (clock enables), we apply
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-- a dont_touch attribute to preserve the signals through both synthesis and
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-- P&R. Implementation of "dont_touch" has been confirmed after P&R.
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attribute dont_touch : string;
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attribute dont_touch of rEnableDataBufg1x : signal is "TRUE";
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attribute dont_touch of rEnableDataBufg2x : signal is "TRUE";
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attribute dont_touch of aEnableRfBufg1x : signal is "TRUE";
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attribute dont_touch of aEnableRfBufg2x : signal is "TRUE";
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attribute X_INTERFACE_INFO : string;
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attribute X_INTERFACE_PARAMETER : string;
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attribute X_INTERFACE_INFO of DataClk1xPll : signal is
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"xilinx.com:signal:clock:1.0 DataClk1xPll CLK";
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attribute X_INTERFACE_INFO of DataClk2xPll : signal is
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"xilinx.com:signal:clock:1.0 DataClk2xPll CLK";
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begin
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rPllReset <= not rPllReset_n;
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-- Assert rGatedBaseClksValid once the PLL has been locked for the specified
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-- time.
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rGatedBaseClksValid <= rPllLockedLcl;
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DataClkEnables : process(ReliableClk)
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begin
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if rising_edge(ReliableClk) then
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if rPllReset_n = '0' then
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rEnableDataBufg1x <= '0';
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rEnableDataBufg2x <= '0';
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rEnableRfdcBufg1xLcl <= '0';
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rEnableRfdcBufg2xLcl <= '0';
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else
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rEnableDataBufg1x <=
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rSafeToEnableGatedClks and
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rEnableDataClk1x and
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(not rPllUnlockedSticky);
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rEnableDataBufg2x <=
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rSafeToEnableGatedClks and
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rEnableDataClk2x and
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(not rPllUnlockedSticky);
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rEnableRfdcBufg1xLcl <=
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rSafeToEnableGatedClks and
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rEnableRfdcClk1x and
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(not rPllUnlockedSticky);
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rEnableRfdcBufg2xLcl <=
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rSafeToEnableGatedClks and
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rEnableRfdcClk2x and
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(not rPllUnlockedSticky);
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end if;
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end if;
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end process DataClkEnables;
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aEnableRfBufg1x(0) <= rEnableRfdcBufg1xLcl;
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aEnableRfBufg2x(0) <= rEnableRfdcBufg2xLcl;
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DataClk1xSafeBufg: BUFGCE
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generic map(
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CE_TYPE => "ASYNC"
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)
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port map (
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I => DataClk1xPll,
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CE => rEnableDataBufg1x,
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O => DataClk1x
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);
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DataClk2xSafeBufg: BUFGCE
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generic map(
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CE_TYPE => "ASYNC"
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)
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port map (
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I => DataClk2xPll,
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CE => rEnableDataBufg2x,
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O => DataClk2x
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);
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-----------------------------------------------------------------------------
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-- Create PLL Lock Signal
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-----------------------------------------------------------------------------
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-- Double-sync the incoming aPllLocked signal from the PLL.
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aPllLockedLcl(0) <= aPllLocked;
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DataClkPllLockedDS: sync_wrapper
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generic map (
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WIDTH => 1,
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STAGES => open,
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INITIAL_VAL => open,
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FALSE_PATH_TO_IN => open)
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port map (
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clk => ReliableClk,
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rst => rPllReset,
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signal_in => aPllLockedLcl,
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signal_out => rPllLockedDs
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);
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-- Filter the Lock signal. Assert a lock when the PLL lock signal has been
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-- asserted for kPllLockTimeNs
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--
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-- !!! SAFE COUNTER STARTUP !!!
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-- rLockedFilterCount cannot start incrementing until rPllReset_n is
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-- de-asserted. Once rPllReset_n is de-asserted through a AXI access, input
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-- values for the registers in this state machine will not change until the
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-- MMCM locks and the double synchronizer reflects a locked status, making
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-- this start-up safe.
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PllLockFilter: process (ReliableClk)
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begin
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if rising_edge(ReliableClk) then
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if rPllReset_n = '0' then
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rLockedFilterCount <= kMaxPllLockCount-1;
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rPllLockedLcl <= '0';
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else
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if rPllLockedDs(0) = '1' then
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if rLockedFilterCount = 0 then
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rPllLockedLcl <= '1';
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else
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rPllLockedLcl <= '0';
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rLockedFilterCount <= rLockedFilterCount - 1;
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end if;
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else
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rLockedFilterCount <= kMaxPllLockCount-1;
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rPllLockedLcl <= '0';
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end if;
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end if;
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end if;
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end process PllLockFilter;
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-- Sticky bit to hold '1' if PLL ever comes unlocked
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PllStickyBit: process (ReliableClk)
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begin
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if rising_edge(ReliableClk) then
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if (not rPllReset_n or rClearDataClkUnlockedSticky) = '1' then
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rPllUnlockedSticky <= '0';
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else
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if rPllLockedLcl = '1' and rPllLockedDs(0) = '0' then
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rPllUnlockedSticky <= '1';
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end if;
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end if;
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end if;
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end process;
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rPllLocked <= rPllLockedLcl;
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-- AXI transaction decoding
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rClearDataClkUnlockedSticky <= rSoftwareControl(kCLEAR_DATA_CLK_UNLOCKED);
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rEnableDataClk1x <= rSoftwareControl(kENABLE_DATA_CLK);
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rEnableDataClk2x <= rSoftwareControl(kENABLE_DATA_CLK_2X);
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rEnableRfdcClk1x <= rSoftwareControl(kENABLE_RF_CLK);
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rEnableRfdcClk2x <= rSoftwareControl(kENABLE_RF_CLK_2X);
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rSoftwareStatus(kDATA_CLK_PLL_LOCKED) <= rPllLockedLcl;
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rSoftwareStatus(kDATA_CLK_PLL_UNLOCKED_STICKY) <= rPllUnlockedSticky;
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end STRUCT;
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@@ -1,208 +0,0 @@
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--
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-- Copyright 2021 Ettus Research, a National Instruments Brand
|
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--
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-- SPDX-License-Identifier: LGPL-3.0-or-later
|
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--
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-- Module: rf_reset_controller
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--
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-- Description:
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--
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-- Control RFDC, ADC, and DAC resets.
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
library WORK;
|
||||
use WORK.PkgRFDC_REGS_REGMAP.all;
|
||||
|
||||
entity rf_reset_controller is
|
||||
port(
|
||||
-- Clocks
|
||||
-- Config clock is async to all the others.
|
||||
ConfigClk : in std_logic;
|
||||
DataClk : in std_logic;
|
||||
PllRefClk : in std_logic;
|
||||
RfClk : in std_logic;
|
||||
RfClk2x : in std_logic;
|
||||
DataClk2x : in std_logic;
|
||||
|
||||
-- Master resets from the Radio
|
||||
dAdcResetPulse : in std_logic;
|
||||
dDacResetPulse : in std_logic;
|
||||
|
||||
-- ADC Resets
|
||||
dAdcDataOutReset_n : out std_logic;
|
||||
r2AdcFirReset_n : out std_logic;
|
||||
rAdcRfdcAxiReset_n : out std_logic;
|
||||
rAdcEnableData : out std_logic;
|
||||
rAdcGearboxReset_n : out std_logic;
|
||||
|
||||
-- DAC Resets
|
||||
dDacDataInReset_n : out std_logic;
|
||||
r2DacFirReset_n : out std_logic;
|
||||
d2DacFirReset_n : out std_logic;
|
||||
rDacRfdcAxiReset_n : out std_logic;
|
||||
rDacGearboxReset_n : out std_logic;
|
||||
|
||||
-- SW Control and Status
|
||||
-- Control to initiate resets to RFDC and decimation block including the
|
||||
-- gearboxes. The reset status is a sticky status of both ADC and DAC.
|
||||
cSoftwareControl : in std_logic_vector(31 downto 0);
|
||||
cSoftwareStatus : out std_logic_vector(31 downto 0)
|
||||
);
|
||||
end rf_reset_controller;
|
||||
|
||||
|
||||
architecture RTL of rf_reset_controller is
|
||||
|
||||
-- POR value for all resets are high.
|
||||
signal cTriggerAdcReset : std_logic := '1';
|
||||
signal cTriggerAdcResetDlyd : std_logic := '1';
|
||||
signal cTriggerDacReset : std_logic := '1';
|
||||
signal cTriggerDacResetDlyd : std_logic := '1';
|
||||
|
||||
signal dTriggerAdcReset_ms : std_logic := '1';
|
||||
signal dTriggerAdcReset : std_logic := '1';
|
||||
signal dTriggerDacReset_ms : std_logic := '1';
|
||||
signal dTriggerDacReset : std_logic := '1';
|
||||
|
||||
-- POR value of all reset done signals are set to low.
|
||||
signal cTriggerAdcResetDone_ms : std_logic := '0';
|
||||
signal cTriggerAdcResetDone : std_logic := '0';
|
||||
signal cAdcResetDoneSticky : std_logic := '0';
|
||||
signal cTriggerDacResetDone_ms : std_logic := '0';
|
||||
signal cTriggerDacResetDone : std_logic := '0';
|
||||
signal cDacResetDoneSticky : std_logic := '0';
|
||||
|
||||
attribute ASYNC_REG : string;
|
||||
attribute ASYNC_REG of dTriggerAdcReset : signal is "TRUE";
|
||||
attribute ASYNC_REG of dTriggerDacReset : signal is "TRUE";
|
||||
attribute ASYNC_REG of cTriggerAdcResetDone : signal is "TRUE";
|
||||
attribute ASYNC_REG of cTriggerDacResetDone : signal is "TRUE";
|
||||
attribute ASYNC_REG of dTriggerAdcReset_ms : signal is "TRUE";
|
||||
attribute ASYNC_REG of dTriggerDacReset_ms : signal is "TRUE";
|
||||
attribute ASYNC_REG of cTriggerAdcResetDone_ms : signal is "TRUE";
|
||||
attribute ASYNC_REG of cTriggerDacResetDone_ms : signal is "TRUE";
|
||||
|
||||
begin
|
||||
|
||||
-- rAdcEnableData is set to '1' as we don't control the flow of RX data.
|
||||
rAdcEnableData <= '1';
|
||||
|
||||
cTriggerAdcReset <= cSoftwareControl(kADC_RESET);
|
||||
cTriggerDacReset <= cSoftwareControl(kDAC_RESET);
|
||||
|
||||
cSoftwareStatus <= (
|
||||
kADC_SEQ_DONE => cAdcResetDoneSticky,
|
||||
kDAC_SEQ_DONE => cDacResetDoneSticky,
|
||||
others => '0'
|
||||
);
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- High-Level Resets Using ConfigClk
|
||||
-----------------------------------------------------------------------------
|
||||
-- Pass the master FSM reset around to the other clock domains and then
|
||||
-- return them back to the ConfigClk domain. This is also a handy way to
|
||||
-- prove all your clocks are toggling to some extent.
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
SeqResetDataClk : process(DataClk)
|
||||
begin
|
||||
if rising_edge(DataClk) then
|
||||
-- double-syncs have no sync reset!
|
||||
dTriggerAdcReset_ms <= cTriggerAdcReset;
|
||||
dTriggerAdcReset <= dTriggerAdcReset_ms;
|
||||
dTriggerDacReset_ms <= cTriggerDacReset;
|
||||
dTriggerDacReset <= dTriggerDacReset_ms;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Reset Sequence Done Status
|
||||
-----------------------------------------------------------------------------
|
||||
-- Now back to ConfigClk! We provide the status for all software controlled
|
||||
-- resets. We move the signal from ConfigClk to DataClk domain and move it
|
||||
-- back to ConfigClk domain. This just proves that DataClk is toggling and
|
||||
-- the reset requested by software is sampled in the DataClk.
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
SeqResetDone : process(ConfigClk)
|
||||
begin
|
||||
if rising_edge(ConfigClk) then
|
||||
-- double-syncs have no sync reset!
|
||||
cTriggerAdcResetDone_ms <= dTriggerAdcReset;
|
||||
cTriggerAdcResetDone <= cTriggerAdcResetDone_ms;
|
||||
cTriggerDacResetDone_ms <= dTriggerDacReset;
|
||||
cTriggerDacResetDone <= cTriggerDacResetDone_ms;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- ADC reset done
|
||||
SwAdcResetDone: process(ConfigClk)
|
||||
begin
|
||||
if rising_edge(ConfigClk) then
|
||||
cTriggerAdcResetDlyd <= cTriggerAdcReset;
|
||||
-- De-assert reset status on the rising edge of SW ADC reset.
|
||||
if cTriggerAdcReset = '1' and cTriggerAdcResetDlyd = '0' then
|
||||
cAdcResetDoneSticky <= '0';
|
||||
-- Assert and hold the ADC reset status on ADC reset strobe.
|
||||
elsif cTriggerAdcResetDone = '1' then
|
||||
cAdcResetDoneSticky <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process SwAdcResetDone;
|
||||
|
||||
-- DAC reset done
|
||||
SwDacResetDone: process(ConfigClk)
|
||||
begin
|
||||
if rising_edge(ConfigClk) then
|
||||
cTriggerDacResetDlyd <= cTriggerDacReset;
|
||||
-- De-assert reset status on the rising edge of SW DAC reset.
|
||||
if cTriggerDacReset = '1' and cTriggerDacResetDlyd = '0' then
|
||||
cDacResetDoneSticky <= '0';
|
||||
-- Assert and hold the DAC reset status on DAC reset strobe.
|
||||
elsif cTriggerDacResetDone = '1' then
|
||||
cDacResetDoneSticky <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process SwDacResetDone;
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- rf_reset Instances
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
AdcResets: entity work.rf_reset (RTL)
|
||||
port map (
|
||||
DataClk => DataClk,
|
||||
PllRefClk => PllRefClk,
|
||||
RfClk => RfClk,
|
||||
RfClk2x => RfClk2x,
|
||||
DataClk2x => DataClk2x,
|
||||
dTimedReset => dAdcResetPulse,
|
||||
dSwReset => dTriggerAdcReset,
|
||||
dReset_n => dAdcDataOutReset_n,
|
||||
d2Reset_n => open,
|
||||
r2Reset_n => r2AdcFirReset_n,
|
||||
rAxiReset_n => rAdcRfdcAxiReset_n,
|
||||
rReset_n => rAdcGearboxReset_n
|
||||
);
|
||||
|
||||
DacResets: entity work.rf_reset (RTL)
|
||||
port map (
|
||||
DataClk => DataClk,
|
||||
PllRefClk => PllRefClk,
|
||||
RfClk => RfClk,
|
||||
RfClk2x => RfClk2x,
|
||||
DataClk2x => DataClk2x,
|
||||
dTimedReset => dDacResetPulse,
|
||||
dSwReset => dTriggerDacReset,
|
||||
dReset_n => dDacDataInReset_n,
|
||||
d2Reset_n => d2DacFirReset_n,
|
||||
r2Reset_n => r2DacFirReset_n,
|
||||
rAxiReset_n => rDacRfdcAxiReset_n,
|
||||
rReset_n => rDacGearboxReset_n
|
||||
);
|
||||
|
||||
end RTL;
|
||||
Reference in New Issue
Block a user