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fpga: Add X440/FBX support

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Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>


Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
This commit is contained in:
Javier Valenzuela
2023-06-12 10:27:29 -05:00
committed by Aki Tomita
co-authored by Martin Braun Wade Fife Ryan Marlow
parent a405111ce7
commit 5cadf901c7
121 changed files with 20670 additions and 8739 deletions
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top/x400/regmap/x440/PkgRFDC_REGS_REGMAP.vhd
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top/x400/regmap/x440/rfdc_mapping_regmap_utils.vh
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//
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: rfdc_mapping_regmap_utils.vh
// Description:
// The constants in this file are autogenerated by XmlParse.
//===============================================================================
// A numerically ordered list of registers and their HDL source files
//===============================================================================
//===============================================================================
// RegTypes
//===============================================================================
//===============================================================================
// Register Group CHANNEL_SWAPPING
//===============================================================================
// Enumerated type RFDC_ADC_MAPPING
localparam RFDC_ADC_MAPPING_SIZE = 8;
localparam CH2_RX_MAPPING = 'h0; // RFDC_ADC_MAPPING:CH2_RX_MAPPING
localparam CH1_RX_MAPPING = 'h1; // RFDC_ADC_MAPPING:CH1_RX_MAPPING
localparam CH3_RX_MAPPING = 'h2; // RFDC_ADC_MAPPING:CH3_RX_MAPPING
localparam CH0_RX_MAPPING = 'h3; // RFDC_ADC_MAPPING:CH0_RX_MAPPING
localparam CH6_RX_MAPPING = 'h4; // RFDC_ADC_MAPPING:CH6_RX_MAPPING
localparam CH5_RX_MAPPING = 'h5; // RFDC_ADC_MAPPING:CH5_RX_MAPPING
localparam CH7_RX_MAPPING = 'h6; // RFDC_ADC_MAPPING:CH7_RX_MAPPING
localparam CH4_RX_MAPPING = 'h7; // RFDC_ADC_MAPPING:CH4_RX_MAPPING
// Enumerated type RFDC_DAC_MAPPING
localparam RFDC_DAC_MAPPING_SIZE = 8;
localparam CH0_TX_MAPPING = 'h0; // RFDC_DAC_MAPPING:CH0_TX_MAPPING
localparam CH3_TX_MAPPING = 'h1; // RFDC_DAC_MAPPING:CH3_TX_MAPPING
localparam CH1_TX_MAPPING = 'h2; // RFDC_DAC_MAPPING:CH1_TX_MAPPING
localparam CH2_TX_MAPPING = 'h3; // RFDC_DAC_MAPPING:CH2_TX_MAPPING
localparam CH4_TX_MAPPING = 'h4; // RFDC_DAC_MAPPING:CH4_TX_MAPPING
localparam CH7_TX_MAPPING = 'h5; // RFDC_DAC_MAPPING:CH7_TX_MAPPING
localparam CH5_TX_MAPPING = 'h6; // RFDC_DAC_MAPPING:CH5_TX_MAPPING
localparam CH6_TX_MAPPING = 'h7; // RFDC_DAC_MAPPING:CH6_TX_MAPPING
top/x400/regmap/x440/rfdc_regs_regmap_utils.vh
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//
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: rfdc_regs_regmap_utils.vh
// Description:
// The constants in this file are autogenerated by XmlParse.
//===============================================================================
// A numerically ordered list of registers and their HDL source files
//===============================================================================
// MMCM : 0x0 (x440_rfdc_regs.v)
// INVERT_DB0_IQ_REG : 0x10000 (x440_rfdc_regs.v)
// INVERT_DB1_IQ_REG : 0x10800 (x440_rfdc_regs.v)
// MMCM_RESET_REG : 0x11000 (x440_rfdc_regs.v)
// RF0_RESET_CONTROL_REG : 0x12000 (x440_rfdc_regs.v)
// RF0_RESET_STATUS_REG : 0x12008 (x440_rfdc_regs.v)
// RF1_RESET_CONTROL_REG : 0x12800 (x440_rfdc_regs.v)
// RF1_RESET_STATUS_REG : 0x12808 (x440_rfdc_regs.v)
// RF_AXI_STATUS_REG : 0x13000 (x440_rfdc_regs.v)
// FABRIC_DSP_REG : 0x13008 (x440_rfdc_regs.v)
// CALIBRATION_DATA : 0x14000 (x440_rfdc_regs.v)
// CALIBRATION_ENABLE : 0x14008 (x440_rfdc_regs.v)
// THRESHOLD_STATUS : 0x15000 (x440_rfdc_regs.v)
// RF_PLL_CONTROL_REG : 0x16000 (x440_rfdc_regs.v)
// RF_PLL_STATUS_REG : 0x16008 (x440_rfdc_regs.v)
// ADC_TILEMAP_REG : 0x17000 (x440_rfdc_regs.v)
// DAC_TILEMAP_REG : 0x17008 (x440_rfdc_regs.v)
// RFDC_INFO_REG : 0x18000 (x440_rfdc_regs.v)
//===============================================================================
// RegTypes
//===============================================================================
// ADC_TILEMAP_REGTYPE Type (from common_regs.v)
localparam ADC_TILEMAP_REGTYPE_SIZE = 32;
localparam ADC_TILEMAP_REGTYPE_MASK = 32'hFFFFFFFF;
localparam ADC_TILEMAP_DB0_CHAN0_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_TILE
localparam ADC_TILEMAP_DB0_CHAN0_TILE_MSB = 1; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_TILE
localparam ADC_TILEMAP_DB0_CHAN0_TILE = 0; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_TILE
localparam ADC_TILEMAP_DB0_CHAN0_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_BLOCK
localparam ADC_TILEMAP_DB0_CHAN0_BLOCK_MSB = 3; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_BLOCK
localparam ADC_TILEMAP_DB0_CHAN0_BLOCK = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN0_BLOCK
localparam ADC_TILEMAP_DB0_CHAN1_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_TILE
localparam ADC_TILEMAP_DB0_CHAN1_TILE_MSB = 5; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_TILE
localparam ADC_TILEMAP_DB0_CHAN1_TILE = 4; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_TILE
localparam ADC_TILEMAP_DB0_CHAN1_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_BLOCK
localparam ADC_TILEMAP_DB0_CHAN1_BLOCK_MSB = 7; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_BLOCK
localparam ADC_TILEMAP_DB0_CHAN1_BLOCK = 6; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN1_BLOCK
localparam ADC_TILEMAP_DB0_CHAN2_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_TILE
localparam ADC_TILEMAP_DB0_CHAN2_TILE_MSB = 9; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_TILE
localparam ADC_TILEMAP_DB0_CHAN2_TILE = 8; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_TILE
localparam ADC_TILEMAP_DB0_CHAN2_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_BLOCK
localparam ADC_TILEMAP_DB0_CHAN2_BLOCK_MSB = 11; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_BLOCK
localparam ADC_TILEMAP_DB0_CHAN2_BLOCK = 10; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN2_BLOCK
localparam ADC_TILEMAP_DB0_CHAN3_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_TILE
localparam ADC_TILEMAP_DB0_CHAN3_TILE_MSB = 13; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_TILE
localparam ADC_TILEMAP_DB0_CHAN3_TILE = 12; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_TILE
localparam ADC_TILEMAP_DB0_CHAN3_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_BLOCK
localparam ADC_TILEMAP_DB0_CHAN3_BLOCK_MSB = 15; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_BLOCK
localparam ADC_TILEMAP_DB0_CHAN3_BLOCK = 14; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB0_CHAN3_BLOCK
localparam ADC_TILEMAP_DB1_CHAN0_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_TILE
localparam ADC_TILEMAP_DB1_CHAN0_TILE_MSB = 17; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_TILE
localparam ADC_TILEMAP_DB1_CHAN0_TILE = 16; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_TILE
localparam ADC_TILEMAP_DB1_CHAN0_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_BLOCK
localparam ADC_TILEMAP_DB1_CHAN0_BLOCK_MSB = 19; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_BLOCK
localparam ADC_TILEMAP_DB1_CHAN0_BLOCK = 18; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN0_BLOCK
localparam ADC_TILEMAP_DB1_CHAN1_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_TILE
localparam ADC_TILEMAP_DB1_CHAN1_TILE_MSB = 21; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_TILE
localparam ADC_TILEMAP_DB1_CHAN1_TILE = 20; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_TILE
localparam ADC_TILEMAP_DB1_CHAN1_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_BLOCK
localparam ADC_TILEMAP_DB1_CHAN1_BLOCK_MSB = 23; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_BLOCK
localparam ADC_TILEMAP_DB1_CHAN1_BLOCK = 22; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN1_BLOCK
localparam ADC_TILEMAP_DB1_CHAN2_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_TILE
localparam ADC_TILEMAP_DB1_CHAN2_TILE_MSB = 25; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_TILE
localparam ADC_TILEMAP_DB1_CHAN2_TILE = 24; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_TILE
localparam ADC_TILEMAP_DB1_CHAN2_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_BLOCK
localparam ADC_TILEMAP_DB1_CHAN2_BLOCK_MSB = 27; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_BLOCK
localparam ADC_TILEMAP_DB1_CHAN2_BLOCK = 26; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN2_BLOCK
localparam ADC_TILEMAP_DB1_CHAN3_TILE_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_TILE
localparam ADC_TILEMAP_DB1_CHAN3_TILE_MSB = 29; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_TILE
localparam ADC_TILEMAP_DB1_CHAN3_TILE = 28; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_TILE
localparam ADC_TILEMAP_DB1_CHAN3_BLOCK_SIZE = 2; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_BLOCK
localparam ADC_TILEMAP_DB1_CHAN3_BLOCK_MSB = 31; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_BLOCK
localparam ADC_TILEMAP_DB1_CHAN3_BLOCK = 30; //ADC_TILEMAP_REGTYPE:ADC_TILEMAP_DB1_CHAN3_BLOCK
// DAC_TILEMAP_REGTYPE Type (from common_regs.v)
localparam DAC_TILEMAP_REGTYPE_SIZE = 32;
localparam DAC_TILEMAP_REGTYPE_MASK = 32'hFFFFFFFF;
localparam DAC_TILEMAP_DB0_CHAN0_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_TILE
localparam DAC_TILEMAP_DB0_CHAN0_TILE_MSB = 1; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_TILE
localparam DAC_TILEMAP_DB0_CHAN0_TILE = 0; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_TILE
localparam DAC_TILEMAP_DB0_CHAN0_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_BLOCK
localparam DAC_TILEMAP_DB0_CHAN0_BLOCK_MSB = 3; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_BLOCK
localparam DAC_TILEMAP_DB0_CHAN0_BLOCK = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN0_BLOCK
localparam DAC_TILEMAP_DB0_CHAN1_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_TILE
localparam DAC_TILEMAP_DB0_CHAN1_TILE_MSB = 5; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_TILE
localparam DAC_TILEMAP_DB0_CHAN1_TILE = 4; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_TILE
localparam DAC_TILEMAP_DB0_CHAN1_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_BLOCK
localparam DAC_TILEMAP_DB0_CHAN1_BLOCK_MSB = 7; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_BLOCK
localparam DAC_TILEMAP_DB0_CHAN1_BLOCK = 6; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN1_BLOCK
localparam DAC_TILEMAP_DB0_CHAN2_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_TILE
localparam DAC_TILEMAP_DB0_CHAN2_TILE_MSB = 9; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_TILE
localparam DAC_TILEMAP_DB0_CHAN2_TILE = 8; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_TILE
localparam DAC_TILEMAP_DB0_CHAN2_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_BLOCK
localparam DAC_TILEMAP_DB0_CHAN2_BLOCK_MSB = 11; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_BLOCK
localparam DAC_TILEMAP_DB0_CHAN2_BLOCK = 10; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN2_BLOCK
localparam DAC_TILEMAP_DB0_CHAN3_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_TILE
localparam DAC_TILEMAP_DB0_CHAN3_TILE_MSB = 13; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_TILE
localparam DAC_TILEMAP_DB0_CHAN3_TILE = 12; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_TILE
localparam DAC_TILEMAP_DB0_CHAN3_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_BLOCK
localparam DAC_TILEMAP_DB0_CHAN3_BLOCK_MSB = 15; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_BLOCK
localparam DAC_TILEMAP_DB0_CHAN3_BLOCK = 14; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB0_CHAN3_BLOCK
localparam DAC_TILEMAP_DB1_CHAN0_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_TILE
localparam DAC_TILEMAP_DB1_CHAN0_TILE_MSB = 17; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_TILE
localparam DAC_TILEMAP_DB1_CHAN0_TILE = 16; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_TILE
localparam DAC_TILEMAP_DB1_CHAN0_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_BLOCK
localparam DAC_TILEMAP_DB1_CHAN0_BLOCK_MSB = 19; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_BLOCK
localparam DAC_TILEMAP_DB1_CHAN0_BLOCK = 18; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN0_BLOCK
localparam DAC_TILEMAP_DB1_CHAN1_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_TILE
localparam DAC_TILEMAP_DB1_CHAN1_TILE_MSB = 21; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_TILE
localparam DAC_TILEMAP_DB1_CHAN1_TILE = 20; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_TILE
localparam DAC_TILEMAP_DB1_CHAN1_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_BLOCK
localparam DAC_TILEMAP_DB1_CHAN1_BLOCK_MSB = 23; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_BLOCK
localparam DAC_TILEMAP_DB1_CHAN1_BLOCK = 22; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN1_BLOCK
localparam DAC_TILEMAP_DB1_CHAN2_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_TILE
localparam DAC_TILEMAP_DB1_CHAN2_TILE_MSB = 25; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_TILE
localparam DAC_TILEMAP_DB1_CHAN2_TILE = 24; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_TILE
localparam DAC_TILEMAP_DB1_CHAN2_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_BLOCK
localparam DAC_TILEMAP_DB1_CHAN2_BLOCK_MSB = 27; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_BLOCK
localparam DAC_TILEMAP_DB1_CHAN2_BLOCK = 26; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN2_BLOCK
localparam DAC_TILEMAP_DB1_CHAN3_TILE_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_TILE
localparam DAC_TILEMAP_DB1_CHAN3_TILE_MSB = 29; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_TILE
localparam DAC_TILEMAP_DB1_CHAN3_TILE = 28; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_TILE
localparam DAC_TILEMAP_DB1_CHAN3_BLOCK_SIZE = 2; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_BLOCK
localparam DAC_TILEMAP_DB1_CHAN3_BLOCK_MSB = 31; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_BLOCK
localparam DAC_TILEMAP_DB1_CHAN3_BLOCK = 30; //DAC_TILEMAP_REGTYPE:DAC_TILEMAP_DB1_CHAN3_BLOCK
// FABRIC_DSP_REGTYPE Type (from common_regs.v)
localparam FABRIC_DSP_REGTYPE_SIZE = 32;
localparam FABRIC_DSP_REGTYPE_MASK = 32'hFFFFFFFF;
localparam FABRIC_DSP_RX_CNT_SIZE = 4; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT
localparam FABRIC_DSP_RX_CNT_MSB = 3; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT
localparam FABRIC_DSP_RX_CNT = 0; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT
localparam FABRIC_DSP_TX_CNT_SIZE = 4; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT
localparam FABRIC_DSP_TX_CNT_MSB = 7; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT
localparam FABRIC_DSP_TX_CNT = 4; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT
localparam FABRIC_DSP_RESERVED_SIZE = 2; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED
localparam FABRIC_DSP_RESERVED_MSB = 9; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED
localparam FABRIC_DSP_RESERVED = 8; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED
localparam FABRIC_DSP_RX_CNT_DB1_SIZE = 4; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT_DB1
localparam FABRIC_DSP_RX_CNT_DB1_MSB = 13; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT_DB1
localparam FABRIC_DSP_RX_CNT_DB1 = 10; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RX_CNT_DB1
localparam FABRIC_DSP_TX_CNT_DB1_SIZE = 4; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT_DB1
localparam FABRIC_DSP_TX_CNT_DB1_MSB = 17; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT_DB1
localparam FABRIC_DSP_TX_CNT_DB1 = 14; //FABRIC_DSP_REGTYPE:FABRIC_DSP_TX_CNT_DB1
localparam FABRIC_DSP_RESERVED_DB1_SIZE = 2; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED_DB1
localparam FABRIC_DSP_RESERVED_DB1_MSB = 19; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED_DB1
localparam FABRIC_DSP_RESERVED_DB1 = 18; //FABRIC_DSP_REGTYPE:FABRIC_DSP_RESERVED_DB1
localparam FABRIC_DSP_BW_SIZE = 12; //FABRIC_DSP_REGTYPE:FABRIC_DSP_BW
localparam FABRIC_DSP_BW_MSB = 31; //FABRIC_DSP_REGTYPE:FABRIC_DSP_BW
localparam FABRIC_DSP_BW = 20; //FABRIC_DSP_REGTYPE:FABRIC_DSP_BW
// RF_AXI_STATUS_REGTYPE Type (from common_regs.v)
localparam RF_AXI_STATUS_REGTYPE_SIZE = 32;
localparam RF_AXI_STATUS_REGTYPE_MASK = 32'hFFFFFFFF;
localparam RFDC_DAC_TREADY_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY
localparam RFDC_DAC_TREADY_MSB = 1; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY
localparam RFDC_DAC_TREADY = 0; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY
localparam RFDC_DAC_TVALID_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID
localparam RFDC_DAC_TVALID_MSB = 3; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID
localparam RFDC_DAC_TVALID = 2; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID
localparam RFDC_ADC_Q_TREADY_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY
localparam RFDC_ADC_Q_TREADY_MSB = 5; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY
localparam RFDC_ADC_Q_TREADY = 4; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY
localparam RFDC_ADC_I_TREADY_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY
localparam RFDC_ADC_I_TREADY_MSB = 7; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY
localparam RFDC_ADC_I_TREADY = 6; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY
localparam RFDC_ADC_Q_TVALID_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID
localparam RFDC_ADC_Q_TVALID_MSB = 9; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID
localparam RFDC_ADC_Q_TVALID = 8; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID
localparam RFDC_ADC_I_TVALID_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID
localparam RFDC_ADC_I_TVALID_MSB = 11; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID
localparam RFDC_ADC_I_TVALID = 10; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID
localparam USER_ADC_TVALID_SIZE = 2; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID
localparam USER_ADC_TVALID_MSB = 13; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID
localparam USER_ADC_TVALID = 12; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID
localparam USER_ADC_TREADY_SIZE = 2; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY
localparam USER_ADC_TREADY_MSB = 15; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY
localparam USER_ADC_TREADY = 14; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY
localparam RFDC_DAC_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY_DB1
localparam RFDC_DAC_TREADY_DB1_MSB = 17; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY_DB1
localparam RFDC_DAC_TREADY_DB1 = 16; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TREADY_DB1
localparam RFDC_DAC_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID_DB1
localparam RFDC_DAC_TVALID_DB1_MSB = 19; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID_DB1
localparam RFDC_DAC_TVALID_DB1 = 18; //RF_AXI_STATUS_REGTYPE:RFDC_DAC_TVALID_DB1
localparam RFDC_ADC_Q_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY_DB1
localparam RFDC_ADC_Q_TREADY_DB1_MSB = 21; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY_DB1
localparam RFDC_ADC_Q_TREADY_DB1 = 20; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TREADY_DB1
localparam RFDC_ADC_I_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY_DB1
localparam RFDC_ADC_I_TREADY_DB1_MSB = 23; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY_DB1
localparam RFDC_ADC_I_TREADY_DB1 = 22; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TREADY_DB1
localparam RFDC_ADC_Q_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID_DB1
localparam RFDC_ADC_Q_TVALID_DB1_MSB = 25; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID_DB1
localparam RFDC_ADC_Q_TVALID_DB1 = 24; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_Q_TVALID_DB1
localparam RFDC_ADC_I_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID_DB1
localparam RFDC_ADC_I_TVALID_DB1_MSB = 27; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID_DB1
localparam RFDC_ADC_I_TVALID_DB1 = 26; //RF_AXI_STATUS_REGTYPE:RFDC_ADC_I_TVALID_DB1
localparam USER_ADC_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID_DB1
localparam USER_ADC_TVALID_DB1_MSB = 29; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID_DB1
localparam USER_ADC_TVALID_DB1 = 28; //RF_AXI_STATUS_REGTYPE:USER_ADC_TVALID_DB1
localparam USER_ADC_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY_DB1
localparam USER_ADC_TREADY_DB1_MSB = 31; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY_DB1
localparam USER_ADC_TREADY_DB1 = 30; //RF_AXI_STATUS_REGTYPE:USER_ADC_TREADY_DB1
// RF_RESET_CONTROL_REGTYPE Type (from common_regs.v)
localparam RF_RESET_CONTROL_REGTYPE_SIZE = 32;
localparam RF_RESET_CONTROL_REGTYPE_MASK = 32'h331;
localparam FSM_RESET_SIZE = 1; //RF_RESET_CONTROL_REGTYPE:FSM_RESET
localparam FSM_RESET_MSB = 0; //RF_RESET_CONTROL_REGTYPE:FSM_RESET
localparam FSM_RESET = 0; //RF_RESET_CONTROL_REGTYPE:FSM_RESET
localparam ADC_RESET_SIZE = 1; //RF_RESET_CONTROL_REGTYPE:ADC_RESET
localparam ADC_RESET_MSB = 4; //RF_RESET_CONTROL_REGTYPE:ADC_RESET
localparam ADC_RESET = 4; //RF_RESET_CONTROL_REGTYPE:ADC_RESET
localparam ADC_ENABLE_SIZE = 1; //RF_RESET_CONTROL_REGTYPE:ADC_ENABLE
localparam ADC_ENABLE_MSB = 5; //RF_RESET_CONTROL_REGTYPE:ADC_ENABLE
localparam ADC_ENABLE = 5; //RF_RESET_CONTROL_REGTYPE:ADC_ENABLE
localparam DAC_RESET_SIZE = 1; //RF_RESET_CONTROL_REGTYPE:DAC_RESET
localparam DAC_RESET_MSB = 8; //RF_RESET_CONTROL_REGTYPE:DAC_RESET
localparam DAC_RESET = 8; //RF_RESET_CONTROL_REGTYPE:DAC_RESET
localparam DAC_ENABLE_SIZE = 1; //RF_RESET_CONTROL_REGTYPE:DAC_ENABLE
localparam DAC_ENABLE_MSB = 9; //RF_RESET_CONTROL_REGTYPE:DAC_ENABLE
localparam DAC_ENABLE = 9; //RF_RESET_CONTROL_REGTYPE:DAC_ENABLE
// RF_RESET_STATUS_REGTYPE Type (from common_regs.v)
localparam RF_RESET_STATUS_REGTYPE_SIZE = 32;
localparam RF_RESET_STATUS_REGTYPE_MASK = 32'h888;
localparam FSM_RESET_DONE_SIZE = 1; //RF_RESET_STATUS_REGTYPE:FSM_RESET_DONE
localparam FSM_RESET_DONE_MSB = 3; //RF_RESET_STATUS_REGTYPE:FSM_RESET_DONE
localparam FSM_RESET_DONE = 3; //RF_RESET_STATUS_REGTYPE:FSM_RESET_DONE
localparam ADC_SEQ_DONE_SIZE = 1; //RF_RESET_STATUS_REGTYPE:ADC_SEQ_DONE
localparam ADC_SEQ_DONE_MSB = 7; //RF_RESET_STATUS_REGTYPE:ADC_SEQ_DONE
localparam ADC_SEQ_DONE = 7; //RF_RESET_STATUS_REGTYPE:ADC_SEQ_DONE
localparam DAC_SEQ_DONE_SIZE = 1; //RF_RESET_STATUS_REGTYPE:DAC_SEQ_DONE
localparam DAC_SEQ_DONE_MSB = 11; //RF_RESET_STATUS_REGTYPE:DAC_SEQ_DONE
localparam DAC_SEQ_DONE = 11; //RF_RESET_STATUS_REGTYPE:DAC_SEQ_DONE
// RFDC_INFO_REGTYPE Type (from common_regs.v)
localparam RFDC_INFO_REGTYPE_SIZE = 32;
localparam RFDC_INFO_REGTYPE_MASK = 32'h3FF03FF;
localparam RFDC_INFO_XTRA_RESAMP_SIZE = 4; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP
localparam RFDC_INFO_XTRA_RESAMP_MSB = 3; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP
localparam RFDC_INFO_XTRA_RESAMP = 0; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP
localparam RFDC_INFO_SPC_RX_SIZE = 3; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX
localparam RFDC_INFO_SPC_RX_MSB = 6; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX
localparam RFDC_INFO_SPC_RX = 4; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX
localparam RFDC_INFO_SPC_TX_SIZE = 3; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX
localparam RFDC_INFO_SPC_TX_MSB = 9; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX
localparam RFDC_INFO_SPC_TX = 7; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX
localparam RFDC_INFO_XTRA_RESAMP_DB1_SIZE = 4; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP_DB1
localparam RFDC_INFO_XTRA_RESAMP_DB1_MSB = 19; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP_DB1
localparam RFDC_INFO_XTRA_RESAMP_DB1 = 16; //RFDC_INFO_REGTYPE:RFDC_INFO_XTRA_RESAMP_DB1
localparam RFDC_INFO_SPC_RX_DB1_SIZE = 3; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX_DB1
localparam RFDC_INFO_SPC_RX_DB1_MSB = 22; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX_DB1
localparam RFDC_INFO_SPC_RX_DB1 = 20; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_RX_DB1
localparam RFDC_INFO_SPC_TX_DB1_SIZE = 3; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX_DB1
localparam RFDC_INFO_SPC_TX_DB1_MSB = 25; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX_DB1
localparam RFDC_INFO_SPC_TX_DB1 = 23; //RFDC_INFO_REGTYPE:RFDC_INFO_SPC_TX_DB1
//===============================================================================
// Register Group RFDC_REGS
//===============================================================================
// Enumerated type FABRIC_DSP_BW_ENUM
localparam FABRIC_DSP_BW_ENUM_SIZE = 5;
localparam FABRIC_DSP_BW_NONE = 'h0; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_NONE
localparam FABRIC_DSP_BW_100M = 'h64; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_100M
localparam FABRIC_DSP_BW_200M = 'hC8; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_200M
localparam FABRIC_DSP_BW_400M = 'h190; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_400M
localparam FABRIC_DSP_BW_FULL = 'h3E8; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_FULL
// MMCM Window (from x440_rfdc_regs.v)
localparam MMCM = 'h0; // Window Offset
localparam MMCM_SIZE = 'h10000; // size in bytes
// INVERT_DB0_IQ_REG Register (from x440_rfdc_regs.v)
localparam INVERT_DB0_IQ_REG = 'h10000; // Register Offset
localparam INVERT_DB0_IQ_REG_SIZE = 32; // register width in bits
localparam INVERT_DB0_IQ_REG_MASK = 32'hF0F;
localparam INVERT_DB0_ADC0_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC0_IQ
localparam INVERT_DB0_ADC0_IQ_MSB = 0; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC0_IQ
localparam INVERT_DB0_ADC0_IQ = 0; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC0_IQ
localparam INVERT_DB0_ADC1_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC1_IQ
localparam INVERT_DB0_ADC1_IQ_MSB = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC1_IQ
localparam INVERT_DB0_ADC1_IQ = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC1_IQ
localparam INVERT_DB0_ADC2_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC2_IQ
localparam INVERT_DB0_ADC2_IQ_MSB = 2; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC2_IQ
localparam INVERT_DB0_ADC2_IQ = 2; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC2_IQ
localparam INVERT_DB0_ADC3_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC3_IQ
localparam INVERT_DB0_ADC3_IQ_MSB = 3; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC3_IQ
localparam INVERT_DB0_ADC3_IQ = 3; //INVERT_DB0_IQ_REG:INVERT_DB0_ADC3_IQ
localparam INVERT_DB0_DAC0_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC0_IQ
localparam INVERT_DB0_DAC0_IQ_MSB = 8; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC0_IQ
localparam INVERT_DB0_DAC0_IQ = 8; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC0_IQ
localparam INVERT_DB0_DAC1_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC1_IQ
localparam INVERT_DB0_DAC1_IQ_MSB = 9; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC1_IQ
localparam INVERT_DB0_DAC1_IQ = 9; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC1_IQ
localparam INVERT_DB0_DAC2_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC2_IQ
localparam INVERT_DB0_DAC2_IQ_MSB = 10; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC2_IQ
localparam INVERT_DB0_DAC2_IQ = 10; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC2_IQ
localparam INVERT_DB0_DAC3_IQ_SIZE = 1; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC3_IQ
localparam INVERT_DB0_DAC3_IQ_MSB = 11; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC3_IQ
localparam INVERT_DB0_DAC3_IQ = 11; //INVERT_DB0_IQ_REG:INVERT_DB0_DAC3_IQ
// INVERT_DB1_IQ_REG Register (from x440_rfdc_regs.v)
localparam INVERT_DB1_IQ_REG = 'h10800; // Register Offset
localparam INVERT_DB1_IQ_REG_SIZE = 32; // register width in bits
localparam INVERT_DB1_IQ_REG_MASK = 32'hF0F;
localparam INVERT_DB1_ADC0_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC0_IQ
localparam INVERT_DB1_ADC0_IQ_MSB = 0; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC0_IQ
localparam INVERT_DB1_ADC0_IQ = 0; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC0_IQ
localparam INVERT_DB1_ADC1_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC1_IQ
localparam INVERT_DB1_ADC1_IQ_MSB = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC1_IQ
localparam INVERT_DB1_ADC1_IQ = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC1_IQ
localparam INVERT_DB1_ADC2_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC2_IQ
localparam INVERT_DB1_ADC2_IQ_MSB = 2; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC2_IQ
localparam INVERT_DB1_ADC2_IQ = 2; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC2_IQ
localparam INVERT_DB1_ADC3_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC3_IQ
localparam INVERT_DB1_ADC3_IQ_MSB = 3; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC3_IQ
localparam INVERT_DB1_ADC3_IQ = 3; //INVERT_DB1_IQ_REG:INVERT_DB1_ADC3_IQ
localparam INVERT_DB1_DAC0_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC0_IQ
localparam INVERT_DB1_DAC0_IQ_MSB = 8; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC0_IQ
localparam INVERT_DB1_DAC0_IQ = 8; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC0_IQ
localparam INVERT_DB1_DAC1_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC1_IQ
localparam INVERT_DB1_DAC1_IQ_MSB = 9; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC1_IQ
localparam INVERT_DB1_DAC1_IQ = 9; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC1_IQ
localparam INVERT_DB1_DAC2_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC2_IQ
localparam INVERT_DB1_DAC2_IQ_MSB = 10; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC2_IQ
localparam INVERT_DB1_DAC2_IQ = 10; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC2_IQ
localparam INVERT_DB1_DAC3_IQ_SIZE = 1; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC3_IQ
localparam INVERT_DB1_DAC3_IQ_MSB = 11; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC3_IQ
localparam INVERT_DB1_DAC3_IQ = 11; //INVERT_DB1_IQ_REG:INVERT_DB1_DAC3_IQ
// MMCM_RESET_REG Register (from x440_rfdc_regs.v)
localparam MMCM_RESET_REG = 'h11000; // Register Offset
localparam MMCM_RESET_REG_SIZE = 32; // register width in bits
localparam MMCM_RESET_REG_MASK = 32'h1;
localparam RESET_MMCM_SIZE = 1; //MMCM_RESET_REG:RESET_MMCM
localparam RESET_MMCM_MSB = 0; //MMCM_RESET_REG:RESET_MMCM
localparam RESET_MMCM = 0; //MMCM_RESET_REG:RESET_MMCM
// RF0_RESET_CONTROL_REG Register (from x440_rfdc_regs.v)
localparam RF0_RESET_CONTROL_REG = 'h12000; // Register Offset
localparam RF0_RESET_CONTROL_REG_SIZE = 32; // register width in bits
// RF0_RESET_STATUS_REG Register (from x440_rfdc_regs.v)
localparam RF0_RESET_STATUS_REG = 'h12008; // Register Offset
localparam RF0_RESET_STATUS_REG_SIZE = 32; // register width in bits
// RF1_RESET_CONTROL_REG Register (from x440_rfdc_regs.v)
localparam RF1_RESET_CONTROL_REG = 'h12800; // Register Offset
localparam RF1_RESET_CONTROL_REG_SIZE = 32; // register width in bits
// RF1_RESET_STATUS_REG Register (from x440_rfdc_regs.v)
localparam RF1_RESET_STATUS_REG = 'h12808; // Register Offset
localparam RF1_RESET_STATUS_REG_SIZE = 32; // register width in bits
// RF_AXI_STATUS_REG Register (from x440_rfdc_regs.v)
localparam RF_AXI_STATUS_REG = 'h13000; // Register Offset
localparam RF_AXI_STATUS_REG_SIZE = 32; // register width in bits
// FABRIC_DSP_REG Register (from x440_rfdc_regs.v)
localparam FABRIC_DSP_REG = 'h13008; // Register Offset
localparam FABRIC_DSP_REG_SIZE = 32; // register width in bits
// CALIBRATION_DATA Register (from x440_rfdc_regs.v)
localparam CALIBRATION_DATA = 'h14000; // Register Offset
localparam CALIBRATION_DATA_SIZE = 32; // register width in bits
localparam CALIBRATION_DATA_MASK = 32'hFFFFFFFF;
localparam I_DATA_SIZE = 16; //CALIBRATION_DATA:I_DATA
localparam I_DATA_MSB = 15; //CALIBRATION_DATA:I_DATA
localparam I_DATA = 0; //CALIBRATION_DATA:I_DATA
localparam Q_DATA_SIZE = 16; //CALIBRATION_DATA:Q_DATA
localparam Q_DATA_MSB = 31; //CALIBRATION_DATA:Q_DATA
localparam Q_DATA = 16; //CALIBRATION_DATA:Q_DATA
// CALIBRATION_ENABLE Register (from x440_rfdc_regs.v)
localparam CALIBRATION_ENABLE = 'h14008; // Register Offset
localparam CALIBRATION_ENABLE_SIZE = 32; // register width in bits
localparam CALIBRATION_ENABLE_MASK = 32'hFF;
localparam ENABLE_CALIBRATION_DATA_0_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0
localparam ENABLE_CALIBRATION_DATA_0_MSB = 0; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0
localparam ENABLE_CALIBRATION_DATA_0 = 0; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0
localparam ENABLE_CALIBRATION_DATA_1_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1
localparam ENABLE_CALIBRATION_DATA_1_MSB = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1
localparam ENABLE_CALIBRATION_DATA_1 = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1
localparam ENABLE_CALIBRATION_DATA_2_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2
localparam ENABLE_CALIBRATION_DATA_2_MSB = 2; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2
localparam ENABLE_CALIBRATION_DATA_2 = 2; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2
localparam ENABLE_CALIBRATION_DATA_3_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3
localparam ENABLE_CALIBRATION_DATA_3_MSB = 3; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3
localparam ENABLE_CALIBRATION_DATA_3 = 3; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3
localparam ENABLE_CALIBRATION_DATA_4_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_4
localparam ENABLE_CALIBRATION_DATA_4_MSB = 4; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_4
localparam ENABLE_CALIBRATION_DATA_4 = 4; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_4
localparam ENABLE_CALIBRATION_DATA_5_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_5
localparam ENABLE_CALIBRATION_DATA_5_MSB = 5; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_5
localparam ENABLE_CALIBRATION_DATA_5 = 5; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_5
localparam ENABLE_CALIBRATION_DATA_6_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_6
localparam ENABLE_CALIBRATION_DATA_6_MSB = 6; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_6
localparam ENABLE_CALIBRATION_DATA_6 = 6; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_6
localparam ENABLE_CALIBRATION_DATA_7_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_7
localparam ENABLE_CALIBRATION_DATA_7_MSB = 7; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_7
localparam ENABLE_CALIBRATION_DATA_7 = 7; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_7
// THRESHOLD_STATUS Register (from x440_rfdc_regs.v)
localparam THRESHOLD_STATUS = 'h15000; // Register Offset
localparam THRESHOLD_STATUS_SIZE = 32; // register width in bits
localparam THRESHOLD_STATUS_MASK = 32'hFFFF;
localparam ADC0_01_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD1
localparam ADC0_01_THRESHOLD1_MSB = 0; //THRESHOLD_STATUS:ADC0_01_THRESHOLD1
localparam ADC0_01_THRESHOLD1 = 0; //THRESHOLD_STATUS:ADC0_01_THRESHOLD1
localparam ADC0_01_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD2
localparam ADC0_01_THRESHOLD2_MSB = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD2
localparam ADC0_01_THRESHOLD2 = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD2
localparam ADC0_23_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC0_23_THRESHOLD1
localparam ADC0_23_THRESHOLD1_MSB = 2; //THRESHOLD_STATUS:ADC0_23_THRESHOLD1
localparam ADC0_23_THRESHOLD1 = 2; //THRESHOLD_STATUS:ADC0_23_THRESHOLD1
localparam ADC0_23_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC0_23_THRESHOLD2
localparam ADC0_23_THRESHOLD2_MSB = 3; //THRESHOLD_STATUS:ADC0_23_THRESHOLD2
localparam ADC0_23_THRESHOLD2 = 3; //THRESHOLD_STATUS:ADC0_23_THRESHOLD2
localparam ADC1_01_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC1_01_THRESHOLD1
localparam ADC1_01_THRESHOLD1_MSB = 4; //THRESHOLD_STATUS:ADC1_01_THRESHOLD1
localparam ADC1_01_THRESHOLD1 = 4; //THRESHOLD_STATUS:ADC1_01_THRESHOLD1
localparam ADC1_01_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC1_01_THRESHOLD2
localparam ADC1_01_THRESHOLD2_MSB = 5; //THRESHOLD_STATUS:ADC1_01_THRESHOLD2
localparam ADC1_01_THRESHOLD2 = 5; //THRESHOLD_STATUS:ADC1_01_THRESHOLD2
localparam ADC1_23_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC1_23_THRESHOLD1
localparam ADC1_23_THRESHOLD1_MSB = 6; //THRESHOLD_STATUS:ADC1_23_THRESHOLD1
localparam ADC1_23_THRESHOLD1 = 6; //THRESHOLD_STATUS:ADC1_23_THRESHOLD1
localparam ADC1_23_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC1_23_THRESHOLD2
localparam ADC1_23_THRESHOLD2_MSB = 7; //THRESHOLD_STATUS:ADC1_23_THRESHOLD2
localparam ADC1_23_THRESHOLD2 = 7; //THRESHOLD_STATUS:ADC1_23_THRESHOLD2
localparam ADC2_01_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC2_01_THRESHOLD1
localparam ADC2_01_THRESHOLD1_MSB = 8; //THRESHOLD_STATUS:ADC2_01_THRESHOLD1
localparam ADC2_01_THRESHOLD1 = 8; //THRESHOLD_STATUS:ADC2_01_THRESHOLD1
localparam ADC2_01_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC2_01_THRESHOLD2
localparam ADC2_01_THRESHOLD2_MSB = 9; //THRESHOLD_STATUS:ADC2_01_THRESHOLD2
localparam ADC2_01_THRESHOLD2 = 9; //THRESHOLD_STATUS:ADC2_01_THRESHOLD2
localparam ADC2_23_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC2_23_THRESHOLD1
localparam ADC2_23_THRESHOLD1_MSB = 10; //THRESHOLD_STATUS:ADC2_23_THRESHOLD1
localparam ADC2_23_THRESHOLD1 = 10; //THRESHOLD_STATUS:ADC2_23_THRESHOLD1
localparam ADC2_23_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC2_23_THRESHOLD2
localparam ADC2_23_THRESHOLD2_MSB = 11; //THRESHOLD_STATUS:ADC2_23_THRESHOLD2
localparam ADC2_23_THRESHOLD2 = 11; //THRESHOLD_STATUS:ADC2_23_THRESHOLD2
localparam ADC3_01_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC3_01_THRESHOLD1
localparam ADC3_01_THRESHOLD1_MSB = 12; //THRESHOLD_STATUS:ADC3_01_THRESHOLD1
localparam ADC3_01_THRESHOLD1 = 12; //THRESHOLD_STATUS:ADC3_01_THRESHOLD1
localparam ADC3_01_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC3_01_THRESHOLD2
localparam ADC3_01_THRESHOLD2_MSB = 13; //THRESHOLD_STATUS:ADC3_01_THRESHOLD2
localparam ADC3_01_THRESHOLD2 = 13; //THRESHOLD_STATUS:ADC3_01_THRESHOLD2
localparam ADC3_23_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC3_23_THRESHOLD1
localparam ADC3_23_THRESHOLD1_MSB = 14; //THRESHOLD_STATUS:ADC3_23_THRESHOLD1
localparam ADC3_23_THRESHOLD1 = 14; //THRESHOLD_STATUS:ADC3_23_THRESHOLD1
localparam ADC3_23_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC3_23_THRESHOLD2
localparam ADC3_23_THRESHOLD2_MSB = 15; //THRESHOLD_STATUS:ADC3_23_THRESHOLD2
localparam ADC3_23_THRESHOLD2 = 15; //THRESHOLD_STATUS:ADC3_23_THRESHOLD2
// RF_PLL_CONTROL_REG Register (from x440_rfdc_regs.v)
localparam RF_PLL_CONTROL_REG = 'h16000; // Register Offset
localparam RF_PLL_CONTROL_REG_SIZE = 32; // register width in bits
localparam RF_PLL_CONTROL_REG_MASK = 32'h1111100;
localparam ENABLE_RF0_CLK_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_RF0_CLK
localparam ENABLE_RF0_CLK_MSB = 8; //RF_PLL_CONTROL_REG:ENABLE_RF0_CLK
localparam ENABLE_RF0_CLK = 8; //RF_PLL_CONTROL_REG:ENABLE_RF0_CLK
localparam ENABLE_RF0_CLK_2X_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_RF0_CLK_2X
localparam ENABLE_RF0_CLK_2X_MSB = 12; //RF_PLL_CONTROL_REG:ENABLE_RF0_CLK_2X
localparam ENABLE_RF0_CLK_2X = 12; //RF_PLL_CONTROL_REG:ENABLE_RF0_CLK_2X
localparam CLEAR_DATA_CLK_UNLOCKED_SIZE = 1; //RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED
localparam CLEAR_DATA_CLK_UNLOCKED_MSB = 16; //RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED
localparam CLEAR_DATA_CLK_UNLOCKED = 16; //RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED
localparam ENABLE_RF1_CLK_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_RF1_CLK
localparam ENABLE_RF1_CLK_MSB = 20; //RF_PLL_CONTROL_REG:ENABLE_RF1_CLK
localparam ENABLE_RF1_CLK = 20; //RF_PLL_CONTROL_REG:ENABLE_RF1_CLK
localparam ENABLE_RF1_CLK_2X_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_RF1_CLK_2X
localparam ENABLE_RF1_CLK_2X_MSB = 24; //RF_PLL_CONTROL_REG:ENABLE_RF1_CLK_2X
localparam ENABLE_RF1_CLK_2X = 24; //RF_PLL_CONTROL_REG:ENABLE_RF1_CLK_2X
// RF_PLL_STATUS_REG Register (from x440_rfdc_regs.v)
localparam RF_PLL_STATUS_REG = 'h16008; // Register Offset
localparam RF_PLL_STATUS_REG_SIZE = 32; // register width in bits
localparam RF_PLL_STATUS_REG_MASK = 32'h110000;
localparam DATA_CLK_PLL_UNLOCKED_STICKY_SIZE = 1; //RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY
localparam DATA_CLK_PLL_UNLOCKED_STICKY_MSB = 16; //RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY
localparam DATA_CLK_PLL_UNLOCKED_STICKY = 16; //RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY
localparam DATA_CLK_PLL_LOCKED_SIZE = 1; //RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED
localparam DATA_CLK_PLL_LOCKED_MSB = 20; //RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED
localparam DATA_CLK_PLL_LOCKED = 20; //RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED
// ADC_TILEMAP_REG Register (from x440_rfdc_regs.v)
localparam ADC_TILEMAP_REG = 'h17000; // Register Offset
localparam ADC_TILEMAP_REG_SIZE = 32; // register width in bits
// DAC_TILEMAP_REG Register (from x440_rfdc_regs.v)
localparam DAC_TILEMAP_REG = 'h17008; // Register Offset
localparam DAC_TILEMAP_REG_SIZE = 32; // register width in bits
// RFDC_INFO_REG Register (from x440_rfdc_regs.v)
localparam RFDC_INFO_REG = 'h18000; // Register Offset
localparam RFDC_INFO_REG_SIZE = 32; // register width in bits
top/x400/regmap/x440/versioning_regs_regmap_utils.vh
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//
// Copyright 2023 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: versioning_regs_regmap_utils.vh
// Description:
// The constants in this file are autogenerated by XmlParse.
//===============================================================================
// A numerically ordered list of registers and their HDL source files
//===============================================================================
// CURRENT_VERSION : 0x0 (x4xx_versioning_regs.v)
// OLDEST_COMPATIBLE_VERSION : 0x4 (x4xx_versioning_regs.v)
// VERSION_LAST_MODIFIED : 0x8 (x4xx_versioning_regs.v)
// RESERVED : 0xC (x4xx_versioning_regs.v)
//===============================================================================
// RegTypes
//===============================================================================
// RESERVED_TYPE Type (from x4xx_versioning_regs.v)
localparam RESERVED_TYPE_SIZE = 32;
localparam RESERVED_TYPE_MASK = 32'h0;
// TIMESTAMP_TYPE Type (from x4xx_versioning_regs.v)
localparam TIMESTAMP_TYPE_SIZE = 32;
localparam TIMESTAMP_TYPE_MASK = 32'hFFFFFFFF;
localparam HH_SIZE = 8; //TIMESTAMP_TYPE:HH
localparam HH_MSB = 7; //TIMESTAMP_TYPE:HH
localparam HH = 0; //TIMESTAMP_TYPE:HH
localparam DD_SIZE = 8; //TIMESTAMP_TYPE:DD
localparam DD_MSB = 15; //TIMESTAMP_TYPE:DD
localparam DD = 8; //TIMESTAMP_TYPE:DD
localparam MM_SIZE = 8; //TIMESTAMP_TYPE:MM
localparam MM_MSB = 23; //TIMESTAMP_TYPE:MM
localparam MM = 16; //TIMESTAMP_TYPE:MM
localparam YY_SIZE = 8; //TIMESTAMP_TYPE:YY
localparam YY_MSB = 31; //TIMESTAMP_TYPE:YY
localparam YY = 24; //TIMESTAMP_TYPE:YY
// VERSION_TYPE Type (from x4xx_versioning_regs.v)
localparam VERSION_TYPE_SIZE = 32;
localparam VERSION_TYPE_MASK = 32'hFFFFFFFF;
localparam BUILD_SIZE = 12; //VERSION_TYPE:BUILD
localparam BUILD_MSB = 11; //VERSION_TYPE:BUILD
localparam BUILD = 0; //VERSION_TYPE:BUILD
localparam MINOR_SIZE = 11; //VERSION_TYPE:MINOR
localparam MINOR_MSB = 22; //VERSION_TYPE:MINOR
localparam MINOR = 12; //VERSION_TYPE:MINOR
localparam MAJOR_SIZE = 9; //VERSION_TYPE:MAJOR
localparam MAJOR_MSB = 31; //VERSION_TYPE:MAJOR
localparam MAJOR = 23; //VERSION_TYPE:MAJOR
//===============================================================================
// Register Group VERSIONING_CONSTANTS
//===============================================================================
// Enumerated type CPLD_IFC_VERSION
localparam CPLD_IFC_VERSION_SIZE = 7;
localparam CPLD_IFC_CURRENT_VERSION_MINOR = 'h0; // CPLD_IFC_VERSION:CPLD_IFC_CURRENT_VERSION_MINOR
localparam CPLD_IFC_CURRENT_VERSION_BUILD = 'h0; // CPLD_IFC_VERSION:CPLD_IFC_CURRENT_VERSION_BUILD
localparam CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // CPLD_IFC_VERSION:CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MINOR
localparam CPLD_IFC_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // CPLD_IFC_VERSION:CPLD_IFC_OLDEST_COMPATIBLE_VERSION_BUILD
localparam CPLD_IFC_CURRENT_VERSION_MAJOR = 'h2; // CPLD_IFC_VERSION:CPLD_IFC_CURRENT_VERSION_MAJOR
localparam CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h2; // CPLD_IFC_VERSION:CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam CPLD_IFC_VERSION_LAST_MODIFIED_TIME = 'h21011809; // CPLD_IFC_VERSION:CPLD_IFC_VERSION_LAST_MODIFIED_TIME
// Enumerated type DB_GPIO_IFC_VERSION
localparam DB_GPIO_IFC_VERSION_SIZE = 7;
localparam DB_GPIO_IFC_CURRENT_VERSION_MINOR = 'h0; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_CURRENT_VERSION_MINOR
localparam DB_GPIO_IFC_CURRENT_VERSION_BUILD = 'h0; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_CURRENT_VERSION_BUILD
localparam DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR
localparam DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD
localparam DB_GPIO_IFC_CURRENT_VERSION_MAJOR = 'h1; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_CURRENT_VERSION_MAJOR
localparam DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h1; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME = 'h22070116; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME
// Enumerated type FPGA_VERSION
localparam FPGA_VERSION_SIZE = 7;
localparam FPGA_CURRENT_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
localparam FPGA_CURRENT_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD
localparam FPGA_CURRENT_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h8; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h23042011; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
// Enumerated type RF_CORE_FULL_VERSION
localparam RF_CORE_FULL_VERSION_SIZE = 7;
localparam RF_CORE_FULL_CURRENT_VERSION_MINOR = 'h0; // RF_CORE_FULL_VERSION:RF_CORE_FULL_CURRENT_VERSION_MINOR
localparam RF_CORE_FULL_CURRENT_VERSION_BUILD = 'h0; // RF_CORE_FULL_VERSION:RF_CORE_FULL_CURRENT_VERSION_BUILD
localparam RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // RF_CORE_FULL_VERSION:RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MINOR
localparam RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // RF_CORE_FULL_VERSION:RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_BUILD
localparam RF_CORE_FULL_CURRENT_VERSION_MAJOR = 'h1; // RF_CORE_FULL_VERSION:RF_CORE_FULL_CURRENT_VERSION_MAJOR
localparam RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h1; // RF_CORE_FULL_VERSION:RF_CORE_FULL_OLDEST_COMPATIBLE_VERSION_MAJOR
localparam RF_CORE_FULL_VERSION_LAST_MODIFIED_TIME = 'h22062900; // RF_CORE_FULL_VERSION:RF_CORE_FULL_VERSION_LAST_MODIFIED_TIME
//===============================================================================
// Register Group VERSIONING_REGS
//===============================================================================
// Enumerated type COMPONENTS_INDEXES
localparam COMPONENTS_INDEXES_SIZE = 6;
localparam FPGA_VERSION_INDEX = 'h0; // COMPONENTS_INDEXES:FPGA_VERSION_INDEX
localparam CPLD_IFC_INDEX = 'h1; // COMPONENTS_INDEXES:CPLD_IFC_INDEX
localparam DB0_RF_CORE_INDEX = 'h2; // COMPONENTS_INDEXES:DB0_RF_CORE_INDEX
localparam DB1_RF_CORE_INDEX = 'h3; // COMPONENTS_INDEXES:DB1_RF_CORE_INDEX
localparam DB0_GPIO_IFC_INDEX = 'h4; // COMPONENTS_INDEXES:DB0_GPIO_IFC_INDEX
localparam DB1_GPIO_IFC_INDEX = 'h5; // COMPONENTS_INDEXES:DB1_GPIO_IFC_INDEX
// CURRENT_VERSION Register (from x4xx_versioning_regs.v)
localparam CURRENT_VERSION_COUNT = 64; // Number of elements in array
// OLDEST_COMPATIBLE_VERSION Register (from x4xx_versioning_regs.v)
localparam OLDEST_COMPATIBLE_VERSION_COUNT = 64; // Number of elements in array
// VERSION_LAST_MODIFIED Register (from x4xx_versioning_regs.v)
localparam VERSION_LAST_MODIFIED_COUNT = 64; // Number of elements in array
// RESERVED Register (from x4xx_versioning_regs.v)
localparam RESERVED_COUNT = 64; // Number of elements in array
// Return the offset of an element of register array CURRENT_VERSION
function integer CURRENT_VERSION (input integer i);
CURRENT_VERSION = (i * 'h10) + 'h0;
endfunction
// Return the offset of an element of register array OLDEST_COMPATIBLE_VERSION
function integer OLDEST_COMPATIBLE_VERSION (input integer i);
OLDEST_COMPATIBLE_VERSION = (i * 'h10) + 'h4;
endfunction
// Return the offset of an element of register array VERSION_LAST_MODIFIED
function integer VERSION_LAST_MODIFIED (input integer i);
VERSION_LAST_MODIFIED = (i * 'h10) + 'h8;
endfunction
// Return the offset of an element of register array RESERVED
function integer RESERVED (input integer i);
RESERVED = (i * 'h10) + 'hC;
endfunction
top/x400/regmap/x440/x440_rfdc_mapping.v
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//
// Copyright 2022 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: x440_rfdc_mapping
// Description:
// Auxiliary register map to provide a single source for RFDC mapping information
//XmlParse xml_on
//
//<regmap name="RFDC_MAPPING_REGMAP" readablestrobes="false" generatevhdl="true" generateverilog="true" ettusguidelines="true">
// <group name="CHANNEL_SWAPPING">
//
// <enumeratedtype name="RFDC_ADC_MAPPING" showhex="true">
// <value name="CH0_RX_MAPPING" integer="3"> Located in Tile 225, Channel 1 </value>
// <value name="CH1_RX_MAPPING" integer="1"> Located in Tile 224, Channel 1 </value>
// <value name="CH2_RX_MAPPING" integer="0"> Located in Tile 224, Channel 0 </value>
// <value name="CH3_RX_MAPPING" integer="2"> Located in Tile 225, Channel 0 </value>
// <value name="CH4_RX_MAPPING" integer="7"> Located in Tile 227, Channel 1 </value>
// <value name="CH5_RX_MAPPING" integer="5"> Located in Tile 226, Channel 1 </value>
// <value name="CH6_RX_MAPPING" integer="4"> Located in Tile 226, Channel 0 </value>
// <value name="CH7_RX_MAPPING" integer="6"> Located in Tile 227, Channel 0 </value>
// </enumeratedtype>
//
// <enumeratedtype name="RFDC_DAC_MAPPING" showhex="true">
// <value name="CH0_TX_MAPPING" integer="0"> Located in Tile 228, Channel 0 </value>
// <value name="CH1_TX_MAPPING" integer="2"> Located in Tile 228, Channel 2 </value>
// <value name="CH2_TX_MAPPING" integer="3"> Located in Tile 228, Channel 3 </value>
// <value name="CH3_TX_MAPPING" integer="1"> Located in Tile 228, Channel 1 </value>
// <value name="CH4_TX_MAPPING" integer="4"> Located in Tile 229, Channel 0 </value>
// <value name="CH5_TX_MAPPING" integer="6"> Located in Tile 229, Channel 2 </value>
// <value name="CH6_TX_MAPPING" integer="7"> Located in Tile 229, Channel 3 </value>
// <value name="CH7_TX_MAPPING" integer="5"> Located in Tile 229, Channel 1 </value>
// </enumeratedtype>
//
// </group>
//</regmap>
//XmlParse xml_off