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fpga: Add X440/FBX support

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Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>


Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
This commit is contained in:
Javier Valenzuela
2023-06-12 10:27:29 -05:00
committed by Aki Tomita
co-authored by Martin Braun Wade Fife Ryan Marlow
parent a405111ce7
commit 5cadf901c7
121 changed files with 20670 additions and 8739 deletions
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top/x400/ip/x4xx_ps_rfdc_bd/Makefile.inc
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_X4XX_PS_RFDC_ORIG_SRCS = $(addprefix $(IP_DIR)/x4xx_ps_rfdc_bd/, \
x4xx_ps_rfdc_bd.tcl \
)
IP_X4XX_PS_RFDC_HDL_SRCS = $(addprefix $(BASE_DIR)/x400/rf/common/, \
capture_sysref.v \
rf_nco_reset.vhd \
rf_reset_controller.vhd \
rf_reset.vhd \
clock_gates.vhd \
sync_wrapper.v \
axis_mux.vhd \
gpio_to_axis_mux.vhd \
) \
$(addprefix $(BASE_DIR)/../lib/control/, \
synchronizer.v \
synchronizer_impl.v \
) \
$(addprefix $(BASE_DIR)/x400/regmap/, PkgRFDC_REGS_REGMAP.vhd )
IP_X4XX_PS_RFDC_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/x4xx_ps_rfdc_bd/, \
x4xx_ps_rfdc_bd.tcl \
)
IP_X4XX_PS_RFDC_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/x4xx_ps_rfdc_bd/, \
x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd.bd \
)
BD_X4XX_PS_RFDC_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/x4xx_ps_rfdc_bd/, \
x4xx_ps_rfdc_bd.bd.out \
x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd_ooc.xdc \
x4xx_ps_rfdc_bd/synth/x4xx_ps_rfdc_bd.v \
)
EMPTY_IP_SRCS =
.INTERMEDIATE: IP_X4XX_PS_RFDC_BD_TRGT
$(IP_X4XX_PS_RFDC_BD_SRCS) $(BD_X4XX_PS_RFDC_BD_OUTS) $(IP_X4XX_PS_RFDC_BDTCL_SRCS): IP_X4XX_PS_RFDC_BD_TRGT
@:
IP_X4XX_PS_RFDC_BD_TRGT: $(IP_X4XX_PS_RFDC_ORIG_SRCS)
$(call BUILD_VIVADO_BDTCL,x4xx_ps_rfdc_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_X4XX_PS_RFDC_HDL_SRCS))
top/x400/ip/x4xx_ps_rfdc_bd/hdl_sources.tcl
-14
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@@ -1,14 +0,0 @@
set script_loc [file normalize [info script]]
set script_dir [file dirname $script_loc]
read_verilog -library work $script_dir/../../rf/common/capture_sysref.v
read_verilog -library work $script_dir/../../../../lib/control/synchronizer.v
read_verilog -library work $script_dir/../../../../lib/control/synchronizer_impl.v
read_verilog -library work $script_dir/../../rf/common/sync_wrapper.v
read_vhdl -library work $script_dir/../../rf/common/rf_nco_reset.vhd
read_vhdl -library work $script_dir/../../regmap/PkgRFDC_REGS_REGMAP.vhd
read_vhdl -library work $script_dir/../../rf/common/rf_reset_controller.vhd
read_vhdl -library work $script_dir/../../rf/common/rf_reset.vhd
read_vhdl -library work $script_dir/../../rf/common/clock_gates.vhd
read_vhdl -library work $script_dir/../../rf/common/axis_mux.vhd
read_vhdl -library work $script_dir/../../rf/common/gpio_to_axis_mux.vhd
top/x400/ip/x4xx_ps_rfdc_bd/regmap/common_regs.v
-550
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@@ -1,550 +0,0 @@
//
// Copyright 2021 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: common_regs
// Description:
// Registers definition within the x4xx_ps_rfdc_bd IP.
//XmlParse xml_on
//<top name="X4XX_FPGA">
// <ports>
// <info>
// This section lists all common Processing System ports through
// which the register maps in this project are accessed. Each input
// port to the fabric will point to a regmap.
// </info>
// <port name="ARM_M_AXI_HPM0" targetregmap="AXI_HPM0_REGMAP">
// <info>
// This is the main AXI4-Lite master interface that the PS
// exposes to the kernel to interact with the FPGA fabric.
// There are multiple endpoints connected to this interface.
// </info>
// </port>
// <port name="ARM_S_AXI_HPC0" sourcewindow="PL_DMA_MASTER_REGMAP|AXI_HPC0_WINDOW">
// <info>
// This is one of the two cache-coherent AXI slave ports available to
// communicate from the fabric (master) to the PS (slave).
// </info>
// </port>
// <port name="ARM_S_AXI_HPC1" sourcewindow="PL_DMA_MASTER_REGMAP|AXI_HPC1_WINDOW">
// <info>
// This is one of the two cache-coherent AXI slave ports available to
// communicate from the fabric (master) to the PS (slave).
// </info>
// </port>
// <port name="ARM_SPI1_CS3" targetregmap="MB_CPLD_PS_REGMAP">
// <info>
// This is the SPI1 interface
// (see <a href="https://www.xilinx.com/html_docs/registers/ug1087/mod___spi.html" target="_blank">Zynq UltraScale+ Devices Register Reference</a>)
// of the PS.
// With chip select 3 enabled transactions are targeted for the PS MB CPLD register interface linked here.{br}
// The request format on SPI is defined as.{br}
// {b}Write request:{/b}
// {ul}
// {li}1'b1 = write
// {li}15 bit address
// {li}32 bit data (MOSI)
// {li}8 bit processing gap
// {li}5 bit padding
// {li}1 bit ack
// {li}2 bit status
// {/ul}
// {b}Read request:{/b}
// {ul}
// {li}1'b0 = read
// {li}15 bit address
// {li}8 bit processing gap
// {li}32 bit data (MISO)
// {li}5 bit padding
// {li}1 bit ack
// {li}2 bit status
// {/ul}
// </info>
// </port>
// </ports>
// <regmapcfg readablestrobes="false">
// <map name="AXI_HPM0_REGMAP"/>
// <map name="MB_CPLD_PS_REGMAP"/>
// </regmapcfg>
//</top>
//
//<regmap name="AXI_HPM0_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
// <info>
// This is the map for the register space that the Processing System's
// M_AXI_HPM0_FPD port (AXI4 master interface) has access to.
// This port has a 40-bit address bus.
// </info>
// <group name="COMMON">
// <window name="RPU" offset="0x0080000000" size="0x00010000">
// <info>Space reserved for RPU access</info>
// </window>
// <window name="JTAG_ENGINE" offset="0x1000000000" size="0x1000">
// <info>Register space for the JTAG engine for MB CPLD programming.</info>
// </window>
// <window name="RESERVED" offset="0x100003F000" size="0x1000">
// <info>Register space reserved for future use.</info>
// </window>
// <window name="MPM_ENDPOINT" offset="0x1000080000" size="0x20000"
// targetregmap="PL_CPLD_REGMAP">
// <info>MPM endpoint fro MB/DB communication.</info>
// </window>
// <window name="CORE_REGS" offset="0x10000A0000" size="0x4000"
// targetregmap="CORE_REGS_REGMAP">
// <info>Register space reserved for mboard-regs (Core).</info>
// </window>
// <window name="INT_ETH_DMA" offset="0x10000A4000" size="0x6000"
// targetregmap="ETH_DMA_CTRL_REGMAP">
// <info>AXI DMA engine for internal Ethernet interface.</info>
// </window>
// <window name="INT_ETH_REGS" offset="0x10000AA000" size="0x2000">
// <info>Misc. registers for internal Ethernet.</info>
// </window>
// <window name="RFDC" offset="0x1000100000" size="0x40000">
// <info>Register space occupied by the Xilinx RFDC IP block.</info>
// </window>
// <window name="RFDC_REGS" offset="0x1000140000" size="0x20000"
// targetregmap="RFDC_REGS_REGMAP">
// <info>Register space for RFDC control/status registers.</info>
// </window>
// </group>
//</regmap>
//
//<regmap name="ETH_DMA_CTRL_REGMAP" readablestrobes="false" generatevhdl="true" generateverilog="false" ettusguidelines="true">
// <info>
// This is the map that the nixge driver uses in Ethernet DMA to
// move data between the Processing System's architecture and the fabric.
// This map is a combination of two main components: a Xilix AXI DMA engine
// and some registers for MAC/PHY control.
// </info>
// <group name="ETH_DMA_CTRL">
// <window name="AXI_DMA_CTRL" offset="0x0" size="0x4000">
// <info>
// Refer to Xilinx' AXI DMA v7.1 IP product guide for further
// information on this register map:
// https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf
// </info>
// </window>
// <window name="ETH_IO_CTRL" offset="0x4000" size="0x2000">
// <info>MAC/PHY control for the Ethernet interface.</info>
// </window>
// </group>
//</regmap>
//<regmap name="PL_DMA_MASTER_REGMAP" readablestrobes="false" generatevhdl="true" generateverilog="false" ettusguidelines="true">
// <info>
// This is a regmap to document the different ports that have access to the PS system memory.
// Each port may have different restrictions on system memory. See the corresponding window
// for details
// </info>
// <group name="HPC0_DMA">
// <window name="AXI_HPC0_WINDOW" offset="0x0" size="0x10000000000">
// <info>
// The HPC0 port of the PS is used for general purpose cache-coherent accesses
// to the PS system memory. Different applications may use it for different
// purposes. Its access is configured as follows: {br}
// {table border="1"}
// {tr}{th}Offset{/th} {th}Size{/th} {th}Description{/th}{tr}
// {tr}{td}0x000800000000{/td}{td}0x000800000000{/td}{td}DDR_HIGH{/td}{tr}
// {tr}{td}0x00000000{/td} {td}0x80000000{/td} {td}DDR_LOW{/td}{tr}
// {tr}{td}0xFF000000{/td} {td}0x01000000{/td} {td}LPS_OCM{/td}{tr}
// {tr}{td}0xC0000000{/td} {td}0x20000000{/td} {td}QSPI{/td}{tr}
// {/table}
// </info>
// </window>
// </group>
// <group name="HPC1_DMA">
// <window name="AXI_HPC1_WINDOW" offset="0x0" size="0x1000000000">
// <info>
// The HPC1 port of the PS is connected to the Ethernet DMA module. Three slave
// interfaces are lumped together in this window: scatter-gather, dma-rx, and dma-tx.
// Its access is configured as follows: {br}
// {table border="1"}
// {tr}{th}Offset{/th} {th}Size{/th} {th}Description{/th}{tr}
// {tr}{td}0x000800000000{/td}{td}0x000800000000{/td}{td}DDR_HIGH{/td}{tr}
// {tr}{td}0x00000000{/td} {td}0x80000000{/td} {td}DDR_LOW{/td}{tr}
// {tr}{td}0xC0000000{/td} {td}0x20000000{/td} {td}QSPI{/td}{tr}
// {/table}
// </info>
// </window>
// </group>
//</regmap>
//
//<regmap name="RFDC_REGS_REGMAP" readablestrobes="false" generatevhdl="true" generateverilog="true" ettusguidelines="true">
// <group name="RFDC_REGS">
// <info>
// These are the registers located within the RFDC block design
// that provide control and status support for the RF chain.
// </info>
//
// <window name="MMCM" offset="0x0" size="0x10000">
// <info>
// Register space for controlling the data clock MMCM instance
// within the RFDC block design.
// Refer to Xilinx' Clocking Wizard v6.0 Product Guide for the
// regiter space description in chapter 2.
// (https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf)
// </info>
// </window>
//
// <register name="INVERT_IQ_REG" offset="0x10000" size="32">
// <info>Control register for inverting I/Q data.</info>
// <!-- TODO: possibly redo these bitfields -->
// <bitfield name="INVERT_DB0_ADC0_IQ" range="0"/>
// <bitfield name="INVERT_DB0_ADC1_IQ" range="1"/>
// <bitfield name="INVERT_DB0_ADC2_IQ" range="2"/>
// <bitfield name="INVERT_DB0_ADC3_IQ" range="3"/>
// <bitfield name="INVERT_DB1_ADC0_IQ" range="4"/>
// <bitfield name="INVERT_DB1_ADC1_IQ" range="5"/>
// <bitfield name="INVERT_DB1_ADC2_IQ" range="6"/>
// <bitfield name="INVERT_DB1_ADC3_IQ" range="7"/>
// <bitfield name="INVERT_DB0_DAC0_IQ" range="8"/>
// <bitfield name="INVERT_DB0_DAC1_IQ" range="9"/>
// <bitfield name="INVERT_DB0_DAC2_IQ" range="10"/>
// <bitfield name="INVERT_DB0_DAC3_IQ" range="11"/>
// <bitfield name="INVERT_DB1_DAC0_IQ" range="12"/>
// <bitfield name="INVERT_DB1_DAC1_IQ" range="13"/>
// <bitfield name="INVERT_DB1_DAC2_IQ" range="14"/>
// <bitfield name="INVERT_DB1_DAC3_IQ" range="15"/>
// </register>
//
// <register name="MMCM_RESET_REG" offset="0x11000" size="32">
// <info>Control register for resetting the data clock MMCM.</info>
// <bitfield name="RESET_MMCM" range="0">
// <info>
// Write a '1' to this bit to reset the MMCM. Then write a
// '0' to place the MMCM out of reset.
// </info>
// </bitfield>
// </register>
//
// <register name="RF_RESET_CONTROL_REG" offset="0x12000" size="32">
// <info>
// Control register for the RF reset controller.
// Verify the FSM ID before polling starting any reset sequence.
// To use the SW reset triggers: Wait until DB*_DONE is de-asserted.
// Assert either the *_RESET or *_ENABLE bitfields.
// Wait until DB*_DONE is asserted to release the trigger.
// The DB*_DONE signal should then de-assert.{BR/}
// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is
// merely for documentation.{/b}
// </info>
// <bitfield name="FSM_RESET" range="0">
// <info>
// Write a '1' to this bit to reset the RF reset controller.
// Write a '0' once db0_fsm_reset_done asserts.
// </info>
// </bitfield>
// <bitfield name="ADC_RESET" range="4">
// <info>
// Write a '1' to this bit to trigger a reset for the
// daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done
// is asserted.
// </info>
// </bitfield>
// <bitfield name="ADC_ENABLE" range="5">
// <info>
// Write a '1' to this bit to trigger the enable sequence for
// the daughterboard 0 ADC chain. Write a '0' once
// db0_adc_seq_done is asserted.
// </info>
// </bitfield>
// <bitfield name="DAC_RESET" range="8">
// <info>
// Write a '1' to this bit to trigger a reset for the
// daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done
// is asserted.
// </info>
// </bitfield>
// <bitfield name="DAC_ENABLE" range="9">
// <info>
// Write a '1' to this bit to trigger the enable sequence for
// the daughterboard 0 DAC chain. Write a '0' once
// db0_dac_seq_done is asserted.
// </info>
// </bitfield>
// </register>
//
// <register name="RF_RESET_STATUS_REG" offset="0x12008" size="32" writable="false">
// <info>
// Status register for the RF reset controller.
// Verify the FSM ID before polling starting any reset sequence.
// Refer to RF_RESET_CONTROL_REG for instructions on how to use
// the status bits in this register.{BR/}
// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is
// merely for documentation.{/b}
// </info>
// <bitfield name="FSM_RESET_DONE" range="3">
// <info>
// This bit asserts ('1') when the DB0 RF reset controller FSM
// reset sequence is completed. The bitfield deasserts ('0')
// after deasserting db0_fsm_reset.
// </info>
// </bitfield>
// <bitfield name="ADC_SEQ_DONE" range="7">
// <info>
// This bit asserts ('1') when the DB0 ADC chain reset sequence
// is completed. The bitfield deasserts ('0') after
// deasserting the issued triggered (enable or reset).
// </info>
// </bitfield>
// <bitfield name="DAC_SEQ_DONE" range="11">
// <info>
// This bit asserts ('1') when the DB0 DAC chain reset sequence
// is completed. The bitfield deasserts ('0') after
// deasserting the issued triggered (enable or reset).
// </info>
// </bitfield>
// </register>
//
// <register name="RF_AXI_STATUS_REG" offset="0x13000" size="32" writable="false">
// <info>
// Status register for the RF AXI-Stream interfaces.{BR/}
// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is
// merely for documentation.{/b}
// </info>
// <bitfield name="RFDC_DAC_TREADY" range="1..0">
// <info>
// This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream
// TReady handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_DAC_TVALID" range="3..2">
// <info>
// This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream
// TValid handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_Q_TREADY" range="5..4">
// <info>
// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
// TReady handshake signals (Q portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_I_TREADY" range="7..6">
// <info>
// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
// TReady handshake signals (I portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_Q_TVALID" range="9..8">
// <info>
// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
// TValid handshake signals (Q portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_I_TVALID" range="11..10">
// <info>
// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
// TValid handshake signals (I portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="USER_ADC_TVALID" range="13..12">
// <info>
// This bitfield is wired to the user's ADC (DB0) AXI-Stream
// TValid handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="USER_ADC_TREADY" range="15..14">
// <info>
// This bitfield is wired to the user's ADC (DB0) AXI-Stream
// TReady handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_DAC_TREADY_DB1" range="17..16">
// <info>
// This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream
// TReady handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_DAC_TVALID_DB1" range="19..18">
// <info>
// This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream
// TValid handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_Q_TREADY_DB1" range="21..20">
// <info>
// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
// TReady handshake signals (Q portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_I_TREADY_DB1" range="23..22">
// <info>
// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
// TReady handshake signals (I portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_Q_TVALID_DB1" range="25..24">
// <info>
// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
// TValid handshake signals (Q portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="RFDC_ADC_I_TVALID_DB1" range="27..26">
// <info>
// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
// TValid handshake signals (I portion). The LSB is channel 0
// and the MSB is channel 1.
// </info>
// </bitfield>
// <bitfield name="USER_ADC_TVALID_DB1" range="29..28">
// <info>
// This bitfield is wired to the user's ADC (DB1) AXI-Stream
// TValid handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// <bitfield name="USER_ADC_TREADY_DB1" range="31..30">
// <info>
// This bitfield is wired to the user's ADC (DB1) AXI-Stream
// TReady handshake signals. The LSB is channel 0 and the MSB
// is channel 1.
// </info>
// </bitfield>
// </register>
//
// <register name="CALIBRATION_DATA" offset="0x014000">
// <info>
// The fields of this register provide data to all the DAC channels when enabled
// by the CALIBRATION_ENABLE register.
// </info>
// <bitfield name="Q_DATA" range="31..16">
// </bitfield>
// <bitfield name="I_DATA" range="15..00">
// </bitfield>
// </register>
//
// <register name="CALIBRATION_ENABLE" offset="0x014008">
// <info>
// This register enables calibration data in the DAC data path for each of the
// four channels. Each of these bits is normally '0'. When written '1', DAC data
// for the corresponding channel will be constantly driven with the contents of
// the CALIBRATION_DATA register.
// </info>
// <bitfield name="ENABLE_CALIBRATION_DATA_0" range="0">
// <info>
// Enables calibration data for channel 0.
// </info>
// </bitfield>
// <bitfield name="ENABLE_CALIBRATION_DATA_1" range="1">
// <info>
// Enables calibration data for channel 1.
// </info>
// </bitfield>
// <bitfield name="ENABLE_CALIBRATION_DATA_2" range="4">
// <info>
// Enables calibration data for channel 2.
// </info>
// </bitfield>
// <bitfield name="ENABLE_CALIBRATION_DATA_3" range="5">
// <info>
// Enables calibration data for channel 3.
// </info>
// </bitfield>
// </register>
//
// <register name="RF_PLL_CONTROL_REG" offset="0x16000" size="32" writable="true">
// <info>
// Enable RF MMCM outputs.
// </info>
// <bitfield name="ENABLE_DATA_CLK" range="0"/>
// <bitfield name="ENABLE_DATA_CLK_2X" range="4"/>
// <bitfield name="ENABLE_RF_CLK" range="8"/>
// <bitfield name="ENABLE_RF_CLK_2X" range="12"/>
// <bitfield name="CLEAR_DATA_CLK_UNLOCKED" range="16"/>
// </register>
//
// <register name="RF_PLL_STATUS_REG" offset="0x16008" size="32" writable="false">
// <info>
// Data Clk Pll Status Register
// </info>
// <bitfield name="DATA_CLK_PLL_UNLOCKED_STICKY" range="16"/>
// <bitfield name="DATA_CLK_PLL_LOCKED" range="20"/>
// </register>
//
// <register name="THRESHOLD_STATUS" offset="0x015000">
// <info>
// This register shows threshold status for the ADCs. Each bit reflects the
// RFDC's real-time ADC status signals, which will assert when the ADC input
// signal exceeds the programmed threshold value. The status will remain
// asserted until cleared by software.
// The bitfield names follow the pattern ADCX_ZZ_over_threshold(1|2), where X is
// the location of the tile in the converter column and ZZ is either 01 (the
// lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile).
// See also the Xilinx document PG269.
// </info>
// <bitfield name="ADC0_01_THRESHOLD1" range="0">
// </bitfield>
// <bitfield name="ADC0_01_THRESHOLD2" range="1">
// </bitfield>
// <bitfield name="ADC0_23_THRESHOLD1" range="2">
// </bitfield>
// <bitfield name="ADC0_23_THRESHOLD2" range="3">
// </bitfield>
// <bitfield name="ADC2_01_THRESHOLD1" range="8">
// </bitfield>
// <bitfield name="ADC2_01_THRESHOLD2" range="9">
// </bitfield>
// <bitfield name="ADC2_23_THRESHOLD1" range="10">
// </bitfield>
// <bitfield name="ADC2_23_THRESHOLD2" range="11">
// </bitfield>
// </register>
//
// <enumeratedtype name="FABRIC_DSP_BW_ENUM" showhex="true">
// <value name="FABRIC_DSP_BW_NONE" integer="0"/>
// <value name="FABRIC_DSP_BW_100M" integer="100"/>
// <value name="FABRIC_DSP_BW_200M" integer="200"/>
// <value name="FABRIC_DSP_BW_400M" integer="400"/>
// </enumeratedtype>
//
// <register name="FABRIC_DSP_REG" offset="0x13008" size="32" writable="false">
// <info>
// This register provides information to the driver on the type
// of DSP that is instantiated in the fabric.{BR/}
// The X410 platform supports multiple RF daughterboards, each requiring
// a different fabric RF DSP chain that works with specific RFDC settings.
// Each bandwidth DSP chain has a unique identifier (BW in MHz), this
// information is conveyed in this register to let the driver
// configure the RFDC with the proper settings.
// Also, channel count for the DSP module is included.{BR/}
// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is
// merely for documentation.{/b}
// </info>
// <bitfield name="FABRIC_DSP_BW" range="11..0" type="FABRIC_DSP_BW_ENUM" initialvalue="FABRIC_DSP_BW_NONE">
// <info>Fabric DSP BW in MHz for daughterboard 0.</info>
// </bitfield>
// <bitfield name="FABRIC_DSP_RX_CNT" range="13..12" initialvalue="0">
// <info>Fabric DSP RX channel count for daughterboard 0.</info>
// </bitfield>
// <bitfield name="FABRIC_DSP_TX_CNT" range="15..14" initialvalue="0">
// <info>Fabric DSP TX channel count for daughterboard 0.</info>
// </bitfield>
// <bitfield name="FABRIC_DSP_BW_DB1" range="27..16" type="FABRIC_DSP_BW_ENUM" initialvalue="FABRIC_DSP_BW_NONE">
// <info>Fabric DSP BW in MHz for daughterboard 1.</info>
// </bitfield>
// <bitfield name="FABRIC_DSP_RX_CNT_DB1" range="29..28" initialvalue="0">
// <info>Fabric DSP RX channel count for daughterboard 0.</info>
// </bitfield>
// <bitfield name="FABRIC_DSP_TX_CNT_DB1" range="31..30" initialvalue="0">
// <info>Fabric DSP TX channel count for daughterboard 0.</info>
// </bitfield>
// </register>
//
// </group>
//</regmap>
//XmlParse xml_off
top/x400/ip/x4xx_ps_rfdc_bd/regmap/uhd_regs.v
-336
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@@ -1,336 +0,0 @@
//
// Copyright 2021 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: uhd_regs
// Description:
// Registers definition within the x4xx_ps_rfdc_bd IP.
//XmlParse xml_on
//<regmap name="CMAC_REGMAP" markdown="true" generateverilog="false">
// <group name="XILINX_CMAC_REGISTERS">
// <info>
// 100G MAC ethernet registers (Link 0) defined in the CMAC Manual starting on pg 187.
//
// - http://www.xilinx.com/support/documentation/ip_documentation/cmac_usplus/v2_4/pg203-cmac-usplus.pdf
//
// </info>
// </group>
//</regmap>
//XmlParse xml_on
//<regmap name="XGE_MAC_REGMAP" markdown="true" generateverilog="false">
// <group name="OPENCORE_XGE_REGISTERS">
// <info>
//
// 10G MAC ethernet registers defined in the USRP OSS distribution fpga/usrp3/lib/xge/doc/xge_mac_spec.pdf
//
// </info>
// </group>
//</regmap>
//<regmap name="DMA_REGMAP" markdown="true" generateverilog="false">
// <group name="XILINX_DMA_REGISTERS">
// <info>
// Scatter Gather DMA block defined in Xilinx DMA manual start on pg 11
//
// - https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf
//
// </info>
// </group>
//</regmap>
//<regmap name="NIXGE_REGMAP" markdown="true" generateverilog="false">
// <group name="XGE_MAC_WINDOW">
// <window name="XGE_MAC" offset="0x1000" size="0x1000" targetregmap="XGE_MAC_REGMAP"/>
// </group>
// <group name="XGE_MAC_REGS">
// <info>
// nixge (maps to 10g mac if present)
// </info>
// <register name="PORT_INFO" offset="0x0000">
// <bitfield name="COMPAT_NUM" range="31..24">
// <info>
// Constant indicating version for this space.
// Not used by the NIXGE driver (12/4/2020)
// </info>
// </bitfield>
// <bitfield name="ACTIVITY" range="17">
// <info>
// Generically this mirrors the activity LED. Specific meaning varies based on the MGT_PROTOCOL.
// </info>
// </bitfield>
// <bitfield name="LINK_UP" range="16">
// <info>
// Generically means that a connection with a peer has been established. Specific
// meaning varies based on the MGT_PROTOCOL.
// </info>
// </bitfield>
// <bitfield name="MGT_PROTOCOL" range="15..8">
// <info>
// Constant indicating what flavor of communication this port is using
//
// - 0 = NONE
// - 1 = 1GbE
// - 2 = 10GbE
// - 3 = Aurora
// - 4 = WhiteRabbit
// - 5 = 100GbE
//
// </info>
// </bitfield>
// <bitfield name="PORTNUM" range="7..0">
// <info>
// Constant indicating which port this register is hooked to
//
// - 0 = QSFP0
// - 1 = QSFP1
//
// </info>
// </bitfield>
// </register>
// <register name="MAC_CTRL_STATUS" offset="0x0004">
// <info>
// Definition of this register depends on Protocol
//
// **10GBE**
//
// *READ - Status*
//
// - 0 = status_crc_error
// - 1 = status_fragment_error
// - 2 = status_txdfifo_ovflow
// - 3 = status_txdfifo_udflow
// - 4 = status_rxdfifo_ovflow
// - 5 = status_rxdfifo_udflow
// - 6 = status_pause_frame_rx
// - 7 = status_local_fault
// - 8 = status_remote_fault
//
// *WRITE - Ctl*
//
// - 0 = ctrl_tx_enable
//
// **100 GBE**
//
// *READ - Status*
//
// - 0 = tx_ovfout - Sets if TX overflow reported by CMAC
// (Stays set till MAC is reset). This is a fatal error
// - 1 = tx_unfout - Sets if TX underflow reported by CMAC
// (Stays set till MAC is reset). This is a fatal error
// - 2 = stat_rx_aligned - goes high when CMAC has finished
// alignment, and is ready to start reception of traffic.
// - 3 = mac_dropped_packet - If the mac RX wants to push data(TVALID)
// but upstream is trying to hold(TREADY)off we drop a packet.
// Upstream circuitry should detect this when traffic is forked
// between CHDR and CPU, so this bit will only set if there is a
// HW design error.
// - 4 = auto_config_done - This bit goes high when the auto_config
// state machine finishes operation. It is very similiar to
// stat_rx_alligned, but waits for extra writes which occur
// after allignement to complete.
// - 24:16 = pause_mask - readable version of pause_mask bellow.
//
// *WRITE - Ctl*
//
// - 0 = auto_enable - Defaults to ON after reset - Enables a
// state machine that performs CMAC register writes to
// bring up the MAC without SW intervention.
// - 24:16 = pause_mask - A second layer of enables(the first being
// register in the CMAC) on the pause_request mechanic. Bits
// 7:0 of enable pause on PFC7:0. Bit 8 enables global pause
// request (not priority controlled). The mask is used for TX
// and RX.
// </info>
// </register>
// <register name="MAC_PHY_STATUS" offset="0x0008">
// <info>
//
// Definition of this register depends on Protocol
//
// **10GBE**
//
// *READ - Status *
//
// - 0 = core_status 0 - link_up
// - 1 = core_status 1
// - 2 = core_status 2
// - 3 = core_status 3
// - 4 = core_status 4
// - 5 = core_status 5
// - 6 = core_status 6
// - 7 = core_status 7
//
// **100 GBE**
//
// *READ - Status*
//
// - 0 = usr_tx_reset - TX PLL's have locked - The clock for the 100G mac isn't stable till this bit sets.
// - 1 = usr_rx_reset - RX PLL's have locked
//
// </info>
// </register>
// <register name="MAC_LED_CTL" offset="0x000C">
// <bitfield name="identify_enable" range="0">
// <info>
// When set identify_value is used to control the activity LED.
// When clear the activity LED set on any TX or RX traffic to the mgt
// </info>
// </bitfield>
// <bitfield name="identify_value" range="1">
// <info>
// When identify_enable is set, this value controls the activity LED.
// </info>
// </bitfield>
// </register>
// <register name="ETH_MDIO_BASE" offset="0x0010">
// <info>
// The x4xx family of products does not use MDIO.
// </info>
// </register>
// <register name="AURORA_OVERRUNS" offset="0x0020">
// <info>
// Only valid if the protocol is Aurora.
// </info>
// </register>
// <register name="AURORA_CHECKSUM_ERRORS" offset="0x0024">
// <info>
// Only valid if the protocol is Aurora.
// </info>
// </register>
// <register name="AURORA_BIST_CHECKER_SAMPS" offset="0x0028">
// <info>
// Only valid if the protocol is Aurora.
// </info>
// </register>
// <register name="AURORA_BIST_CHECKER_ERRORS" offset="0x002C">
// <info>
// Only valid if the protocol is Aurora.
// </info>
// </register>
// </group>
//</regmap>
//
//<regmap name="UIO_REGMAP" markdown="true" generateverilog="false">
// <group name="UIO_REGS">
// <info>
// UIO
// </info>
// <register name="IP" offset="0x0000">
// <info>
// Set this port's IP address
// </info>
// </register>
// <register name="UDP" offset="0x0004">
// <info>
// Set the UDP port for CHDR_traffic
// </info>
// </register>
// <register name="BRIDGE_MAC_LSB" offset="0x0010">
// <info>
// If BRIDGE_ENABLE is set use this MAC_ID
// </info>
// </register>
// <register name="BRIDGE_MAC_MSB" offset="0x0014">
// <info>
// If BRIDGE_ENABLE is set use this MAC_ID
// </info>
// </register>
// <register name="BRIDGE_IP" offset="0x0018">
// <info>
// If BRIDGE_ENABLE is set use this IP Address
// </info>
// </register>
// <register name="BRIDGE_UDP" offset="0x001C">
// <info>
// If BRIDGE_ENABLE is set use this UDP Port for CHDR_traffic
// </info>
// </register>
// <register name="BRIDGE_ENABLE" offset="0x0020">
// <info>
// Bit 0 Controls the following logic
//
//```verilog
// always_comb begin : bridge_mux
// my_mac = bridge_en ? bridge_mac_reg : mac_reg;
// my_ip = bridge_en ? bridge_ip_reg : ip_reg;
// my_udp_chdr_port = bridge_en ? bridge_udp_port : udp_port;
// end
//```
//
// </info>
// </register>
// <register name="CHDR_DROPPED" offset="0x0030">
// <info>
// Count the number of Packets dropped that were addressed to the CHDR section.
// </info>
// </register>
// <register name="CPU_DROPPED" offset="0x0034">
// <info>
// Count the number of Packets dropped that were addressed to us, but not to the CHDR section.
// </info>
// </register>
// <register name="PAUSE" offset="0x0038">
// <bitfield name="pause_set" range="15..0">
// <info>
// If the fullness of the CHDR_FIFO in ETH_W words exceeds this value request an ethernet pause. This feature is only
// used with 100Gb ethernet
// </info>
// </bitfield>
// <bitfield name="pause_clear" range="31..16">
// <info>
// If the fullness of the CHDR_FIFO in ETH_W words falls bellow this value stop requesting an ethernet pause.
// *Pause clear must be less than pause set or terrible things will happen.*
// The clearing of the pause request causes the MAC to send a request to resume traffic. This feature is only
// used with 100Gb ethernet
// </info>
// </bitfield>
// </register>
// </group>
//</regmap>
//<regmap name="QSFP_REGMAP" markdown="true" generateverilog="false">
// <group name="QSFP_WINDOWS">
// <info>
// Register space for a single QSFP Communication port. This currently breaks into 2 possible configurations
//
// - 1X10GB Ethernet - Using OpenCore XGE MAC
// - 1x100GB Ethernet - Using Xilinx CMAC
// - (future possible) - Xilinx Aurora (various rates and lane widths)
// - (future possible) - 4X10GB Ethernet
//
// </info>
// <window name="ETH_DMA" offset="0x000" size="0x4000" targetregmap="DMA_REGMAP"/>
// <window name="NIXGE" offset="0x8000" size="0x2000" targetregmap="NIXGE_REGMAP"/>
// <window name="UIO" offset="0xA000" size="0x2000" targetregmap="UIO_REGMAP"/>
// <window name="CMAC" offset="0xC000" size="0x2000" targetregmap="CMAC_REGMAP"/>
// </group>
//</regmap>
//<regmap name="AXI_HPM0_REGMAP" markdown="true" generateverilog="false">
// <group name="UHD_ONLY">
// <info>
// - 0_0 indicates QSFP0 - Lane0 or a 4 LANE QSFP0
// - 0_1 indicates QSFP0 - Lane1
// - 0_2 indicates QSFP0 - Lane2
// - 0_3 indicates QSFP0 - Lane3
// - 1_0 indicates QSFP1 - Lane0 or a 4 LANE QSFP1
// - 1_1 indicates QSFP1 - Lane1
// - 1_2 indicates QSFP1 - Lane2
// - 1_3 indicates QSFP1 - Lane3
// </info>
// <window name="QSFP_0_0" offset="0x1200000000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_0_1" offset="0x1200010000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_0_2" offset="0x1200020000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_0_3" offset="0x1200030000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_1_0" offset="0x1200040000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_1_1" offset="0x1200050000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_1_2" offset="0x1200060000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// <window name="QSFP_1_3" offset="0x1200070000" size="0x10000" targetregmap="QSFP_REGMAP"/>
// </group>
//</regmap>
//XmlParse xml_off
top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/Makefile.inc
+56
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@@ -0,0 +1,56 @@
#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
include $(TOOLS_DIR)/make/viv_ip_builder.mak
IP_X4XX_PS_RFDC_ORIG_SRCS = $(addprefix $(IP_DIR)/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/, \
x440_ps_rfdc_bd.tcl \
)
IP_X4XX_PS_RFDC_HDL_SRCS = $(addprefix $(BASE_DIR)/x400/rf/common/, \
capture_sysref.v \
rf_nco_reset.vhd \
rf_reset.vhd \
sync_wrapper.v \
axis_mux.vhd \
gpio_to_axis_mux.vhd \
) \
$(addprefix $(BASE_DIR)/x400/rf/x440/, \
x440_clock_gates.vhd \
x440_rf_reset_controller.vhd \
x440_rfdc_tx_control_remap.v \
) \
$(addprefix $(BASE_DIR)/../lib/control/, \
synchronizer.v \
synchronizer_impl.v \
) \
$(addprefix $(BASE_DIR)/x400/regmap/x440/, \
PkgRFDC_REGS_REGMAP.vhd \
rfdc_mapping_regmap_utils.vh \
)
IP_X4XX_PS_RFDC_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/x440_ps_rfdc_bd/, \
x440_ps_rfdc_bd.tcl \
)
IP_X4XX_PS_RFDC_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/x440_ps_rfdc_bd/, \
x440_ps_rfdc_bd/x440_ps_rfdc_bd.bd \
)
BD_X4XX_PS_RFDC_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/x440_ps_rfdc_bd/, \
x440_ps_rfdc_bd.bd.out \
x440_ps_rfdc_bd/x440_ps_rfdc_bd_ooc.xdc \
x440_ps_rfdc_bd/synth/x440_ps_rfdc_bd.v \
)
EMPTY_IP_SRCS =
.INTERMEDIATE: IP_X4XX_PS_RFDC_BD_TRGT
$(IP_X4XX_PS_RFDC_BD_SRCS) $(BD_X4XX_PS_RFDC_BD_OUTS) $(IP_X4XX_PS_RFDC_BDTCL_SRCS): IP_X4XX_PS_RFDC_BD_TRGT
@:
IP_X4XX_PS_RFDC_BD_TRGT: $(IP_X4XX_PS_RFDC_ORIG_SRCS)
$(call BUILD_VIVADO_BDTCL,x440_ps_rfdc_bd,$(ARCH),$(PART_ID),$(IP_DIR)/x4xx_ps_rfdc_bd,$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_X4XX_PS_RFDC_HDL_SRCS))
top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/hdl_sources.tcl
+16
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@@ -0,0 +1,16 @@
set script_loc [file normalize [info script]]
set script_dir [file dirname $script_loc]
read_verilog -library work $script_dir/../../../rf/common/capture_sysref.v
read_verilog -library work $script_dir/../../../../../lib/control/synchronizer.v
read_verilog -library work $script_dir/../../../../../lib/control/synchronizer_impl.v
read_verilog -library work $script_dir/../../../rf/common/sync_wrapper.v
read_verilog -library work $script_dir/../../../regmap/x440/rfdc_mapping_regmap_utils.vh
read_verilog -library work $script_dir/../../../rf/x440/x440_rfdc_tx_control_remap.v
read_vhdl -library work $script_dir/../../../rf/common/rf_nco_reset.vhd
read_vhdl -library work $script_dir/../../../regmap/x440/PkgRFDC_REGS_REGMAP.vhd
read_vhdl -library work $script_dir/../../../rf/x440/x440_rf_reset_controller.vhd
read_vhdl -library work $script_dir/../../../rf/common/rf_reset.vhd
read_vhdl -library work $script_dir/../../../rf/x440/x440_clock_gates.vhd
read_vhdl -library work $script_dir/../../../rf/common/axis_mux.vhd
read_vhdl -library work $script_dir/../../../rf/common/gpio_to_axis_mux.vhd
top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/regmap/x440_rfdc_regs.v
+262
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@@ -0,0 +1,262 @@
//
// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: x440_rfdc_regs
// Description:
// Registers definition within the x4xx_ps_rfdc_bd IP.
//XmlParse xml_on
//<top name="X440_FPGA">
// <ports>
// <info>
// This section lists all common Processing System ports through
// which the register maps in this project are accessed. Each input
// port to the fabric will point to a regmap.
// </info>
// <port name="ARM_M_AXI_HPM0" targetregmap="AXI_HPM0_REGMAP">
// <info>
// This is the main AXI4-Lite master interface that the PS
// exposes to the kernel to interact with the FPGA fabric.
// There are multiple endpoints connected to this interface.
// </info>
// </port>
// <port name="ARM_S_AXI_HPC0" sourcewindow="PL_DMA_MASTER_REGMAP|AXI_HPC0_WINDOW">
// <info>
// This is one of the two cache-coherent AXI slave ports available to
// communicate from the fabric (master) to the PS (slave).
// </info>
// </port>
// <port name="ARM_S_AXI_HPC1" sourcewindow="PL_DMA_MASTER_REGMAP|AXI_HPC1_WINDOW">
// <info>
// This is one of the two cache-coherent AXI slave ports available to
// communicate from the fabric (master) to the PS (slave).
// </info>
// </port>
// <port name="ARM_SPI1_CS3" targetregmap="MB_CPLD_PS_REGMAP">
// <info>
// This is the SPI1 interface
// (see <a href="https://www.xilinx.com/html_docs/registers/ug1087/mod___spi.html" target="_blank">Zynq UltraScale+ Devices Register Reference</a>)
// of the PS.
// With chip select 3 enabled transactions are targeted for the PS MB CPLD register interface linked here.{br}
// The request format on SPI is defined as.{br}
// {b}Write request:{/b}
// {ul}
// {li}1'b1 = write
// {li}15 bit address
// {li}32 bit data (MOSI)
// {li}8 bit processing gap
// {li}5 bit padding
// {li}1 bit ack
// {li}2 bit status
// {/ul}
// {b}Read request:{/b}
// {ul}
// {li}1'b0 = read
// {li}15 bit address
// {li}8 bit processing gap
// {li}32 bit data (MISO)
// {li}5 bit padding
// {li}1 bit ack
// {li}2 bit status
// {/ul}
// </info>
// </port>
// </ports>
// <regmapcfg readablestrobes="false">
// <map name="AXI_HPM0_REGMAP"/>
// <map name="MB_CPLD_PS_REGMAP"/>
// </regmapcfg>
//</top>
//
//<regmap name="RFDC_REGS_REGMAP" readablestrobes="false" generatevhdl="true" generateverilog="true" ettusguidelines="true">
// <group name="RFDC_REGS">
// <info>
// These are the registers located within the RFDC block design
// that provide control and status support for the RF chain.
// </info>
//
// <window name="MMCM" offset="0x0" size="0x10000">
// <info>
// Register space for controlling the data clock MMCM instance
// within the RFDC block design.
// Refer to Xilinx' Clocking Wizard v6.0 Product Guide for the
// regiter space description in chapter 2.
// (https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf)
// </info>
// </window>
//
// <register name="INVERT_DB0_IQ_REG" offset="0x10000" size="32">
// <info>Control register for inverting I/Q data.</info>
// <bitfield name="INVERT_DB0_ADC0_IQ" range="0"/>
// <bitfield name="INVERT_DB0_ADC1_IQ" range="1"/>
// <bitfield name="INVERT_DB0_ADC2_IQ" range="2"/>
// <bitfield name="INVERT_DB0_ADC3_IQ" range="3"/>
// <bitfield name="INVERT_DB0_DAC0_IQ" range="8"/>
// <bitfield name="INVERT_DB0_DAC1_IQ" range="9"/>
// <bitfield name="INVERT_DB0_DAC2_IQ" range="10"/>
// <bitfield name="INVERT_DB0_DAC3_IQ" range="11"/>
// </register>
//
// <register name="INVERT_DB1_IQ_REG" offset="0x10800" size="32">
// <info>Control register for inverting I/Q data.</info>
// <bitfield name="INVERT_DB1_ADC0_IQ" range="0"/>
// <bitfield name="INVERT_DB1_ADC1_IQ" range="1"/>
// <bitfield name="INVERT_DB1_ADC2_IQ" range="2"/>
// <bitfield name="INVERT_DB1_ADC3_IQ" range="3"/>
// <bitfield name="INVERT_DB1_DAC0_IQ" range="8"/>
// <bitfield name="INVERT_DB1_DAC1_IQ" range="9"/>
// <bitfield name="INVERT_DB1_DAC2_IQ" range="10"/>
// <bitfield name="INVERT_DB1_DAC3_IQ" range="11"/>
// </register>
//
// <register name="MMCM_RESET_REG" offset="0x11000" size="32">
// <info>Control register for resetting the data clock MMCM.</info>
// <bitfield name="RESET_MMCM" range="0">
// <info>
// Write a '1' to this bit to reset the MMCM. Then write a
// '0' to place the MMCM out of reset.
// </info>
// </bitfield>
// </register>
//
// <register name="RF0_RESET_CONTROL_REG" offset="0x12000" typename="RF_RESET_CONTROL_REGTYPE"/>
// <register name="RF0_RESET_STATUS_REG" offset="0x12008" typename="RF_RESET_STATUS_REGTYPE"/>
// <register name="RF1_RESET_CONTROL_REG" offset="0x12800" typename="RF_RESET_CONTROL_REGTYPE"/>
// <register name="RF1_RESET_STATUS_REG" offset="0x12808" typename="RF_RESET_STATUS_REGTYPE"/>
//
// <register name="RF_AXI_STATUS_REG" offset="0x13000" typename="RF_AXI_STATUS_REGTYPE"/>
//
// <register name="CALIBRATION_DATA" offset="0x014000">
// <info>
// The fields of this register provide data to all the DAC channels when enabled
// by the CALIBRATION_ENABLE register.
// </info>
// <bitfield name="Q_DATA" range="31..16">
// </bitfield>
// <bitfield name="I_DATA" range="15..00">
// </bitfield>
// </register>
//
// <register name="CALIBRATION_ENABLE" offset="0x014008">
// <info>
// This register enables calibration data in the DAC data path for each of the
// four channels. Each of these bits is normally '0'. When written '1', DAC data
// for the corresponding channel will be constantly driven with the contents of
// the CALIBRATION_DATA register.
// </info>
// <bitfield name="ENABLE_CALIBRATION_DATA_0" range="0">
// <info>
// Enables calibration data for channel #0/0.
// </info>
// </bitfield>
// <bitfield name="ENABLE_CALIBRATION_DATA_1" range="1">
// <info>
// Enables calibration data for channel #0/1.
// </info>
// </bitfield>
// <bitfield name="ENABLE_CALIBRATION_DATA_2" range="2">
// <info>
// Enables calibration data for channel #0/2.
// </info>
// </bitfield>
// <bitfield name="ENABLE_CALIBRATION_DATA_3" range="3">
// <info>
// Enables calibration data for channel #0/3.
// </info>
// </bitfield>
// <bitfield name="ENABLE_CALIBRATION_DATA_4" range="4">
// <info>
// Enables calibration data for channel #1/0.
// </info>
// </bitfield>
// <bitfield name="ENABLE_CALIBRATION_DATA_5" range="5">
// <info>
// Enables calibration data for channel #1/1.
// </info>
// </bitfield>
// <bitfield name="ENABLE_CALIBRATION_DATA_6" range="6">
// <info>
// Enables calibration data for channel #1/2.
// </info>
// </bitfield>
// <bitfield name="ENABLE_CALIBRATION_DATA_7" range="7">
// <info>
// Enables calibration data for channel #1/3.
// </info>
// </bitfield>
// </register>
//
// <register name="RF_PLL_CONTROL_REG" offset="0x16000" size="32" writable="true">
// <info>
// Enable RF MMCM outputs.
// </info>
// <bitfield name="ENABLE_RF0_CLK" range="8"/>
// <bitfield name="ENABLE_RF0_CLK_2X" range="12"/>
// <bitfield name="CLEAR_DATA_CLK_UNLOCKED" range="16"/>
// <bitfield name="ENABLE_RF1_CLK" range="20"/>
// <bitfield name="ENABLE_RF1_CLK_2X" range="24"/>
// </register>
//
// <register name="RF_PLL_STATUS_REG" offset="0x16008" size="32" writable="false">
// <info>
// Data Clk Pll Status Register
// </info>
// <bitfield name="DATA_CLK_PLL_UNLOCKED_STICKY" range="16"/>
// <bitfield name="DATA_CLK_PLL_LOCKED" range="20"/>
// </register>
//
// <register name="THRESHOLD_STATUS" offset="0x015000">
// <info>
// This register shows threshold status for the ADCs. Each bit reflects the
// RFDC's real-time ADC status signals, which will assert when the ADC input
// signal exceeds the programmed threshold value. The status will remain
// asserted until cleared by software.
// The bitfield names follow the pattern ADCX_ZZ_over_threshold(1|2), where X is
// the location of the tile in the converter column and ZZ is either 01 (the
// lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile).
// See also the Xilinx document PG269.
// </info>
// <bitfield name="ADC0_01_THRESHOLD1" range="0">
// </bitfield>
// <bitfield name="ADC0_01_THRESHOLD2" range="1">
// </bitfield>
// <bitfield name="ADC0_23_THRESHOLD1" range="2">
// </bitfield>
// <bitfield name="ADC0_23_THRESHOLD2" range="3">
// </bitfield>
// <bitfield name="ADC1_01_THRESHOLD1" range="4">
// </bitfield>
// <bitfield name="ADC1_01_THRESHOLD2" range="5">
// </bitfield>
// <bitfield name="ADC1_23_THRESHOLD1" range="6">
// </bitfield>
// <bitfield name="ADC1_23_THRESHOLD2" range="7">
// </bitfield>
// <bitfield name="ADC2_01_THRESHOLD1" range="8">
// </bitfield>
// <bitfield name="ADC2_01_THRESHOLD2" range="9">
// </bitfield>
// <bitfield name="ADC2_23_THRESHOLD1" range="10">
// </bitfield>
// <bitfield name="ADC2_23_THRESHOLD2" range="11">
// </bitfield>
// <bitfield name="ADC3_01_THRESHOLD1" range="12">
// </bitfield>
// <bitfield name="ADC3_01_THRESHOLD2" range="13">
// </bitfield>
// <bitfield name="ADC3_23_THRESHOLD1" range="14">
// </bitfield>
// <bitfield name="ADC3_23_THRESHOLD2" range="15">
// </bitfield>
// </register>
//
// <register name="FABRIC_DSP_REG" offset="0x13008" typename="FABRIC_DSP_REGTYPE"/>
// <register name="ADC_TILEMAP_REG" offset="0x17000" typename="ADC_TILEMAP_REGTYPE"/>
// <register name="DAC_TILEMAP_REG" offset="0x17008" typename="DAC_TILEMAP_REGTYPE"/>
// <register name="RFDC_INFO_REG" offset="0x18000" typename="RFDC_INFO_REGTYPE"/>
//
// </group>
//</regmap>
//XmlParse xml_off
top/x400/ip/x4xx_ps_rfdc_bd/synthstub/x4xx_ps_rfdc_bd.vhd → top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/synthstub/x440_ps_rfdc_bd.vhd
+98 -32
View File
@@ -1,9 +1,9 @@
------------------------------------------------------------------------------------------
--
-- File: x4xx_ps_rfdc_bd.vhd
-- File: x440_ps_rfdc_bd.vhd
-- Author: niBlockDesign::niBdExportStub
-- Original Project: HwBuildTools
-- Date: 27 September 2021
-- Date: 06 September 2022
--
------------------------------------------------------------------------------------------
-- (c) Copyright National Instruments Corporation
@@ -12,7 +12,7 @@
------------------------------------------------------------------------------------------
--
-- Purpose: This is an automatically generated stub file to match the entity
-- declaration for 'x4xx_ps_rfdc_bd'. This file was created using niBdExportStub
-- declaration for 'x440_ps_rfdc_bd'. This file was created using niBdExportStub
-- Do not modify this file directly!
--
------------------------------------------------------------------------------------------
@@ -22,37 +22,44 @@ use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity x4xx_ps_rfdc_bd is
entity x440_ps_rfdc_bd is
port (
adc_data_out_resetn_dclk : out STD_LOGIC;
adc_enable_data_rclk : out STD_LOGIC;
adc_reset_pulse_dclk : in STD_LOGIC;
adc_rfdc_axi_resetn_rclk : out STD_LOGIC;
adc_enable_data_r0clk : out STD_LOGIC;
adc_enable_data_r1clk : out STD_LOGIC;
adc_reset_pulse_r0clk : in STD_LOGIC;
adc_reset_pulse_r1clk : in STD_LOGIC;
adc_resetn_r0clk2x : out STD_LOGIC;
adc_resetn_r1clk2x : out STD_LOGIC;
adc_rfdc_axi_resetn_r0clk : out STD_LOGIC;
adc_rfdc_axi_resetn_r1clk : out STD_LOGIC;
bus_clk : in STD_LOGIC;
bus_rstn : in STD_LOGIC;
clk40 : in STD_LOGIC;
clk40_rstn : in STD_LOGIC;
dac_data_in_resetn_dclk : out STD_LOGIC;
dac_data_in_resetn_dclk2x : out STD_LOGIC;
dac_data_in_resetn_rclk : out STD_LOGIC;
dac_data_in_resetn_rclk2x : out STD_LOGIC;
dac_reset_pulse_dclk : in STD_LOGIC;
data_clk : out STD_LOGIC;
data_clk_2x : out STD_LOGIC;
dac_data_in_resetn_r0clk : out STD_LOGIC;
dac_data_in_resetn_r0clk2x : out STD_LOGIC;
dac_data_in_resetn_r1clk : out STD_LOGIC;
dac_data_in_resetn_r1clk2x : out STD_LOGIC;
dac_reset_pulse_r0clk : in STD_LOGIC;
dac_reset_pulse_r1clk : in STD_LOGIC;
data_clock_locked : out STD_LOGIC;
enable_gated_clocks_clk40 : in STD_LOGIC;
enable_sysref_rclk : in STD_LOGIC;
fir_resetn_rclk2x : out STD_LOGIC;
enable_sysref_r0clk : in STD_LOGIC;
enable_sysref_r1clk : in STD_LOGIC;
gated_base_clks_valid_clk40 : out STD_LOGIC;
invert_adc_iq_rclk2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
invert_dac_iq_rclk2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
invert_adc_iq_r0clk2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
invert_adc_iq_r1clk2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
invert_dac_iq_r0clk2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
invert_dac_iq_r1clk2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
irq0_lpd_rpu_n : in STD_LOGIC;
irq1_lpd_rpu_n : in STD_LOGIC;
jtag0_tck : inout STD_LOGIC;
jtag0_tdi : inout STD_LOGIC;
jtag0_tdo : in STD_LOGIC;
jtag0_tms : inout STD_LOGIC;
nco_reset_done_dclk : out STD_LOGIC;
nco_reset_done_r0clk : out STD_LOGIC;
nco_reset_done_r1clk : out STD_LOGIC;
pl_clk40 : out STD_LOGIC;
pl_clk100 : out STD_LOGIC;
pl_clk166 : out STD_LOGIC;
@@ -65,15 +72,18 @@ port (
pl_resetn3 : out STD_LOGIC;
pll_ref_clk_in : in STD_LOGIC;
pll_ref_clk_out : out STD_LOGIC;
radio0_rfdc_clk : out STD_LOGIC_VECTOR ( 0 to 0 );
radio0_rfdc_clk_2x : out STD_LOGIC_VECTOR ( 0 to 0 );
radio1_rfdc_clk : out STD_LOGIC_VECTOR ( 0 to 0 );
radio1_rfdc_clk_2x : out STD_LOGIC_VECTOR ( 0 to 0 );
rf_axi_status_clk40 : in STD_LOGIC_VECTOR ( 31 downto 0 );
rf_dsp_info_clk40 : in STD_LOGIC_VECTOR ( 31 downto 0 );
rfdc_clk : out STD_LOGIC_VECTOR ( 0 to 0 );
rfdc_clk_2x : out STD_LOGIC_VECTOR ( 0 to 0 );
rfdc_irq : out STD_LOGIC;
s_axi_hp0_aclk : in STD_LOGIC;
s_axi_hp1_aclk : in STD_LOGIC;
s_axi_hpc0_aclk : in STD_LOGIC;
start_nco_reset_dclk : in STD_LOGIC;
start_nco_reset_r0clk : in STD_LOGIC;
start_nco_reset_r1clk : in STD_LOGIC;
sysref_out_pclk : out STD_LOGIC;
sysref_out_rclk : out STD_LOGIC;
sysref_pl_in : in STD_LOGIC;
@@ -201,8 +211,20 @@ port (
s_axi_hpc0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
adc0_clk_clk_n : in STD_LOGIC;
adc0_clk_clk_p : in STD_LOGIC;
adc1_clk_clk_n : in STD_LOGIC;
adc1_clk_clk_p : in STD_LOGIC;
adc2_clk_clk_n : in STD_LOGIC;
adc2_clk_clk_p : in STD_LOGIC;
adc3_clk_clk_n : in STD_LOGIC;
adc3_clk_clk_p : in STD_LOGIC;
adc_tile225_ch0_vin_v_n : in STD_LOGIC;
adc_tile225_ch0_vin_v_p : in STD_LOGIC;
adc_tile225_ch1_vin_v_n : in STD_LOGIC;
adc_tile225_ch1_vin_v_p : in STD_LOGIC;
adc_tile227_ch0_vin_v_n : in STD_LOGIC;
adc_tile227_ch0_vin_v_p : in STD_LOGIC;
adc_tile227_ch1_vin_v_n : in STD_LOGIC;
adc_tile227_ch1_vin_v_p : in STD_LOGIC;
m_axi_app_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axi_app_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_app_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
@@ -226,6 +248,18 @@ port (
dac0_clk_clk_p : in STD_LOGIC;
dac1_clk_clk_n : in STD_LOGIC;
dac1_clk_clk_p : in STD_LOGIC;
dac_tile228_ch2_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
dac_tile228_ch2_din_tvalid : in STD_LOGIC;
dac_tile228_ch2_din_tready : out STD_LOGIC;
dac_tile228_ch3_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
dac_tile228_ch3_din_tvalid : in STD_LOGIC;
dac_tile228_ch3_din_tready : out STD_LOGIC;
dac_tile229_ch2_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
dac_tile229_ch2_din_tvalid : in STD_LOGIC;
dac_tile229_ch2_din_tready : out STD_LOGIC;
dac_tile229_ch3_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
dac_tile229_ch3_din_tvalid : in STD_LOGIC;
dac_tile229_ch3_din_tready : out STD_LOGIC;
gpio_0_tri_i : in STD_LOGIC_VECTOR ( 63 downto 0 );
gpio_0_tri_o : out STD_LOGIC_VECTOR ( 63 downto 0 );
gpio_0_tri_t : out STD_LOGIC_VECTOR ( 63 downto 0 );
@@ -310,6 +344,14 @@ port (
m_axi_mpm_ep_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mpm_ep_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_mpm_ep_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
dac_tile228_ch0_vout_v_n : out STD_LOGIC;
dac_tile228_ch0_vout_v_p : out STD_LOGIC;
dac_tile228_ch1_vout_v_n : out STD_LOGIC;
dac_tile228_ch1_vout_v_p : out STD_LOGIC;
dac_tile229_ch0_vout_v_n : out STD_LOGIC;
dac_tile229_ch0_vout_v_p : out STD_LOGIC;
dac_tile229_ch1_vout_v_n : out STD_LOGIC;
dac_tile229_ch1_vout_v_p : out STD_LOGIC;
adc_tile224_ch0_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile224_ch0_dout_i_tready : in STD_LOGIC;
adc_tile224_ch0_dout_i_tvalid : out STD_LOGIC;
@@ -322,6 +364,18 @@ port (
adc_tile224_ch1_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile224_ch1_dout_q_tready : in STD_LOGIC;
adc_tile224_ch1_dout_q_tvalid : out STD_LOGIC;
adc_tile225_ch0_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile225_ch0_dout_i_tready : in STD_LOGIC;
adc_tile225_ch0_dout_i_tvalid : out STD_LOGIC;
adc_tile225_ch0_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile225_ch0_dout_q_tready : in STD_LOGIC;
adc_tile225_ch0_dout_q_tvalid : out STD_LOGIC;
adc_tile225_ch1_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile225_ch1_dout_i_tready : in STD_LOGIC;
adc_tile225_ch1_dout_i_tvalid : out STD_LOGIC;
adc_tile225_ch1_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile225_ch1_dout_q_tready : in STD_LOGIC;
adc_tile225_ch1_dout_q_tvalid : out STD_LOGIC;
adc_tile226_ch0_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile226_ch0_dout_i_tready : in STD_LOGIC;
adc_tile226_ch0_dout_i_tvalid : out STD_LOGIC;
@@ -334,14 +388,26 @@ port (
adc_tile226_ch1_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile226_ch1_dout_q_tready : in STD_LOGIC;
adc_tile226_ch1_dout_q_tvalid : out STD_LOGIC;
dac_tile228_ch0_vout_v_n : out STD_LOGIC;
dac_tile228_ch0_vout_v_p : out STD_LOGIC;
dac_tile228_ch1_vout_v_n : out STD_LOGIC;
dac_tile228_ch1_vout_v_p : out STD_LOGIC;
dac_tile229_ch0_vout_v_n : out STD_LOGIC;
dac_tile229_ch0_vout_v_p : out STD_LOGIC;
dac_tile229_ch1_vout_v_n : out STD_LOGIC;
dac_tile229_ch1_vout_v_p : out STD_LOGIC;
adc_tile227_ch0_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile227_ch0_dout_i_tready : in STD_LOGIC;
adc_tile227_ch0_dout_i_tvalid : out STD_LOGIC;
adc_tile227_ch0_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile227_ch0_dout_q_tready : in STD_LOGIC;
adc_tile227_ch0_dout_q_tvalid : out STD_LOGIC;
adc_tile227_ch1_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile227_ch1_dout_i_tready : in STD_LOGIC;
adc_tile227_ch1_dout_i_tvalid : out STD_LOGIC;
adc_tile227_ch1_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
adc_tile227_ch1_dout_q_tready : in STD_LOGIC;
adc_tile227_ch1_dout_q_tvalid : out STD_LOGIC;
dac_tile228_ch2_vout_v_n : out STD_LOGIC;
dac_tile228_ch2_vout_v_p : out STD_LOGIC;
dac_tile228_ch3_vout_v_n : out STD_LOGIC;
dac_tile228_ch3_vout_v_p : out STD_LOGIC;
dac_tile229_ch2_vout_v_n : out STD_LOGIC;
dac_tile229_ch2_vout_v_p : out STD_LOGIC;
dac_tile229_ch3_vout_v_n : out STD_LOGIC;
dac_tile229_ch3_vout_v_p : out STD_LOGIC;
dac_tile228_ch0_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
dac_tile228_ch0_din_tvalid : in STD_LOGIC;
dac_tile228_ch0_din_tready : out STD_LOGIC;
@@ -404,8 +470,8 @@ port (
s_axi_hpc1_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_hpc1_awuser : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end entity x4xx_ps_rfdc_bd;
end entity x440_ps_rfdc_bd;
architecture stub of x4xx_ps_rfdc_bd is
architecture stub of x440_ps_rfdc_bd is
begin
end architecture stub;
top/x400/ip/x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd.tcl → top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/x440_ps_rfdc_bd.tcl
+746 -257
View File
File diff suppressed because it is too large Load Diff