miegl/b210-k7-fpga
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fpga: Add X440/FBX support

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Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>


Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
This commit is contained in:
Javier Valenzuela
2023-06-12 10:27:29 -05:00
committed by Aki Tomita
co-authored by Martin Braun Wade Fife Ryan Marlow
parent a405111ce7
commit 5cadf901c7
121 changed files with 20670 additions and 8739 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/x400/ip/Makefile.inc
+35
View File
@@ -33,6 +33,14 @@ include $(IP_DIR)/dac_400m_bd/Makefile.inc
include $(IP_DIR)/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/Makefile.inc
endif
ifdef X440
include $(IP_DIR)/adc_full_bd/Makefile.inc
include $(IP_DIR)/adc_100m_bd/Makefile.inc
include $(IP_DIR)/dac_100m_bd/Makefile.inc
include $(IP_DIR)/ddr4_64bits_x440/Makefile.inc
include $(IP_DIR)/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/Makefile.inc
endif
BD_SRCS = \
$(IP_X4XX_PS_RFDC_BD_SRCS) \
$(IP_X4XX_PS_RFDC_HDL_SRCS) \
@@ -66,6 +74,16 @@ $(IP_DAC_400M_BD_SRCS) \
$(IP_DAC_400M_HDL_SRCS)
endif
ifdef X440
BD_SRCS += \
$(IP_ADC_FULL_BD_SRCS) \
$(IP_ADC_FULL_HDL_SRCS) \
$(IP_ADC_100M_BD_SRCS) \
$(IP_ADC_100M_HDL_SRCS) \
$(IP_DAC_100M_BD_SRCS) \
$(IP_DAC_100M_HDL_SRCS)
endif
IP_XCI_SRCS = \
$(IP_XGE_PCS_PMA_SRCS) \
$(IP_AXI64_4K_2CLK_FIFO_SRCS) \
@@ -79,6 +97,11 @@ IP_XCI_SRCS += \
$(IP_DDR4_64BITS_SRCS)
endif
ifdef X440
IP_XCI_SRCS += \
$(IP_DDR4_64BITS_X440_SRCS)
endif
BD_OUTPUTS = \
$(BD_X4XX_PS_RFDC_BD_OUTS) \
$(BD_AXI_INTERCONNECT_APP_BD_OUTS) \
@@ -103,6 +126,13 @@ $(BD_DAC_100M_BD_OUTS) \
$(BD_DAC_400M_BD_OUTS)
endif
ifdef X440
BD_OUTPUTS += \
$(BD_ADC_FULL_BD_OUTS) \
$(BD_ADC_100M_BD_OUTS) \
$(BD_DAC_100M_BD_OUTS)
endif
IP_SYNTH_OUTPUTS = \
$(IP_XGE_PCS_PMA_OUTS) \
$(IP_AXI64_4K_2CLK_FIFO_OUTS) \
@@ -116,6 +146,11 @@ IP_SYNTH_OUTPUTS += \
$(IP_DDR4_64BITS_OUTS)
endif
ifdef X440
IP_SYNTH_OUTPUTS += \
$(IP_DDR4_64BITS_X440_OUTS)
endif
IP_HDL_SIM_SRCS = \
$(IP_AXI64_4K_2CLK_FIFO_HDL_SIM_SRCS) \
$(IP_FIFO_4K_2CLK_HDL_SIM_SRCS) \