fpga: Add X440/FBX support
Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
This commit is contained in:
Javier Valenzuela
committed by
Aki Tomita
Aki Tomita
co-authored by
Martin Braun
Wade Fife
Ryan Marlow
Martin Braun
Wade Fife
Ryan Marlow
parent
a405111ce7
commit
5cadf901c7
@@ -33,6 +33,14 @@ include $(IP_DIR)/dac_400m_bd/Makefile.inc
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include $(IP_DIR)/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/Makefile.inc
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endif
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ifdef X440
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include $(IP_DIR)/adc_full_bd/Makefile.inc
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include $(IP_DIR)/adc_100m_bd/Makefile.inc
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include $(IP_DIR)/dac_100m_bd/Makefile.inc
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include $(IP_DIR)/ddr4_64bits_x440/Makefile.inc
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include $(IP_DIR)/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/Makefile.inc
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endif
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BD_SRCS = \
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$(IP_X4XX_PS_RFDC_BD_SRCS) \
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$(IP_X4XX_PS_RFDC_HDL_SRCS) \
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@@ -66,6 +74,16 @@ $(IP_DAC_400M_BD_SRCS) \
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$(IP_DAC_400M_HDL_SRCS)
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endif
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ifdef X440
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BD_SRCS += \
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$(IP_ADC_FULL_BD_SRCS) \
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$(IP_ADC_FULL_HDL_SRCS) \
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$(IP_ADC_100M_BD_SRCS) \
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$(IP_ADC_100M_HDL_SRCS) \
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$(IP_DAC_100M_BD_SRCS) \
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$(IP_DAC_100M_HDL_SRCS)
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endif
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IP_XCI_SRCS = \
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$(IP_XGE_PCS_PMA_SRCS) \
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$(IP_AXI64_4K_2CLK_FIFO_SRCS) \
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@@ -79,6 +97,11 @@ IP_XCI_SRCS += \
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$(IP_DDR4_64BITS_SRCS)
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endif
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ifdef X440
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IP_XCI_SRCS += \
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$(IP_DDR4_64BITS_X440_SRCS)
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endif
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BD_OUTPUTS = \
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$(BD_X4XX_PS_RFDC_BD_OUTS) \
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$(BD_AXI_INTERCONNECT_APP_BD_OUTS) \
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@@ -103,6 +126,13 @@ $(BD_DAC_100M_BD_OUTS) \
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$(BD_DAC_400M_BD_OUTS)
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endif
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ifdef X440
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BD_OUTPUTS += \
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$(BD_ADC_FULL_BD_OUTS) \
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$(BD_ADC_100M_BD_OUTS) \
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$(BD_DAC_100M_BD_OUTS)
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endif
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IP_SYNTH_OUTPUTS = \
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$(IP_XGE_PCS_PMA_OUTS) \
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$(IP_AXI64_4K_2CLK_FIFO_OUTS) \
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@@ -116,6 +146,11 @@ IP_SYNTH_OUTPUTS += \
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$(IP_DDR4_64BITS_OUTS)
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endif
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ifdef X440
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IP_SYNTH_OUTPUTS += \
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$(IP_DDR4_64BITS_X440_OUTS)
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endif
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IP_HDL_SIM_SRCS = \
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$(IP_AXI64_4K_2CLK_FIFO_HDL_SIM_SRCS) \
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$(IP_FIFO_4K_2CLK_HDL_SIM_SRCS) \
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@@ -0,0 +1,38 @@
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#
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# Copyright 2022 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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include $(TOOLS_DIR)/make/viv_ip_builder.mak
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IP_ADC_FULL_ORIG_SRCS = $(addprefix $(IP_DIR)/adc_full_bd/, \
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adc_full_bd.tcl \
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)
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IP_ADC_FULL_HDL_SRCS = $(addprefix $(BASE_DIR)/x400/rf/, \
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common/adc_iq_repacker.v \
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)
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IP_ADC_FULL_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/adc_full_bd/, \
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adc_full_bd.tcl \
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)
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IP_ADC_FULL_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/adc_full_bd/, \
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adc_full_bd/adc_full_bd.bd \
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)
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BD_ADC_FULL_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/adc_full_bd/, \
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adc_full_bd.bd.out \
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adc_full_bd/adc_full_bd_ooc.xdc \
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adc_full_bd/synth/adc_full_bd.v \
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)
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EMPTY_IP_SRCS =
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.INTERMEDIATE: IP_ADC_FULL_BD_TRGT
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$(IP_ADC_FULL_BD_SRCS) $(BD_ADC_FULL_BD_OUTS) $(IP_ADC_FULL_BDTCL_SRCS): IP_ADC_FULL_BD_TRGT
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@:
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IP_ADC_FULL_BD_TRGT: $(IP_ADC_FULL_ORIG_SRCS) $(IP_ADC_FULL_HDL_SRCS)
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$(call BUILD_VIVADO_BDTCL,adc_full_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(EMPTY_IP_SRCS),$(IP_ADC_FULL_HDL_SRCS),)
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@@ -0,0 +1,338 @@
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################################################################
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# This is a generated script based on design: adc_full_bd
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#
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# Though there are limitations about the generated script,
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# the main purpose of this utility is to make learning
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# IP Integrator Tcl commands easier.
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################################################################
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namespace eval _tcl {
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proc get_script_folder {} {
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set script_path [file normalize [info script]]
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set script_folder [file dirname $script_path]
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return $script_folder
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}
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}
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variable script_folder
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set script_folder [_tcl::get_script_folder]
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################################################################
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# Check if script is running in correct Vivado version.
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################################################################
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set scripts_vivado_version 2021.1
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set current_vivado_version [version -short]
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if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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puts ""
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catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
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return 1
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}
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################################################################
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# START
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################################################################
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# To test this script, run the following commands from Vivado Tcl console:
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# source adc_full_bd_script.tcl
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# The design that will be created by this Tcl script contains the following
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# module references:
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# adc_iq_repacker
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# Please add the sources of those modules before sourcing this Tcl script.
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# If there is no project opened, this script will create a
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# project, but make sure you do not have an existing project
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# <./myproj/project_1.xpr> in the current working folder.
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set list_projs [get_projects -quiet]
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if { $list_projs eq "" } {
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create_project project_1 myproj -part xczu28dr-ffvg1517-2-e
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}
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# CHANGE DESIGN NAME HERE
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variable design_name
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set design_name adc_full_bd
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# If you do not already have an existing IP Integrator design open,
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# you can create a design using the following command:
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# create_bd_design $design_name
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# Creating design if needed
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set errMsg ""
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set nRet 0
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set cur_design [current_bd_design -quiet]
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set list_cells [get_bd_cells -quiet]
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if { ${design_name} eq "" } {
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# USE CASES:
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# 1) Design_name not set
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set errMsg "Please set the variable <design_name> to a non-empty value."
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set nRet 1
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} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
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# USE CASES:
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# 2): Current design opened AND is empty AND names same.
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# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
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# 4): Current design opened AND is empty AND names diff; design_name exists in project.
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if { $cur_design ne $design_name } {
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common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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set design_name [get_property NAME $cur_design]
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}
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common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
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} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
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# USE CASES:
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# 5) Current design opened AND has components AND same names.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 1
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} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
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# USE CASES:
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# 6) Current opened design, has components, but diff names, design_name exists in project.
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# 7) No opened design, design_name exists in project.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 2
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} else {
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# USE CASES:
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# 8) No opened design, design_name not in project.
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# 9) Current opened design, has components, but diff names, design_name not in project.
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common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
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create_bd_design $design_name
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common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
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current_bd_design $design_name
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}
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# Add USER_COMMENTS on $design_name
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set_property USER_COMMENTS.comment_0 "Scale_2x is a simple shift to left by 2 logic and does not need any pipeline stage" [get_bd_designs $design_name]
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common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
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if { $nRet != 0 } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
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return $nRet
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}
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set bCheckIPsPassed 1
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##################################################################
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# CHECK IPs
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##################################################################
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set bCheckIPs 1
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if { $bCheckIPs == 1 } {
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set list_check_ips "\
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xilinx.com:ip:axis_register_slice:1.1\
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xilinx.com:ip:xlconstant:1.1\
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"
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set list_ips_missing ""
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common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
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foreach ip_vlnv $list_check_ips {
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set ip_obj [get_ipdefs -all $ip_vlnv]
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if { $ip_obj eq "" } {
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lappend list_ips_missing $ip_vlnv
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}
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}
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if { $list_ips_missing ne "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
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set bCheckIPsPassed 0
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}
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}
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##################################################################
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# CHECK Modules
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##################################################################
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set bCheckModules 1
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if { $bCheckModules == 1 } {
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set list_check_mods "\
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adc_iq_repacker\
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"
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set list_mods_missing ""
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common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
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foreach mod_vlnv $list_check_mods {
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if { [can_resolve_reference $mod_vlnv] == 0 } {
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lappend list_mods_missing $mod_vlnv
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}
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}
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if { $list_mods_missing ne "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
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common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
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set bCheckIPsPassed 0
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}
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}
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if { $bCheckIPsPassed != 1 } {
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common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
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return 3
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}
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##################################################################
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# DESIGN PROCs
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##################################################################
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# Procedure to create entire design; Provide argument to make
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# procedure reusable. If parentCell is "", will use root.
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proc create_root_design { parentCell } {
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variable script_folder
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variable design_name
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if { $parentCell eq "" } {
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set parentCell [get_bd_cells /]
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}
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# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
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return
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}
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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return
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}
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# Save current instance; Restore later
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set oldCurInst [current_bd_instance .]
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# Set parent object as current
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current_bd_instance $parentObj
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# Create interface ports
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set adc_data_out [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_data_out ]
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set_property -dict [ list \
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CONFIG.FREQ_HZ {512000000} \
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] $adc_data_out
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set adc_i_data_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 adc_i_data_in ]
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set_property -dict [ list \
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CONFIG.FREQ_HZ {512000000} \
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CONFIG.HAS_TKEEP {0} \
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CONFIG.HAS_TLAST {0} \
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CONFIG.HAS_TREADY {1} \
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CONFIG.HAS_TSTRB {0} \
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CONFIG.LAYERED_METADATA {undef} \
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CONFIG.TDATA_NUM_BYTES {16} \
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CONFIG.TDEST_WIDTH {0} \
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CONFIG.TID_WIDTH {0} \
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CONFIG.TUSER_WIDTH {0} \
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] $adc_i_data_in
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set adc_q_data_in [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 adc_q_data_in ]
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set_property -dict [ list \
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CONFIG.FREQ_HZ {512000000} \
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CONFIG.HAS_TKEEP {0} \
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CONFIG.HAS_TLAST {0} \
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CONFIG.HAS_TREADY {1} \
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CONFIG.HAS_TSTRB {0} \
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CONFIG.LAYERED_METADATA {undef} \
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CONFIG.TDATA_NUM_BYTES {16} \
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CONFIG.TDEST_WIDTH {0} \
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CONFIG.TID_WIDTH {0} \
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CONFIG.TUSER_WIDTH {0} \
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] $adc_q_data_in
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# Create ports
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set enable_data_to_repacker_rclk [ create_bd_port -dir I enable_data_to_repacker_rclk ]
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set rfdc_adc_axi_resetn_rclk [ create_bd_port -dir I -type rst rfdc_adc_axi_resetn_rclk ]
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set rfdc_clk [ create_bd_port -dir I -type clk -freq_hz 512000000 rfdc_clk ]
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set swap_iq_rclk [ create_bd_port -dir I swap_iq_rclk ]
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# Create instance: adc_data_to_axi, and set properties
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set adc_data_to_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_data_to_axi ]
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set_property -dict [ list \
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CONFIG.REG_CONFIG {1} \
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CONFIG.TDATA_NUM_BYTES {32} \
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] $adc_data_to_axi
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# Create instance: adc_i_data_from_axi, and set properties
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set adc_i_data_from_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_i_data_from_axi ]
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set_property -dict [ list \
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CONFIG.REG_CONFIG {0} \
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CONFIG.TDATA_NUM_BYTES {16} \
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] $adc_i_data_from_axi
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# Create instance: adc_iq_repacker, and set properties
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set block_name adc_iq_repacker
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set block_cell_name adc_iq_repacker
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if { [catch {set adc_iq_repacker [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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return 1
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} elseif { $adc_iq_repacker eq "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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return 1
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}
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set_property -dict [ list \
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CONFIG.SPC {8} \
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] $adc_iq_repacker
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# Create instance: adc_q_data_from_axi, and set properties
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set adc_q_data_from_axi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 adc_q_data_from_axi ]
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set_property -dict [ list \
|
||||
CONFIG.REG_CONFIG {0} \
|
||||
CONFIG.TDATA_NUM_BYTES {16} \
|
||||
] $adc_q_data_from_axi
|
||||
|
||||
# Create instance: const_1, and set properties
|
||||
set const_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_1 ]
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net adc_i_data_in_1 [get_bd_intf_ports adc_i_data_in] [get_bd_intf_pins adc_i_data_from_axi/S_AXIS]
|
||||
connect_bd_intf_net -intf_net adc_iq_repacker_0_data_out [get_bd_intf_pins adc_data_to_axi/S_AXIS] [get_bd_intf_pins adc_iq_repacker/data_out]
|
||||
connect_bd_intf_net -intf_net adc_q_data_from_axi1_M_AXIS [get_bd_intf_ports adc_data_out] [get_bd_intf_pins adc_data_to_axi/M_AXIS]
|
||||
connect_bd_intf_net -intf_net adc_q_data_in_1 [get_bd_intf_ports adc_q_data_in] [get_bd_intf_pins adc_q_data_from_axi/S_AXIS]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net adc_i_data_from_axi_m_axis_tdata [get_bd_pins adc_i_data_from_axi/m_axis_tdata] [get_bd_pins adc_iq_repacker/adc_i_in]
|
||||
connect_bd_net -net adc_i_data_from_axi_m_axis_tvalid [get_bd_pins adc_i_data_from_axi/m_axis_tvalid] [get_bd_pins adc_iq_repacker/valid_in]
|
||||
connect_bd_net -net adc_q_data_from_axi_m_axis_tdata [get_bd_pins adc_iq_repacker/adc_q_in] [get_bd_pins adc_q_data_from_axi/m_axis_tdata]
|
||||
connect_bd_net -net const_1_dout [get_bd_pins adc_i_data_from_axi/m_axis_tready] [get_bd_pins adc_q_data_from_axi/m_axis_tready] [get_bd_pins const_1/dout]
|
||||
connect_bd_net -net enable_data_to_repacker_rclk_1 [get_bd_ports enable_data_to_repacker_rclk] [get_bd_pins adc_iq_repacker/enable]
|
||||
connect_bd_net -net rfdc_adc_axi_resetn_rclk_1 [get_bd_ports rfdc_adc_axi_resetn_rclk] [get_bd_pins adc_data_to_axi/aresetn] [get_bd_pins adc_i_data_from_axi/aresetn] [get_bd_pins adc_q_data_from_axi/aresetn]
|
||||
connect_bd_net -net rfdc_clk_1 [get_bd_ports rfdc_clk] [get_bd_pins adc_data_to_axi/aclk] [get_bd_pins adc_i_data_from_axi/aclk] [get_bd_pins adc_iq_repacker/clk] [get_bd_pins adc_q_data_from_axi/aclk]
|
||||
connect_bd_net -net swap_iq_rclk_1 [get_bd_ports swap_iq_rclk] [get_bd_pins adc_iq_repacker/swap_iq]
|
||||
|
||||
# Create address segments
|
||||
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
|
||||
validate_bd_design
|
||||
save_bd_design
|
||||
}
|
||||
# End of create_root_design()
|
||||
|
||||
|
||||
##################################################################
|
||||
# MAIN FLOW
|
||||
##################################################################
|
||||
|
||||
create_root_design ""
|
||||
|
||||
|
||||
@@ -0,0 +1,6 @@
|
||||
set script_loc [file normalize [info script]]
|
||||
set script_dir [file dirname $script_loc]
|
||||
|
||||
# Vivado's block diagram default library for files not belonging to any special
|
||||
# library is called xil_defaultlib
|
||||
read_verilog -library xil_defaultlib $script_dir/../../rf/common/adc_iq_repacker.v
|
||||
@@ -0,0 +1,21 @@
|
||||
#
|
||||
# Copyright 2022 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
||||
|
||||
include $(TOOLS_DIR)/make/viv_ip_builder.mak
|
||||
|
||||
IP_DDR4_64BITS_X440_SRCS = \
|
||||
$(IP_BUILD_DIR)/ddr4_64bits_x440/ddr4_64bits_x440.xci
|
||||
|
||||
IP_DDR4_64BITS_X440_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr4_64bits_x440/, \
|
||||
ddr4_64bits_x440.xci.out \
|
||||
)
|
||||
|
||||
.INTERMEDIATE: IP_DDR4_64BITS_X440_TRGT
|
||||
$(IP_DDR4_64BITS_X440_SRCS) $(IP_DDR4_64BITS_X440_OUTS): IP_DDR4_64BITS_X440_TRGT
|
||||
@:
|
||||
|
||||
IP_DDR4_64BITS_X440_TRGT: $(IP_DIR)/ddr4_64bits_x440/ddr4_64bits_x440.xci
|
||||
$(call BUILD_VIVADO_IP,ddr4_64bits_x440,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
|
||||
@@ -0,0 +1,493 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>ddr4_64bits_x440</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="ddr4" spirit:version="2.2"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.BURST_LENGTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.CAN_DEBUG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.CAS_LATENCY">11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.CS_ENABLED">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.CUSTOM_PARTS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.DATA_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.MEMORY_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.SLOT">Single</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.DATA_WIDTH">512</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_BRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_BURST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_CACHE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_LOCK">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_PROT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_QOS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_RRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ID_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.MAX_BURST_LENGTH">256</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_READ_OUTSTANDING">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_WRITE_OUTSTANDING">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.PROTOCOL">AXI4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.SUPPORTS_NARROW_BURST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ADDR_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.DATA_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_PROT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_RRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_WSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK.CAN_DEBUG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYSTEM_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.APP_ADDR_WIDTH">29</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.APP_DATA_WIDTH">512</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.APP_MASK_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.BUFG_DIV_LOC_1">X0Y11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.BUFG_DIV_LOC_2">X0Y10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.BUFG_LOC_1">X0Y70</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.BUFG_LOC_2">X0Y11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.CENTER_BANK_CLOCK_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.CENTER_BANK_MMCME3_ADV_SITE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.ControllerType">DDR4_SDRAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_ADDR_WIDTH">17</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_AL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_AUTO_AP_COL_A3">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_AXI_DATA_WIDTH">512</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_AXI_ID_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_BANK_GROUP_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_BANK_WIDTH">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_BURST_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_BURST_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CA_MIRROR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CKE_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CK_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CLKFBOUT_MULT">15</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CLKIN_PERIOD">9996</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CLKOUT1_DIVIDE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CLKOUTPHY_MODE">VCO_2X</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_COLUMN_WIDTH">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_COMP_DENSITY">8Gb</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CS_ADDR">29</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CS_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_CWL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_Configuration">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DATABITS_PER_STROBE">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DATA_MASK">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DBAW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DCI_CASCADE_CUTOFF">938</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DM_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DQS_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DQ_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_Ecc">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_HR_MIN_FREQ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_IO_VOLTAGE">1.2V</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_IS_CUSTOM">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_IS_FASTER_SPEED_RAM">No</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MAX_PERIOD">1600</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MCS_ECC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEMORY_PART">MT40A512M16HA-075E</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEMORY_TYPE">Components</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_COMP_WIDTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY">8Gb</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY_GB">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_DENSITY_MB">8192</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_DEVICE_WIDTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MEM_SIZE">4294967296</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MIN_PERIOD">750</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MODEL_SPEED_GRADE">DDR4_750_Timing</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MR0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MR2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_Mem_Add_Map">ROW_COLUMN_BANK</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_ODT_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_OUTPUT_DRV">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_RANK_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_ROW_WIDTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_RTT_NOM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_RTT_WR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_SPEED_GRADE">075E</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_Slot">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_StackHeight">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_UI_CLOCK">300000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_USE_CS_PORT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_USE_DM_PORT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_VrefVoltage">0.84</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_nAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_nCK_PER_CLK">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_nCS_PER_RANK">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tCCD_3ds">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tCK">833</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tCKE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tFAW">37</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tFAW_dlr">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tMRD">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRAS">39</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRCD">17</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tREFI">9363</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRFC">421</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRFC_dlr">145</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRP">17</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRRD"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRRD_L">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRRD_S">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRRD_dlr">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tRTP">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tWR">19</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tWTR"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tWTR_L">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tWTR_S">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tXPR">109</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tZQCS">128</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tZQI">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_tZQINIT">256</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.MEM_TYPE">DDR4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.MMCM_IDX_BANK">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.PBLOCK_RAMB18_LOC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.PBLOCK_RAMB18_LOC_SC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.PBLOCK_RAMB36_LOC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.PBLOCK_RAMB36_LOC_SC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.PBLOCK_SLICE_LOC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.PBLOCK_SLICE_LOC_SC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.SYSCLK_CENTER_INFO">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CAL_INPUT_CLK_PERIOD">9996</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKOUT0_DIVIDE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKOUT1_DIVIDE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKOUT2_DIVIDE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKOUT3_DIVIDE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKOUT4_DIVIDE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CLKOUT6_DIVIDE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CUSTOM_PART_ATTRIBUTES">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.Debug_Signal">Disable</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.LR_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT1_FREQ_HZ">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT1_PHASE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT2_FREQ_HZ">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT2_PHASE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT3_FREQ_HZ">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT3_PHASE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT4_FREQ_HZ">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT4_PHASE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PING_PONG_PHY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.Simulation_Mode">BFM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.System_Clock">Differential</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDN_UI_CLKOUT1_FREQ_HZ">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDN_UI_CLKOUT2_FREQ_HZ">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDN_UI_CLKOUT3_FREQ_HZ">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDN_UI_CLKOUT4_FREQ_HZ">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AL_SEL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.ADDR_WIDTH">17</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.BANK_GROUP_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.CKE_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.CK_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.CS_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.ControllerType">DDR4_SDRAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ACT_SKEW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_10">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_11">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_12">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_13">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_14">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_15">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_16">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_17">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_3">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_4">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_5">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_6">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_7">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_8">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ADDR_SKEW_9">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AUTO_AP_COL_A3">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AutoPrecharge">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiAddressWidth">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiArbitrationScheme">RD_PRI_REG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiDataWidth">512</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiIDWidth">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiNarrowBurst">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_AxiSelection">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BA_SKEW_0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BA_SKEW_1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BG_SKEW_0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BG_SKEW_1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BurstLength">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_BurstType">Sequential</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CKE_SKEW_0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CKE_SKEW_1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CKE_SKEW_2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CKE_SKEW_3">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CK_SKEW_0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CK_SKEW_1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CK_SKEW_2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CK_SKEW_3">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CLKFBOUT_MULT">15</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CS_SKEW_0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CS_SKEW_1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CS_SKEW_2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CS_SKEW_3">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Capacity">512</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CasLatency">17</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CasWriteLatency">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ChipSelect">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Clamshell">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_CustomParts">no_file_loaded</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DataMask">DM_NO_DBI</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DataWidth">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_EN_PARITY">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Ecc">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Enable_LVAUX">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_InputClockPeriod">9996</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_LR_SKEW_0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_LR_SKEW_1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MCS_ECC">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Mem_Add_Map">ROW_COLUMN_BANK</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryName">MainMemory</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryPart">MT40A512M16HA-075E</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryType">Components</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_MemoryVoltage">1.2V</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_ODT_SKEW_3">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_OnDieTermination">RZQ/6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Ordering">Normal</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_OutputDriverImpedenceControl">RZQ/7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_PAR_SKEW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_PhyClockRatio">4:1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_RESTORE_CRC">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_SAVE_RESTORE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_SELF_REFRESH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Slot">Single</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Specify_MandD">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TREFI">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TRFC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TRFC_DLR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TXPR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_TimePeriod">833</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_UserRefresh_ZQCS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_isCKEShared">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_isCustom">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_nCK_TREFI">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_nCK_TRFC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_nCK_TRFC_DLR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_nCK_TXPR">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.LR_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.MIGRATION">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.ODT_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.StackHeight">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0_CLOCK_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0_DDR4_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">ddr4_64bits_x440</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCI_Cascade">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_TERM_SYSCLK">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Debug_Signal">Disable</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Default_Bank_Selections">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_PP_4R_MIR">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_SysPorts">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Example_TG">SIMPLE_TG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IOPowerReduction">OFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IO_Power_Reduction">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IS_FROM_PHY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MCS_DBG_EN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MCS_WO_DSP">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.No_Controller">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PARTIAL_RECONFIG_FLOW_MIG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PING_PONG_PHY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phy_Only">Complete_Memory_Controller</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RECONFIG_XSDB_SAVE_RESTORE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reference_Clock">Differential</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SET_DW_TO_40">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Simulation_Mode">BFM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.System_Clock">Differential</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TIMING_3DS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TIMING_OP1">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TIMING_OP2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynquplusRFSOC</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xczu28dr</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffvg1517</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.1_AR76780</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ID_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.BUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.DATA_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_BURST" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_CACHE" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_LOCK" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_PROT" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_QOS" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_REGION" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_RRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.HAS_WSTRB" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.ID_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.PROTOCOL" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.RUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.WUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.BANK_GROUP_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_AxiAddressWidth" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_AxiDataWidth" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_AxiSelection" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKFBOUT_MULT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CLKOUT0_DIVIDE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasLatency" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_CasWriteLatency" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_DataWidth" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_InputClockPeriod" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MemoryPart" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_Specify_MandD" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_TimePeriod" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
<xilinx:boundaryDescriptionInfo>
|
||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"c0_ddr4_act_n":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"c0_ddr4_adr":[{"direction":"out","physical_left":"16","physical_right":"0","is_vector":"true"}],"c0_ddr4_aresetn":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"c0_ddr4_ba":[{"direction":"out","physical_left":"1","physical_right":"0","is_vector":"true"}],"c0_ddr4_bg":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"c0_ddr4_ck_c":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"c0_ddr4_ck_t":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"c0_ddr4_cke":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"c0_ddr4_cs_n":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"c0_ddr4_dm_dbi_n":[{"direction":"inout","physical_left":"7","physical_right":"0","is_vector":"true"}
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|
||||
s_axi_awready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"AWSIZE":[{"physical_name":"c0_ddr4_s_axi_awsize","physical_left":"2","physical_right":"0","logical_left":"2","logical_right":"0","port_maps_used":"none"}],"AWUSER":[{"physical_name":"c0_ddr4_s_axi_awuser","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"AWVALID":[{"physical_name":"c0_ddr4_s_axi_awvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"BID":[{"physical_name":"c0_ddr4_s_axi_bid","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"BREADY":[{"physical_name":"c0_ddr4_s_axi_bready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"BRESP":[{"physical_name":"c0_ddr4_s_axi_bresp","physical_left":"1","physical_right":"0","logical_left
|
||||
":"1","logical_right":"0","port_maps_used":"none"}],"BVALID":[{"physical_name":"c0_ddr4_s_axi_bvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RDATA":[{"physical_name":"c0_ddr4_s_axi_rdata","physical_left":"511","physical_right":"0","logical_left":"511","logical_right":"0","port_maps_used":"none"}],"RID":[{"physical_name":"c0_ddr4_s_axi_rid","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"RLAST":[{"physical_name":"c0_ddr4_s_axi_rlast","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RREADY":[{"physical_name":"c0_ddr4_s_axi_rready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RRESP":[{"physical_name":"c0_ddr4_s_axi_rresp","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0","port_maps_used":"none"}],"RVALID":[{"physica
|
||||
l_name":"c0_ddr4_s_axi_rvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"WDATA":[{"physical_name":"c0_ddr4_s_axi_wdata","physical_left":"511","physical_right":"0","logical_left":"511","logical_right":"0","port_maps_used":"none"}],"WLAST":[{"physical_name":"c0_ddr4_s_axi_wlast","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"WREADY":[{"physical_name":"c0_ddr4_s_axi_wready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"WSTRB":[{"physical_name":"c0_ddr4_s_axi_wstrb","physical_left":"63","physical_right":"0","logical_left":"63","logical_right":"0","port_maps_used":"none"}],"WVALID":[{"physical_name":"c0_ddr4_s_axi_wvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"C0_SYS_CLK":{"vlnv":"xilinx.com:interface:diff_clock:1.0","abstraction_type":"x
|
||||
ilinx.com:interface:diff_clock_rtl:1.0","mode":"slave","parameters":{"BOARD.ASSOCIATED_PARAM":[{"value":"C0_CLOCK_BOARD_INTERFACE","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"CAN_DEBUG":[{"value":"false","value_src":"default","value_permission":"user","resolve_type":"generated","format":"bool","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK_N":[{"physical_name":"c0_sys_clk_n","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"CLK_P":[{"physical_name":"c0_sys_clk_p","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"SYSTEM_RESET":{"vlnv":"xi
|
||||
linx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"slave","parameters":{"BOARD.ASSOCIATED_PARAM":[{"value":"RESET_BOARD_INTERFACE","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_HIGH","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"RST":[{"physical_name":"sys_rst","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}}},"memory_maps":{"C0_DDR4_MEMORY_MAP":{"address_blocks":{"C0_DDR4_ADDRESS_BLOCK":[{"base_address":"0","range":"4294967296","display_name"
|
||||
:"","description":"","usage":"memory","access":"read-write"}]}},"C0_DDR4_MEMORY_MAP_CTRL":{"address_blocks":{"C0_REG":[{"base_address":"0","range":"4096","display_name":"","description":"","usage":"register","access":"read-write"}]}}}}}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
@@ -1,50 +0,0 @@
|
||||
#
|
||||
# Copyright 2021 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
||||
|
||||
include $(TOOLS_DIR)/make/viv_ip_builder.mak
|
||||
|
||||
IP_X4XX_PS_RFDC_ORIG_SRCS = $(addprefix $(IP_DIR)/x4xx_ps_rfdc_bd/, \
|
||||
x4xx_ps_rfdc_bd.tcl \
|
||||
)
|
||||
|
||||
IP_X4XX_PS_RFDC_HDL_SRCS = $(addprefix $(BASE_DIR)/x400/rf/common/, \
|
||||
capture_sysref.v \
|
||||
rf_nco_reset.vhd \
|
||||
rf_reset_controller.vhd \
|
||||
rf_reset.vhd \
|
||||
clock_gates.vhd \
|
||||
sync_wrapper.v \
|
||||
axis_mux.vhd \
|
||||
gpio_to_axis_mux.vhd \
|
||||
) \
|
||||
$(addprefix $(BASE_DIR)/../lib/control/, \
|
||||
synchronizer.v \
|
||||
synchronizer_impl.v \
|
||||
) \
|
||||
$(addprefix $(BASE_DIR)/x400/regmap/, PkgRFDC_REGS_REGMAP.vhd )
|
||||
|
||||
IP_X4XX_PS_RFDC_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/x4xx_ps_rfdc_bd/, \
|
||||
x4xx_ps_rfdc_bd.tcl \
|
||||
)
|
||||
|
||||
IP_X4XX_PS_RFDC_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/x4xx_ps_rfdc_bd/, \
|
||||
x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd.bd \
|
||||
)
|
||||
|
||||
BD_X4XX_PS_RFDC_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/x4xx_ps_rfdc_bd/, \
|
||||
x4xx_ps_rfdc_bd.bd.out \
|
||||
x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd_ooc.xdc \
|
||||
x4xx_ps_rfdc_bd/synth/x4xx_ps_rfdc_bd.v \
|
||||
)
|
||||
|
||||
EMPTY_IP_SRCS =
|
||||
|
||||
.INTERMEDIATE: IP_X4XX_PS_RFDC_BD_TRGT
|
||||
$(IP_X4XX_PS_RFDC_BD_SRCS) $(BD_X4XX_PS_RFDC_BD_OUTS) $(IP_X4XX_PS_RFDC_BDTCL_SRCS): IP_X4XX_PS_RFDC_BD_TRGT
|
||||
@:
|
||||
|
||||
IP_X4XX_PS_RFDC_BD_TRGT: $(IP_X4XX_PS_RFDC_ORIG_SRCS)
|
||||
$(call BUILD_VIVADO_BDTCL,x4xx_ps_rfdc_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_X4XX_PS_RFDC_HDL_SRCS))
|
||||
@@ -1,14 +0,0 @@
|
||||
set script_loc [file normalize [info script]]
|
||||
set script_dir [file dirname $script_loc]
|
||||
|
||||
read_verilog -library work $script_dir/../../rf/common/capture_sysref.v
|
||||
read_verilog -library work $script_dir/../../../../lib/control/synchronizer.v
|
||||
read_verilog -library work $script_dir/../../../../lib/control/synchronizer_impl.v
|
||||
read_verilog -library work $script_dir/../../rf/common/sync_wrapper.v
|
||||
read_vhdl -library work $script_dir/../../rf/common/rf_nco_reset.vhd
|
||||
read_vhdl -library work $script_dir/../../regmap/PkgRFDC_REGS_REGMAP.vhd
|
||||
read_vhdl -library work $script_dir/../../rf/common/rf_reset_controller.vhd
|
||||
read_vhdl -library work $script_dir/../../rf/common/rf_reset.vhd
|
||||
read_vhdl -library work $script_dir/../../rf/common/clock_gates.vhd
|
||||
read_vhdl -library work $script_dir/../../rf/common/axis_mux.vhd
|
||||
read_vhdl -library work $script_dir/../../rf/common/gpio_to_axis_mux.vhd
|
||||
@@ -1,550 +0,0 @@
|
||||
//
|
||||
// Copyright 2021 Ettus Research, A National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: common_regs
|
||||
// Description:
|
||||
// Registers definition within the x4xx_ps_rfdc_bd IP.
|
||||
|
||||
//XmlParse xml_on
|
||||
//<top name="X4XX_FPGA">
|
||||
// <ports>
|
||||
// <info>
|
||||
// This section lists all common Processing System ports through
|
||||
// which the register maps in this project are accessed. Each input
|
||||
// port to the fabric will point to a regmap.
|
||||
// </info>
|
||||
// <port name="ARM_M_AXI_HPM0" targetregmap="AXI_HPM0_REGMAP">
|
||||
// <info>
|
||||
// This is the main AXI4-Lite master interface that the PS
|
||||
// exposes to the kernel to interact with the FPGA fabric.
|
||||
// There are multiple endpoints connected to this interface.
|
||||
// </info>
|
||||
// </port>
|
||||
// <port name="ARM_S_AXI_HPC0" sourcewindow="PL_DMA_MASTER_REGMAP|AXI_HPC0_WINDOW">
|
||||
// <info>
|
||||
// This is one of the two cache-coherent AXI slave ports available to
|
||||
// communicate from the fabric (master) to the PS (slave).
|
||||
// </info>
|
||||
// </port>
|
||||
// <port name="ARM_S_AXI_HPC1" sourcewindow="PL_DMA_MASTER_REGMAP|AXI_HPC1_WINDOW">
|
||||
// <info>
|
||||
// This is one of the two cache-coherent AXI slave ports available to
|
||||
// communicate from the fabric (master) to the PS (slave).
|
||||
// </info>
|
||||
// </port>
|
||||
// <port name="ARM_SPI1_CS3" targetregmap="MB_CPLD_PS_REGMAP">
|
||||
// <info>
|
||||
// This is the SPI1 interface
|
||||
// (see <a href="https://www.xilinx.com/html_docs/registers/ug1087/mod___spi.html" target="_blank">Zynq UltraScale+ Devices Register Reference</a>)
|
||||
// of the PS.
|
||||
// With chip select 3 enabled transactions are targeted for the PS MB CPLD register interface linked here.{br}
|
||||
// The request format on SPI is defined as.{br}
|
||||
// {b}Write request:{/b}
|
||||
// {ul}
|
||||
// {li}1'b1 = write
|
||||
// {li}15 bit address
|
||||
// {li}32 bit data (MOSI)
|
||||
// {li}8 bit processing gap
|
||||
// {li}5 bit padding
|
||||
// {li}1 bit ack
|
||||
// {li}2 bit status
|
||||
// {/ul}
|
||||
// {b}Read request:{/b}
|
||||
// {ul}
|
||||
// {li}1'b0 = read
|
||||
// {li}15 bit address
|
||||
// {li}8 bit processing gap
|
||||
// {li}32 bit data (MISO)
|
||||
// {li}5 bit padding
|
||||
// {li}1 bit ack
|
||||
// {li}2 bit status
|
||||
// {/ul}
|
||||
// </info>
|
||||
// </port>
|
||||
// </ports>
|
||||
// <regmapcfg readablestrobes="false">
|
||||
// <map name="AXI_HPM0_REGMAP"/>
|
||||
// <map name="MB_CPLD_PS_REGMAP"/>
|
||||
// </regmapcfg>
|
||||
//</top>
|
||||
//
|
||||
//<regmap name="AXI_HPM0_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
|
||||
// <info>
|
||||
// This is the map for the register space that the Processing System's
|
||||
// M_AXI_HPM0_FPD port (AXI4 master interface) has access to.
|
||||
// This port has a 40-bit address bus.
|
||||
// </info>
|
||||
// <group name="COMMON">
|
||||
// <window name="RPU" offset="0x0080000000" size="0x00010000">
|
||||
// <info>Space reserved for RPU access</info>
|
||||
// </window>
|
||||
// <window name="JTAG_ENGINE" offset="0x1000000000" size="0x1000">
|
||||
// <info>Register space for the JTAG engine for MB CPLD programming.</info>
|
||||
// </window>
|
||||
// <window name="RESERVED" offset="0x100003F000" size="0x1000">
|
||||
// <info>Register space reserved for future use.</info>
|
||||
// </window>
|
||||
// <window name="MPM_ENDPOINT" offset="0x1000080000" size="0x20000"
|
||||
// targetregmap="PL_CPLD_REGMAP">
|
||||
// <info>MPM endpoint fro MB/DB communication.</info>
|
||||
// </window>
|
||||
// <window name="CORE_REGS" offset="0x10000A0000" size="0x4000"
|
||||
// targetregmap="CORE_REGS_REGMAP">
|
||||
// <info>Register space reserved for mboard-regs (Core).</info>
|
||||
// </window>
|
||||
// <window name="INT_ETH_DMA" offset="0x10000A4000" size="0x6000"
|
||||
// targetregmap="ETH_DMA_CTRL_REGMAP">
|
||||
// <info>AXI DMA engine for internal Ethernet interface.</info>
|
||||
// </window>
|
||||
// <window name="INT_ETH_REGS" offset="0x10000AA000" size="0x2000">
|
||||
// <info>Misc. registers for internal Ethernet.</info>
|
||||
// </window>
|
||||
// <window name="RFDC" offset="0x1000100000" size="0x40000">
|
||||
// <info>Register space occupied by the Xilinx RFDC IP block.</info>
|
||||
// </window>
|
||||
// <window name="RFDC_REGS" offset="0x1000140000" size="0x20000"
|
||||
// targetregmap="RFDC_REGS_REGMAP">
|
||||
// <info>Register space for RFDC control/status registers.</info>
|
||||
// </window>
|
||||
// </group>
|
||||
//</regmap>
|
||||
//
|
||||
//<regmap name="ETH_DMA_CTRL_REGMAP" readablestrobes="false" generatevhdl="true" generateverilog="false" ettusguidelines="true">
|
||||
// <info>
|
||||
// This is the map that the nixge driver uses in Ethernet DMA to
|
||||
// move data between the Processing System's architecture and the fabric.
|
||||
// This map is a combination of two main components: a Xilix AXI DMA engine
|
||||
// and some registers for MAC/PHY control.
|
||||
// </info>
|
||||
// <group name="ETH_DMA_CTRL">
|
||||
// <window name="AXI_DMA_CTRL" offset="0x0" size="0x4000">
|
||||
// <info>
|
||||
// Refer to Xilinx' AXI DMA v7.1 IP product guide for further
|
||||
// information on this register map:
|
||||
// https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf
|
||||
// </info>
|
||||
// </window>
|
||||
// <window name="ETH_IO_CTRL" offset="0x4000" size="0x2000">
|
||||
// <info>MAC/PHY control for the Ethernet interface.</info>
|
||||
// </window>
|
||||
// </group>
|
||||
//</regmap>
|
||||
//<regmap name="PL_DMA_MASTER_REGMAP" readablestrobes="false" generatevhdl="true" generateverilog="false" ettusguidelines="true">
|
||||
// <info>
|
||||
// This is a regmap to document the different ports that have access to the PS system memory.
|
||||
// Each port may have different restrictions on system memory. See the corresponding window
|
||||
// for details
|
||||
// </info>
|
||||
// <group name="HPC0_DMA">
|
||||
// <window name="AXI_HPC0_WINDOW" offset="0x0" size="0x10000000000">
|
||||
// <info>
|
||||
// The HPC0 port of the PS is used for general purpose cache-coherent accesses
|
||||
// to the PS system memory. Different applications may use it for different
|
||||
// purposes. Its access is configured as follows: {br}
|
||||
// {table border="1"}
|
||||
// {tr}{th}Offset{/th} {th}Size{/th} {th}Description{/th}{tr}
|
||||
// {tr}{td}0x000800000000{/td}{td}0x000800000000{/td}{td}DDR_HIGH{/td}{tr}
|
||||
// {tr}{td}0x00000000{/td} {td}0x80000000{/td} {td}DDR_LOW{/td}{tr}
|
||||
// {tr}{td}0xFF000000{/td} {td}0x01000000{/td} {td}LPS_OCM{/td}{tr}
|
||||
// {tr}{td}0xC0000000{/td} {td}0x20000000{/td} {td}QSPI{/td}{tr}
|
||||
// {/table}
|
||||
// </info>
|
||||
// </window>
|
||||
// </group>
|
||||
// <group name="HPC1_DMA">
|
||||
// <window name="AXI_HPC1_WINDOW" offset="0x0" size="0x1000000000">
|
||||
// <info>
|
||||
// The HPC1 port of the PS is connected to the Ethernet DMA module. Three slave
|
||||
// interfaces are lumped together in this window: scatter-gather, dma-rx, and dma-tx.
|
||||
// Its access is configured as follows: {br}
|
||||
// {table border="1"}
|
||||
// {tr}{th}Offset{/th} {th}Size{/th} {th}Description{/th}{tr}
|
||||
// {tr}{td}0x000800000000{/td}{td}0x000800000000{/td}{td}DDR_HIGH{/td}{tr}
|
||||
// {tr}{td}0x00000000{/td} {td}0x80000000{/td} {td}DDR_LOW{/td}{tr}
|
||||
// {tr}{td}0xC0000000{/td} {td}0x20000000{/td} {td}QSPI{/td}{tr}
|
||||
// {/table}
|
||||
// </info>
|
||||
// </window>
|
||||
// </group>
|
||||
//</regmap>
|
||||
//
|
||||
//<regmap name="RFDC_REGS_REGMAP" readablestrobes="false" generatevhdl="true" generateverilog="true" ettusguidelines="true">
|
||||
// <group name="RFDC_REGS">
|
||||
// <info>
|
||||
// These are the registers located within the RFDC block design
|
||||
// that provide control and status support for the RF chain.
|
||||
// </info>
|
||||
//
|
||||
// <window name="MMCM" offset="0x0" size="0x10000">
|
||||
// <info>
|
||||
// Register space for controlling the data clock MMCM instance
|
||||
// within the RFDC block design.
|
||||
// Refer to Xilinx' Clocking Wizard v6.0 Product Guide for the
|
||||
// regiter space description in chapter 2.
|
||||
// (https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf)
|
||||
// </info>
|
||||
// </window>
|
||||
//
|
||||
// <register name="INVERT_IQ_REG" offset="0x10000" size="32">
|
||||
// <info>Control register for inverting I/Q data.</info>
|
||||
// <!-- TODO: possibly redo these bitfields -->
|
||||
// <bitfield name="INVERT_DB0_ADC0_IQ" range="0"/>
|
||||
// <bitfield name="INVERT_DB0_ADC1_IQ" range="1"/>
|
||||
// <bitfield name="INVERT_DB0_ADC2_IQ" range="2"/>
|
||||
// <bitfield name="INVERT_DB0_ADC3_IQ" range="3"/>
|
||||
// <bitfield name="INVERT_DB1_ADC0_IQ" range="4"/>
|
||||
// <bitfield name="INVERT_DB1_ADC1_IQ" range="5"/>
|
||||
// <bitfield name="INVERT_DB1_ADC2_IQ" range="6"/>
|
||||
// <bitfield name="INVERT_DB1_ADC3_IQ" range="7"/>
|
||||
// <bitfield name="INVERT_DB0_DAC0_IQ" range="8"/>
|
||||
// <bitfield name="INVERT_DB0_DAC1_IQ" range="9"/>
|
||||
// <bitfield name="INVERT_DB0_DAC2_IQ" range="10"/>
|
||||
// <bitfield name="INVERT_DB0_DAC3_IQ" range="11"/>
|
||||
// <bitfield name="INVERT_DB1_DAC0_IQ" range="12"/>
|
||||
// <bitfield name="INVERT_DB1_DAC1_IQ" range="13"/>
|
||||
// <bitfield name="INVERT_DB1_DAC2_IQ" range="14"/>
|
||||
// <bitfield name="INVERT_DB1_DAC3_IQ" range="15"/>
|
||||
// </register>
|
||||
//
|
||||
// <register name="MMCM_RESET_REG" offset="0x11000" size="32">
|
||||
// <info>Control register for resetting the data clock MMCM.</info>
|
||||
// <bitfield name="RESET_MMCM" range="0">
|
||||
// <info>
|
||||
// Write a '1' to this bit to reset the MMCM. Then write a
|
||||
// '0' to place the MMCM out of reset.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="RF_RESET_CONTROL_REG" offset="0x12000" size="32">
|
||||
// <info>
|
||||
// Control register for the RF reset controller.
|
||||
// Verify the FSM ID before polling starting any reset sequence.
|
||||
// To use the SW reset triggers: Wait until DB*_DONE is de-asserted.
|
||||
// Assert either the *_RESET or *_ENABLE bitfields.
|
||||
// Wait until DB*_DONE is asserted to release the trigger.
|
||||
// The DB*_DONE signal should then de-assert.{BR/}
|
||||
// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is
|
||||
// merely for documentation.{/b}
|
||||
// </info>
|
||||
// <bitfield name="FSM_RESET" range="0">
|
||||
// <info>
|
||||
// Write a '1' to this bit to reset the RF reset controller.
|
||||
// Write a '0' once db0_fsm_reset_done asserts.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="ADC_RESET" range="4">
|
||||
// <info>
|
||||
// Write a '1' to this bit to trigger a reset for the
|
||||
// daughterboard 0 ADC chain. Write a '0' once db0_adc_seq_done
|
||||
// is asserted.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="ADC_ENABLE" range="5">
|
||||
// <info>
|
||||
// Write a '1' to this bit to trigger the enable sequence for
|
||||
// the daughterboard 0 ADC chain. Write a '0' once
|
||||
// db0_adc_seq_done is asserted.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="DAC_RESET" range="8">
|
||||
// <info>
|
||||
// Write a '1' to this bit to trigger a reset for the
|
||||
// daughterboard 0 DAC chain. Write a '0' once db0_dac_seq_done
|
||||
// is asserted.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="DAC_ENABLE" range="9">
|
||||
// <info>
|
||||
// Write a '1' to this bit to trigger the enable sequence for
|
||||
// the daughterboard 0 DAC chain. Write a '0' once
|
||||
// db0_dac_seq_done is asserted.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="RF_RESET_STATUS_REG" offset="0x12008" size="32" writable="false">
|
||||
// <info>
|
||||
// Status register for the RF reset controller.
|
||||
// Verify the FSM ID before polling starting any reset sequence.
|
||||
// Refer to RF_RESET_CONTROL_REG for instructions on how to use
|
||||
// the status bits in this register.{BR/}
|
||||
// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is
|
||||
// merely for documentation.{/b}
|
||||
// </info>
|
||||
// <bitfield name="FSM_RESET_DONE" range="3">
|
||||
// <info>
|
||||
// This bit asserts ('1') when the DB0 RF reset controller FSM
|
||||
// reset sequence is completed. The bitfield deasserts ('0')
|
||||
// after deasserting db0_fsm_reset.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="ADC_SEQ_DONE" range="7">
|
||||
// <info>
|
||||
// This bit asserts ('1') when the DB0 ADC chain reset sequence
|
||||
// is completed. The bitfield deasserts ('0') after
|
||||
// deasserting the issued triggered (enable or reset).
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="DAC_SEQ_DONE" range="11">
|
||||
// <info>
|
||||
// This bit asserts ('1') when the DB0 DAC chain reset sequence
|
||||
// is completed. The bitfield deasserts ('0') after
|
||||
// deasserting the issued triggered (enable or reset).
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="RF_AXI_STATUS_REG" offset="0x13000" size="32" writable="false">
|
||||
// <info>
|
||||
// Status register for the RF AXI-Stream interfaces.{BR/}
|
||||
// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is
|
||||
// merely for documentation.{/b}
|
||||
// </info>
|
||||
// <bitfield name="RFDC_DAC_TREADY" range="1..0">
|
||||
// <info>
|
||||
// This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream
|
||||
// TReady handshake signals. The LSB is channel 0 and the MSB
|
||||
// is channel 1.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RFDC_DAC_TVALID" range="3..2">
|
||||
// <info>
|
||||
// This bitfield is wired to the RFDC's DAC (DB0) AXI-Stream
|
||||
// TValid handshake signals. The LSB is channel 0 and the MSB
|
||||
// is channel 1.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RFDC_ADC_Q_TREADY" range="5..4">
|
||||
// <info>
|
||||
// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
|
||||
// TReady handshake signals (Q portion). The LSB is channel 0
|
||||
// and the MSB is channel 1.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RFDC_ADC_I_TREADY" range="7..6">
|
||||
// <info>
|
||||
// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
|
||||
// TReady handshake signals (I portion). The LSB is channel 0
|
||||
// and the MSB is channel 1.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RFDC_ADC_Q_TVALID" range="9..8">
|
||||
// <info>
|
||||
// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
|
||||
// TValid handshake signals (Q portion). The LSB is channel 0
|
||||
// and the MSB is channel 1.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RFDC_ADC_I_TVALID" range="11..10">
|
||||
// <info>
|
||||
// This bitfield is wired to the RFDC's ADC (DB0) AXI-Stream
|
||||
// TValid handshake signals (I portion). The LSB is channel 0
|
||||
// and the MSB is channel 1.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="USER_ADC_TVALID" range="13..12">
|
||||
// <info>
|
||||
// This bitfield is wired to the user's ADC (DB0) AXI-Stream
|
||||
// TValid handshake signals. The LSB is channel 0 and the MSB
|
||||
// is channel 1.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="USER_ADC_TREADY" range="15..14">
|
||||
// <info>
|
||||
// This bitfield is wired to the user's ADC (DB0) AXI-Stream
|
||||
// TReady handshake signals. The LSB is channel 0 and the MSB
|
||||
// is channel 1.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RFDC_DAC_TREADY_DB1" range="17..16">
|
||||
// <info>
|
||||
// This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream
|
||||
// TReady handshake signals. The LSB is channel 0 and the MSB
|
||||
// is channel 1.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RFDC_DAC_TVALID_DB1" range="19..18">
|
||||
// <info>
|
||||
// This bitfield is wired to the RFDC's DAC (DB1) AXI-Stream
|
||||
// TValid handshake signals. The LSB is channel 0 and the MSB
|
||||
// is channel 1.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RFDC_ADC_Q_TREADY_DB1" range="21..20">
|
||||
// <info>
|
||||
// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
|
||||
// TReady handshake signals (Q portion). The LSB is channel 0
|
||||
// and the MSB is channel 1.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RFDC_ADC_I_TREADY_DB1" range="23..22">
|
||||
// <info>
|
||||
// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
|
||||
// TReady handshake signals (I portion). The LSB is channel 0
|
||||
// and the MSB is channel 1.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RFDC_ADC_Q_TVALID_DB1" range="25..24">
|
||||
// <info>
|
||||
// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
|
||||
// TValid handshake signals (Q portion). The LSB is channel 0
|
||||
// and the MSB is channel 1.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RFDC_ADC_I_TVALID_DB1" range="27..26">
|
||||
// <info>
|
||||
// This bitfield is wired to the RFDC's ADC (DB1) AXI-Stream
|
||||
// TValid handshake signals (I portion). The LSB is channel 0
|
||||
// and the MSB is channel 1.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="USER_ADC_TVALID_DB1" range="29..28">
|
||||
// <info>
|
||||
// This bitfield is wired to the user's ADC (DB1) AXI-Stream
|
||||
// TValid handshake signals. The LSB is channel 0 and the MSB
|
||||
// is channel 1.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="USER_ADC_TREADY_DB1" range="31..30">
|
||||
// <info>
|
||||
// This bitfield is wired to the user's ADC (DB1) AXI-Stream
|
||||
// TReady handshake signals. The LSB is channel 0 and the MSB
|
||||
// is channel 1.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="CALIBRATION_DATA" offset="0x014000">
|
||||
// <info>
|
||||
// The fields of this register provide data to all the DAC channels when enabled
|
||||
// by the CALIBRATION_ENABLE register.
|
||||
// </info>
|
||||
// <bitfield name="Q_DATA" range="31..16">
|
||||
// </bitfield>
|
||||
// <bitfield name="I_DATA" range="15..00">
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="CALIBRATION_ENABLE" offset="0x014008">
|
||||
// <info>
|
||||
// This register enables calibration data in the DAC data path for each of the
|
||||
// four channels. Each of these bits is normally '0'. When written '1', DAC data
|
||||
// for the corresponding channel will be constantly driven with the contents of
|
||||
// the CALIBRATION_DATA register.
|
||||
// </info>
|
||||
// <bitfield name="ENABLE_CALIBRATION_DATA_0" range="0">
|
||||
// <info>
|
||||
// Enables calibration data for channel 0.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="ENABLE_CALIBRATION_DATA_1" range="1">
|
||||
// <info>
|
||||
// Enables calibration data for channel 1.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="ENABLE_CALIBRATION_DATA_2" range="4">
|
||||
// <info>
|
||||
// Enables calibration data for channel 2.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="ENABLE_CALIBRATION_DATA_3" range="5">
|
||||
// <info>
|
||||
// Enables calibration data for channel 3.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="RF_PLL_CONTROL_REG" offset="0x16000" size="32" writable="true">
|
||||
// <info>
|
||||
// Enable RF MMCM outputs.
|
||||
// </info>
|
||||
// <bitfield name="ENABLE_DATA_CLK" range="0"/>
|
||||
// <bitfield name="ENABLE_DATA_CLK_2X" range="4"/>
|
||||
// <bitfield name="ENABLE_RF_CLK" range="8"/>
|
||||
// <bitfield name="ENABLE_RF_CLK_2X" range="12"/>
|
||||
// <bitfield name="CLEAR_DATA_CLK_UNLOCKED" range="16"/>
|
||||
// </register>
|
||||
//
|
||||
// <register name="RF_PLL_STATUS_REG" offset="0x16008" size="32" writable="false">
|
||||
// <info>
|
||||
// Data Clk Pll Status Register
|
||||
// </info>
|
||||
// <bitfield name="DATA_CLK_PLL_UNLOCKED_STICKY" range="16"/>
|
||||
// <bitfield name="DATA_CLK_PLL_LOCKED" range="20"/>
|
||||
// </register>
|
||||
//
|
||||
// <register name="THRESHOLD_STATUS" offset="0x015000">
|
||||
// <info>
|
||||
// This register shows threshold status for the ADCs. Each bit reflects the
|
||||
// RFDC's real-time ADC status signals, which will assert when the ADC input
|
||||
// signal exceeds the programmed threshold value. The status will remain
|
||||
// asserted until cleared by software.
|
||||
// The bitfield names follow the pattern ADCX_ZZ_over_threshold(1|2), where X is
|
||||
// the location of the tile in the converter column and ZZ is either 01 (the
|
||||
// lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile).
|
||||
// See also the Xilinx document PG269.
|
||||
// </info>
|
||||
// <bitfield name="ADC0_01_THRESHOLD1" range="0">
|
||||
// </bitfield>
|
||||
// <bitfield name="ADC0_01_THRESHOLD2" range="1">
|
||||
// </bitfield>
|
||||
// <bitfield name="ADC0_23_THRESHOLD1" range="2">
|
||||
// </bitfield>
|
||||
// <bitfield name="ADC0_23_THRESHOLD2" range="3">
|
||||
// </bitfield>
|
||||
// <bitfield name="ADC2_01_THRESHOLD1" range="8">
|
||||
// </bitfield>
|
||||
// <bitfield name="ADC2_01_THRESHOLD2" range="9">
|
||||
// </bitfield>
|
||||
// <bitfield name="ADC2_23_THRESHOLD1" range="10">
|
||||
// </bitfield>
|
||||
// <bitfield name="ADC2_23_THRESHOLD2" range="11">
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <enumeratedtype name="FABRIC_DSP_BW_ENUM" showhex="true">
|
||||
// <value name="FABRIC_DSP_BW_NONE" integer="0"/>
|
||||
// <value name="FABRIC_DSP_BW_100M" integer="100"/>
|
||||
// <value name="FABRIC_DSP_BW_200M" integer="200"/>
|
||||
// <value name="FABRIC_DSP_BW_400M" integer="400"/>
|
||||
// </enumeratedtype>
|
||||
//
|
||||
// <register name="FABRIC_DSP_REG" offset="0x13008" size="32" writable="false">
|
||||
// <info>
|
||||
// This register provides information to the driver on the type
|
||||
// of DSP that is instantiated in the fabric.{BR/}
|
||||
// The X410 platform supports multiple RF daughterboards, each requiring
|
||||
// a different fabric RF DSP chain that works with specific RFDC settings.
|
||||
// Each bandwidth DSP chain has a unique identifier (BW in MHz), this
|
||||
// information is conveyed in this register to let the driver
|
||||
// configure the RFDC with the proper settings.
|
||||
// Also, channel count for the DSP module is included.{BR/}
|
||||
// {b}Note: The *_DB1 constants are not used in the HDL, their purpose is
|
||||
// merely for documentation.{/b}
|
||||
// </info>
|
||||
// <bitfield name="FABRIC_DSP_BW" range="11..0" type="FABRIC_DSP_BW_ENUM" initialvalue="FABRIC_DSP_BW_NONE">
|
||||
// <info>Fabric DSP BW in MHz for daughterboard 0.</info>
|
||||
// </bitfield>
|
||||
// <bitfield name="FABRIC_DSP_RX_CNT" range="13..12" initialvalue="0">
|
||||
// <info>Fabric DSP RX channel count for daughterboard 0.</info>
|
||||
// </bitfield>
|
||||
// <bitfield name="FABRIC_DSP_TX_CNT" range="15..14" initialvalue="0">
|
||||
// <info>Fabric DSP TX channel count for daughterboard 0.</info>
|
||||
// </bitfield>
|
||||
// <bitfield name="FABRIC_DSP_BW_DB1" range="27..16" type="FABRIC_DSP_BW_ENUM" initialvalue="FABRIC_DSP_BW_NONE">
|
||||
// <info>Fabric DSP BW in MHz for daughterboard 1.</info>
|
||||
// </bitfield>
|
||||
// <bitfield name="FABRIC_DSP_RX_CNT_DB1" range="29..28" initialvalue="0">
|
||||
// <info>Fabric DSP RX channel count for daughterboard 0.</info>
|
||||
// </bitfield>
|
||||
// <bitfield name="FABRIC_DSP_TX_CNT_DB1" range="31..30" initialvalue="0">
|
||||
// <info>Fabric DSP TX channel count for daughterboard 0.</info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// </group>
|
||||
//</regmap>
|
||||
//XmlParse xml_off
|
||||
@@ -1,336 +0,0 @@
|
||||
//
|
||||
// Copyright 2021 Ettus Research, A National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: uhd_regs
|
||||
// Description:
|
||||
// Registers definition within the x4xx_ps_rfdc_bd IP.
|
||||
|
||||
//XmlParse xml_on
|
||||
//<regmap name="CMAC_REGMAP" markdown="true" generateverilog="false">
|
||||
// <group name="XILINX_CMAC_REGISTERS">
|
||||
// <info>
|
||||
// 100G MAC ethernet registers (Link 0) defined in the CMAC Manual starting on pg 187.
|
||||
//
|
||||
// - http://www.xilinx.com/support/documentation/ip_documentation/cmac_usplus/v2_4/pg203-cmac-usplus.pdf
|
||||
//
|
||||
// </info>
|
||||
// </group>
|
||||
//</regmap>
|
||||
|
||||
//XmlParse xml_on
|
||||
//<regmap name="XGE_MAC_REGMAP" markdown="true" generateverilog="false">
|
||||
// <group name="OPENCORE_XGE_REGISTERS">
|
||||
// <info>
|
||||
//
|
||||
// 10G MAC ethernet registers defined in the USRP OSS distribution fpga/usrp3/lib/xge/doc/xge_mac_spec.pdf
|
||||
//
|
||||
// </info>
|
||||
// </group>
|
||||
//</regmap>
|
||||
|
||||
|
||||
//<regmap name="DMA_REGMAP" markdown="true" generateverilog="false">
|
||||
// <group name="XILINX_DMA_REGISTERS">
|
||||
// <info>
|
||||
// Scatter Gather DMA block defined in Xilinx DMA manual start on pg 11
|
||||
//
|
||||
// - https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf
|
||||
//
|
||||
// </info>
|
||||
// </group>
|
||||
//</regmap>
|
||||
|
||||
//<regmap name="NIXGE_REGMAP" markdown="true" generateverilog="false">
|
||||
// <group name="XGE_MAC_WINDOW">
|
||||
// <window name="XGE_MAC" offset="0x1000" size="0x1000" targetregmap="XGE_MAC_REGMAP"/>
|
||||
// </group>
|
||||
// <group name="XGE_MAC_REGS">
|
||||
// <info>
|
||||
// nixge (maps to 10g mac if present)
|
||||
// </info>
|
||||
// <register name="PORT_INFO" offset="0x0000">
|
||||
// <bitfield name="COMPAT_NUM" range="31..24">
|
||||
// <info>
|
||||
// Constant indicating version for this space.
|
||||
// Not used by the NIXGE driver (12/4/2020)
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="ACTIVITY" range="17">
|
||||
// <info>
|
||||
// Generically this mirrors the activity LED. Specific meaning varies based on the MGT_PROTOCOL.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="LINK_UP" range="16">
|
||||
// <info>
|
||||
// Generically means that a connection with a peer has been established. Specific
|
||||
// meaning varies based on the MGT_PROTOCOL.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="MGT_PROTOCOL" range="15..8">
|
||||
// <info>
|
||||
// Constant indicating what flavor of communication this port is using
|
||||
//
|
||||
// - 0 = NONE
|
||||
// - 1 = 1GbE
|
||||
// - 2 = 10GbE
|
||||
// - 3 = Aurora
|
||||
// - 4 = WhiteRabbit
|
||||
// - 5 = 100GbE
|
||||
//
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="PORTNUM" range="7..0">
|
||||
// <info>
|
||||
// Constant indicating which port this register is hooked to
|
||||
//
|
||||
// - 0 = QSFP0
|
||||
// - 1 = QSFP1
|
||||
//
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
// <register name="MAC_CTRL_STATUS" offset="0x0004">
|
||||
// <info>
|
||||
// Definition of this register depends on Protocol
|
||||
//
|
||||
// **10GBE**
|
||||
//
|
||||
// *READ - Status*
|
||||
//
|
||||
// - 0 = status_crc_error
|
||||
// - 1 = status_fragment_error
|
||||
// - 2 = status_txdfifo_ovflow
|
||||
// - 3 = status_txdfifo_udflow
|
||||
// - 4 = status_rxdfifo_ovflow
|
||||
// - 5 = status_rxdfifo_udflow
|
||||
// - 6 = status_pause_frame_rx
|
||||
// - 7 = status_local_fault
|
||||
// - 8 = status_remote_fault
|
||||
//
|
||||
// *WRITE - Ctl*
|
||||
//
|
||||
// - 0 = ctrl_tx_enable
|
||||
//
|
||||
// **100 GBE**
|
||||
//
|
||||
// *READ - Status*
|
||||
//
|
||||
// - 0 = tx_ovfout - Sets if TX overflow reported by CMAC
|
||||
// (Stays set till MAC is reset). This is a fatal error
|
||||
// - 1 = tx_unfout - Sets if TX underflow reported by CMAC
|
||||
// (Stays set till MAC is reset). This is a fatal error
|
||||
// - 2 = stat_rx_aligned - goes high when CMAC has finished
|
||||
// alignment, and is ready to start reception of traffic.
|
||||
// - 3 = mac_dropped_packet - If the mac RX wants to push data(TVALID)
|
||||
// but upstream is trying to hold(TREADY)off we drop a packet.
|
||||
// Upstream circuitry should detect this when traffic is forked
|
||||
// between CHDR and CPU, so this bit will only set if there is a
|
||||
// HW design error.
|
||||
// - 4 = auto_config_done - This bit goes high when the auto_config
|
||||
// state machine finishes operation. It is very similiar to
|
||||
// stat_rx_alligned, but waits for extra writes which occur
|
||||
// after allignement to complete.
|
||||
// - 24:16 = pause_mask - readable version of pause_mask bellow.
|
||||
//
|
||||
// *WRITE - Ctl*
|
||||
//
|
||||
// - 0 = auto_enable - Defaults to ON after reset - Enables a
|
||||
// state machine that performs CMAC register writes to
|
||||
// bring up the MAC without SW intervention.
|
||||
// - 24:16 = pause_mask - A second layer of enables(the first being
|
||||
// register in the CMAC) on the pause_request mechanic. Bits
|
||||
// 7:0 of enable pause on PFC7:0. Bit 8 enables global pause
|
||||
// request (not priority controlled). The mask is used for TX
|
||||
// and RX.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="MAC_PHY_STATUS" offset="0x0008">
|
||||
// <info>
|
||||
//
|
||||
// Definition of this register depends on Protocol
|
||||
//
|
||||
// **10GBE**
|
||||
//
|
||||
// *READ - Status *
|
||||
//
|
||||
// - 0 = core_status 0 - link_up
|
||||
// - 1 = core_status 1
|
||||
// - 2 = core_status 2
|
||||
// - 3 = core_status 3
|
||||
// - 4 = core_status 4
|
||||
// - 5 = core_status 5
|
||||
// - 6 = core_status 6
|
||||
// - 7 = core_status 7
|
||||
//
|
||||
// **100 GBE**
|
||||
//
|
||||
// *READ - Status*
|
||||
//
|
||||
// - 0 = usr_tx_reset - TX PLL's have locked - The clock for the 100G mac isn't stable till this bit sets.
|
||||
// - 1 = usr_rx_reset - RX PLL's have locked
|
||||
//
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="MAC_LED_CTL" offset="0x000C">
|
||||
// <bitfield name="identify_enable" range="0">
|
||||
// <info>
|
||||
// When set identify_value is used to control the activity LED.
|
||||
// When clear the activity LED set on any TX or RX traffic to the mgt
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="identify_value" range="1">
|
||||
// <info>
|
||||
// When identify_enable is set, this value controls the activity LED.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
// <register name="ETH_MDIO_BASE" offset="0x0010">
|
||||
// <info>
|
||||
// The x4xx family of products does not use MDIO.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="AURORA_OVERRUNS" offset="0x0020">
|
||||
// <info>
|
||||
// Only valid if the protocol is Aurora.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="AURORA_CHECKSUM_ERRORS" offset="0x0024">
|
||||
// <info>
|
||||
// Only valid if the protocol is Aurora.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="AURORA_BIST_CHECKER_SAMPS" offset="0x0028">
|
||||
// <info>
|
||||
// Only valid if the protocol is Aurora.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="AURORA_BIST_CHECKER_ERRORS" offset="0x002C">
|
||||
// <info>
|
||||
// Only valid if the protocol is Aurora.
|
||||
// </info>
|
||||
// </register>
|
||||
// </group>
|
||||
//</regmap>
|
||||
//
|
||||
//<regmap name="UIO_REGMAP" markdown="true" generateverilog="false">
|
||||
// <group name="UIO_REGS">
|
||||
// <info>
|
||||
// UIO
|
||||
// </info>
|
||||
// <register name="IP" offset="0x0000">
|
||||
// <info>
|
||||
// Set this port's IP address
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="UDP" offset="0x0004">
|
||||
// <info>
|
||||
// Set the UDP port for CHDR_traffic
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="BRIDGE_MAC_LSB" offset="0x0010">
|
||||
// <info>
|
||||
// If BRIDGE_ENABLE is set use this MAC_ID
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="BRIDGE_MAC_MSB" offset="0x0014">
|
||||
// <info>
|
||||
// If BRIDGE_ENABLE is set use this MAC_ID
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="BRIDGE_IP" offset="0x0018">
|
||||
// <info>
|
||||
// If BRIDGE_ENABLE is set use this IP Address
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="BRIDGE_UDP" offset="0x001C">
|
||||
// <info>
|
||||
// If BRIDGE_ENABLE is set use this UDP Port for CHDR_traffic
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="BRIDGE_ENABLE" offset="0x0020">
|
||||
// <info>
|
||||
// Bit 0 Controls the following logic
|
||||
//
|
||||
//```verilog
|
||||
// always_comb begin : bridge_mux
|
||||
// my_mac = bridge_en ? bridge_mac_reg : mac_reg;
|
||||
// my_ip = bridge_en ? bridge_ip_reg : ip_reg;
|
||||
// my_udp_chdr_port = bridge_en ? bridge_udp_port : udp_port;
|
||||
// end
|
||||
//```
|
||||
//
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="CHDR_DROPPED" offset="0x0030">
|
||||
// <info>
|
||||
// Count the number of Packets dropped that were addressed to the CHDR section.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="CPU_DROPPED" offset="0x0034">
|
||||
// <info>
|
||||
// Count the number of Packets dropped that were addressed to us, but not to the CHDR section.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="PAUSE" offset="0x0038">
|
||||
// <bitfield name="pause_set" range="15..0">
|
||||
// <info>
|
||||
// If the fullness of the CHDR_FIFO in ETH_W words exceeds this value request an ethernet pause. This feature is only
|
||||
// used with 100Gb ethernet
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="pause_clear" range="31..16">
|
||||
// <info>
|
||||
// If the fullness of the CHDR_FIFO in ETH_W words falls bellow this value stop requesting an ethernet pause.
|
||||
// *Pause clear must be less than pause set or terrible things will happen.*
|
||||
// The clearing of the pause request causes the MAC to send a request to resume traffic. This feature is only
|
||||
// used with 100Gb ethernet
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
// </group>
|
||||
//</regmap>
|
||||
|
||||
//<regmap name="QSFP_REGMAP" markdown="true" generateverilog="false">
|
||||
// <group name="QSFP_WINDOWS">
|
||||
// <info>
|
||||
// Register space for a single QSFP Communication port. This currently breaks into 2 possible configurations
|
||||
//
|
||||
// - 1X10GB Ethernet - Using OpenCore XGE MAC
|
||||
// - 1x100GB Ethernet - Using Xilinx CMAC
|
||||
// - (future possible) - Xilinx Aurora (various rates and lane widths)
|
||||
// - (future possible) - 4X10GB Ethernet
|
||||
//
|
||||
// </info>
|
||||
// <window name="ETH_DMA" offset="0x000" size="0x4000" targetregmap="DMA_REGMAP"/>
|
||||
// <window name="NIXGE" offset="0x8000" size="0x2000" targetregmap="NIXGE_REGMAP"/>
|
||||
// <window name="UIO" offset="0xA000" size="0x2000" targetregmap="UIO_REGMAP"/>
|
||||
// <window name="CMAC" offset="0xC000" size="0x2000" targetregmap="CMAC_REGMAP"/>
|
||||
// </group>
|
||||
//</regmap>
|
||||
|
||||
|
||||
//<regmap name="AXI_HPM0_REGMAP" markdown="true" generateverilog="false">
|
||||
// <group name="UHD_ONLY">
|
||||
// <info>
|
||||
// - 0_0 indicates QSFP0 - Lane0 or a 4 LANE QSFP0
|
||||
// - 0_1 indicates QSFP0 - Lane1
|
||||
// - 0_2 indicates QSFP0 - Lane2
|
||||
// - 0_3 indicates QSFP0 - Lane3
|
||||
// - 1_0 indicates QSFP1 - Lane0 or a 4 LANE QSFP1
|
||||
// - 1_1 indicates QSFP1 - Lane1
|
||||
// - 1_2 indicates QSFP1 - Lane2
|
||||
// - 1_3 indicates QSFP1 - Lane3
|
||||
// </info>
|
||||
// <window name="QSFP_0_0" offset="0x1200000000" size="0x10000" targetregmap="QSFP_REGMAP"/>
|
||||
// <window name="QSFP_0_1" offset="0x1200010000" size="0x10000" targetregmap="QSFP_REGMAP"/>
|
||||
// <window name="QSFP_0_2" offset="0x1200020000" size="0x10000" targetregmap="QSFP_REGMAP"/>
|
||||
// <window name="QSFP_0_3" offset="0x1200030000" size="0x10000" targetregmap="QSFP_REGMAP"/>
|
||||
// <window name="QSFP_1_0" offset="0x1200040000" size="0x10000" targetregmap="QSFP_REGMAP"/>
|
||||
// <window name="QSFP_1_1" offset="0x1200050000" size="0x10000" targetregmap="QSFP_REGMAP"/>
|
||||
// <window name="QSFP_1_2" offset="0x1200060000" size="0x10000" targetregmap="QSFP_REGMAP"/>
|
||||
// <window name="QSFP_1_3" offset="0x1200070000" size="0x10000" targetregmap="QSFP_REGMAP"/>
|
||||
// </group>
|
||||
//</regmap>
|
||||
//XmlParse xml_off
|
||||
@@ -0,0 +1,56 @@
|
||||
#
|
||||
# Copyright 2022 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
||||
|
||||
include $(TOOLS_DIR)/make/viv_ip_builder.mak
|
||||
|
||||
IP_X4XX_PS_RFDC_ORIG_SRCS = $(addprefix $(IP_DIR)/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/, \
|
||||
x440_ps_rfdc_bd.tcl \
|
||||
)
|
||||
|
||||
IP_X4XX_PS_RFDC_HDL_SRCS = $(addprefix $(BASE_DIR)/x400/rf/common/, \
|
||||
capture_sysref.v \
|
||||
rf_nco_reset.vhd \
|
||||
rf_reset.vhd \
|
||||
sync_wrapper.v \
|
||||
axis_mux.vhd \
|
||||
gpio_to_axis_mux.vhd \
|
||||
) \
|
||||
$(addprefix $(BASE_DIR)/x400/rf/x440/, \
|
||||
x440_clock_gates.vhd \
|
||||
x440_rf_reset_controller.vhd \
|
||||
x440_rfdc_tx_control_remap.v \
|
||||
) \
|
||||
$(addprefix $(BASE_DIR)/../lib/control/, \
|
||||
synchronizer.v \
|
||||
synchronizer_impl.v \
|
||||
) \
|
||||
$(addprefix $(BASE_DIR)/x400/regmap/x440/, \
|
||||
PkgRFDC_REGS_REGMAP.vhd \
|
||||
rfdc_mapping_regmap_utils.vh \
|
||||
)
|
||||
|
||||
IP_X4XX_PS_RFDC_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/x440_ps_rfdc_bd/, \
|
||||
x440_ps_rfdc_bd.tcl \
|
||||
)
|
||||
|
||||
IP_X4XX_PS_RFDC_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/x440_ps_rfdc_bd/, \
|
||||
x440_ps_rfdc_bd/x440_ps_rfdc_bd.bd \
|
||||
)
|
||||
|
||||
BD_X4XX_PS_RFDC_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/x440_ps_rfdc_bd/, \
|
||||
x440_ps_rfdc_bd.bd.out \
|
||||
x440_ps_rfdc_bd/x440_ps_rfdc_bd_ooc.xdc \
|
||||
x440_ps_rfdc_bd/synth/x440_ps_rfdc_bd.v \
|
||||
)
|
||||
|
||||
EMPTY_IP_SRCS =
|
||||
|
||||
.INTERMEDIATE: IP_X4XX_PS_RFDC_BD_TRGT
|
||||
$(IP_X4XX_PS_RFDC_BD_SRCS) $(BD_X4XX_PS_RFDC_BD_OUTS) $(IP_X4XX_PS_RFDC_BDTCL_SRCS): IP_X4XX_PS_RFDC_BD_TRGT
|
||||
@:
|
||||
|
||||
IP_X4XX_PS_RFDC_BD_TRGT: $(IP_X4XX_PS_RFDC_ORIG_SRCS)
|
||||
$(call BUILD_VIVADO_BDTCL,x440_ps_rfdc_bd,$(ARCH),$(PART_ID),$(IP_DIR)/x4xx_ps_rfdc_bd,$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi,$(IP_X4XX_PS_RFDC_HDL_SRCS))
|
||||
@@ -0,0 +1,16 @@
|
||||
set script_loc [file normalize [info script]]
|
||||
set script_dir [file dirname $script_loc]
|
||||
|
||||
read_verilog -library work $script_dir/../../../rf/common/capture_sysref.v
|
||||
read_verilog -library work $script_dir/../../../../../lib/control/synchronizer.v
|
||||
read_verilog -library work $script_dir/../../../../../lib/control/synchronizer_impl.v
|
||||
read_verilog -library work $script_dir/../../../rf/common/sync_wrapper.v
|
||||
read_verilog -library work $script_dir/../../../regmap/x440/rfdc_mapping_regmap_utils.vh
|
||||
read_verilog -library work $script_dir/../../../rf/x440/x440_rfdc_tx_control_remap.v
|
||||
read_vhdl -library work $script_dir/../../../rf/common/rf_nco_reset.vhd
|
||||
read_vhdl -library work $script_dir/../../../regmap/x440/PkgRFDC_REGS_REGMAP.vhd
|
||||
read_vhdl -library work $script_dir/../../../rf/x440/x440_rf_reset_controller.vhd
|
||||
read_vhdl -library work $script_dir/../../../rf/common/rf_reset.vhd
|
||||
read_vhdl -library work $script_dir/../../../rf/x440/x440_clock_gates.vhd
|
||||
read_vhdl -library work $script_dir/../../../rf/common/axis_mux.vhd
|
||||
read_vhdl -library work $script_dir/../../../rf/common/gpio_to_axis_mux.vhd
|
||||
@@ -0,0 +1,262 @@
|
||||
//
|
||||
// Copyright 2022 Ettus Research, A National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: x440_rfdc_regs
|
||||
// Description:
|
||||
// Registers definition within the x4xx_ps_rfdc_bd IP.
|
||||
|
||||
//XmlParse xml_on
|
||||
//<top name="X440_FPGA">
|
||||
// <ports>
|
||||
// <info>
|
||||
// This section lists all common Processing System ports through
|
||||
// which the register maps in this project are accessed. Each input
|
||||
// port to the fabric will point to a regmap.
|
||||
// </info>
|
||||
// <port name="ARM_M_AXI_HPM0" targetregmap="AXI_HPM0_REGMAP">
|
||||
// <info>
|
||||
// This is the main AXI4-Lite master interface that the PS
|
||||
// exposes to the kernel to interact with the FPGA fabric.
|
||||
// There are multiple endpoints connected to this interface.
|
||||
// </info>
|
||||
// </port>
|
||||
// <port name="ARM_S_AXI_HPC0" sourcewindow="PL_DMA_MASTER_REGMAP|AXI_HPC0_WINDOW">
|
||||
// <info>
|
||||
// This is one of the two cache-coherent AXI slave ports available to
|
||||
// communicate from the fabric (master) to the PS (slave).
|
||||
// </info>
|
||||
// </port>
|
||||
// <port name="ARM_S_AXI_HPC1" sourcewindow="PL_DMA_MASTER_REGMAP|AXI_HPC1_WINDOW">
|
||||
// <info>
|
||||
// This is one of the two cache-coherent AXI slave ports available to
|
||||
// communicate from the fabric (master) to the PS (slave).
|
||||
// </info>
|
||||
// </port>
|
||||
// <port name="ARM_SPI1_CS3" targetregmap="MB_CPLD_PS_REGMAP">
|
||||
// <info>
|
||||
// This is the SPI1 interface
|
||||
// (see <a href="https://www.xilinx.com/html_docs/registers/ug1087/mod___spi.html" target="_blank">Zynq UltraScale+ Devices Register Reference</a>)
|
||||
// of the PS.
|
||||
// With chip select 3 enabled transactions are targeted for the PS MB CPLD register interface linked here.{br}
|
||||
// The request format on SPI is defined as.{br}
|
||||
// {b}Write request:{/b}
|
||||
// {ul}
|
||||
// {li}1'b1 = write
|
||||
// {li}15 bit address
|
||||
// {li}32 bit data (MOSI)
|
||||
// {li}8 bit processing gap
|
||||
// {li}5 bit padding
|
||||
// {li}1 bit ack
|
||||
// {li}2 bit status
|
||||
// {/ul}
|
||||
// {b}Read request:{/b}
|
||||
// {ul}
|
||||
// {li}1'b0 = read
|
||||
// {li}15 bit address
|
||||
// {li}8 bit processing gap
|
||||
// {li}32 bit data (MISO)
|
||||
// {li}5 bit padding
|
||||
// {li}1 bit ack
|
||||
// {li}2 bit status
|
||||
// {/ul}
|
||||
// </info>
|
||||
// </port>
|
||||
// </ports>
|
||||
// <regmapcfg readablestrobes="false">
|
||||
// <map name="AXI_HPM0_REGMAP"/>
|
||||
// <map name="MB_CPLD_PS_REGMAP"/>
|
||||
// </regmapcfg>
|
||||
//</top>
|
||||
//
|
||||
//<regmap name="RFDC_REGS_REGMAP" readablestrobes="false" generatevhdl="true" generateverilog="true" ettusguidelines="true">
|
||||
// <group name="RFDC_REGS">
|
||||
// <info>
|
||||
// These are the registers located within the RFDC block design
|
||||
// that provide control and status support for the RF chain.
|
||||
// </info>
|
||||
//
|
||||
// <window name="MMCM" offset="0x0" size="0x10000">
|
||||
// <info>
|
||||
// Register space for controlling the data clock MMCM instance
|
||||
// within the RFDC block design.
|
||||
// Refer to Xilinx' Clocking Wizard v6.0 Product Guide for the
|
||||
// regiter space description in chapter 2.
|
||||
// (https://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v6_0/pg065-clk-wiz.pdf)
|
||||
// </info>
|
||||
// </window>
|
||||
//
|
||||
// <register name="INVERT_DB0_IQ_REG" offset="0x10000" size="32">
|
||||
// <info>Control register for inverting I/Q data.</info>
|
||||
// <bitfield name="INVERT_DB0_ADC0_IQ" range="0"/>
|
||||
// <bitfield name="INVERT_DB0_ADC1_IQ" range="1"/>
|
||||
// <bitfield name="INVERT_DB0_ADC2_IQ" range="2"/>
|
||||
// <bitfield name="INVERT_DB0_ADC3_IQ" range="3"/>
|
||||
// <bitfield name="INVERT_DB0_DAC0_IQ" range="8"/>
|
||||
// <bitfield name="INVERT_DB0_DAC1_IQ" range="9"/>
|
||||
// <bitfield name="INVERT_DB0_DAC2_IQ" range="10"/>
|
||||
// <bitfield name="INVERT_DB0_DAC3_IQ" range="11"/>
|
||||
// </register>
|
||||
//
|
||||
// <register name="INVERT_DB1_IQ_REG" offset="0x10800" size="32">
|
||||
// <info>Control register for inverting I/Q data.</info>
|
||||
// <bitfield name="INVERT_DB1_ADC0_IQ" range="0"/>
|
||||
// <bitfield name="INVERT_DB1_ADC1_IQ" range="1"/>
|
||||
// <bitfield name="INVERT_DB1_ADC2_IQ" range="2"/>
|
||||
// <bitfield name="INVERT_DB1_ADC3_IQ" range="3"/>
|
||||
// <bitfield name="INVERT_DB1_DAC0_IQ" range="8"/>
|
||||
// <bitfield name="INVERT_DB1_DAC1_IQ" range="9"/>
|
||||
// <bitfield name="INVERT_DB1_DAC2_IQ" range="10"/>
|
||||
// <bitfield name="INVERT_DB1_DAC3_IQ" range="11"/>
|
||||
// </register>
|
||||
//
|
||||
// <register name="MMCM_RESET_REG" offset="0x11000" size="32">
|
||||
// <info>Control register for resetting the data clock MMCM.</info>
|
||||
// <bitfield name="RESET_MMCM" range="0">
|
||||
// <info>
|
||||
// Write a '1' to this bit to reset the MMCM. Then write a
|
||||
// '0' to place the MMCM out of reset.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="RF0_RESET_CONTROL_REG" offset="0x12000" typename="RF_RESET_CONTROL_REGTYPE"/>
|
||||
// <register name="RF0_RESET_STATUS_REG" offset="0x12008" typename="RF_RESET_STATUS_REGTYPE"/>
|
||||
// <register name="RF1_RESET_CONTROL_REG" offset="0x12800" typename="RF_RESET_CONTROL_REGTYPE"/>
|
||||
// <register name="RF1_RESET_STATUS_REG" offset="0x12808" typename="RF_RESET_STATUS_REGTYPE"/>
|
||||
//
|
||||
// <register name="RF_AXI_STATUS_REG" offset="0x13000" typename="RF_AXI_STATUS_REGTYPE"/>
|
||||
//
|
||||
// <register name="CALIBRATION_DATA" offset="0x014000">
|
||||
// <info>
|
||||
// The fields of this register provide data to all the DAC channels when enabled
|
||||
// by the CALIBRATION_ENABLE register.
|
||||
// </info>
|
||||
// <bitfield name="Q_DATA" range="31..16">
|
||||
// </bitfield>
|
||||
// <bitfield name="I_DATA" range="15..00">
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="CALIBRATION_ENABLE" offset="0x014008">
|
||||
// <info>
|
||||
// This register enables calibration data in the DAC data path for each of the
|
||||
// four channels. Each of these bits is normally '0'. When written '1', DAC data
|
||||
// for the corresponding channel will be constantly driven with the contents of
|
||||
// the CALIBRATION_DATA register.
|
||||
// </info>
|
||||
// <bitfield name="ENABLE_CALIBRATION_DATA_0" range="0">
|
||||
// <info>
|
||||
// Enables calibration data for channel #0/0.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="ENABLE_CALIBRATION_DATA_1" range="1">
|
||||
// <info>
|
||||
// Enables calibration data for channel #0/1.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="ENABLE_CALIBRATION_DATA_2" range="2">
|
||||
// <info>
|
||||
// Enables calibration data for channel #0/2.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="ENABLE_CALIBRATION_DATA_3" range="3">
|
||||
// <info>
|
||||
// Enables calibration data for channel #0/3.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="ENABLE_CALIBRATION_DATA_4" range="4">
|
||||
// <info>
|
||||
// Enables calibration data for channel #1/0.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="ENABLE_CALIBRATION_DATA_5" range="5">
|
||||
// <info>
|
||||
// Enables calibration data for channel #1/1.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="ENABLE_CALIBRATION_DATA_6" range="6">
|
||||
// <info>
|
||||
// Enables calibration data for channel #1/2.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="ENABLE_CALIBRATION_DATA_7" range="7">
|
||||
// <info>
|
||||
// Enables calibration data for channel #1/3.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="RF_PLL_CONTROL_REG" offset="0x16000" size="32" writable="true">
|
||||
// <info>
|
||||
// Enable RF MMCM outputs.
|
||||
// </info>
|
||||
// <bitfield name="ENABLE_RF0_CLK" range="8"/>
|
||||
// <bitfield name="ENABLE_RF0_CLK_2X" range="12"/>
|
||||
// <bitfield name="CLEAR_DATA_CLK_UNLOCKED" range="16"/>
|
||||
// <bitfield name="ENABLE_RF1_CLK" range="20"/>
|
||||
// <bitfield name="ENABLE_RF1_CLK_2X" range="24"/>
|
||||
// </register>
|
||||
//
|
||||
// <register name="RF_PLL_STATUS_REG" offset="0x16008" size="32" writable="false">
|
||||
// <info>
|
||||
// Data Clk Pll Status Register
|
||||
// </info>
|
||||
// <bitfield name="DATA_CLK_PLL_UNLOCKED_STICKY" range="16"/>
|
||||
// <bitfield name="DATA_CLK_PLL_LOCKED" range="20"/>
|
||||
// </register>
|
||||
//
|
||||
// <register name="THRESHOLD_STATUS" offset="0x015000">
|
||||
// <info>
|
||||
// This register shows threshold status for the ADCs. Each bit reflects the
|
||||
// RFDC's real-time ADC status signals, which will assert when the ADC input
|
||||
// signal exceeds the programmed threshold value. The status will remain
|
||||
// asserted until cleared by software.
|
||||
// The bitfield names follow the pattern ADCX_ZZ_over_threshold(1|2), where X is
|
||||
// the location of the tile in the converter column and ZZ is either 01 (the
|
||||
// lower RF-ADC in the tile) or 23 (the upper RF-ADC in the tile).
|
||||
// See also the Xilinx document PG269.
|
||||
// </info>
|
||||
// <bitfield name="ADC0_01_THRESHOLD1" range="0">
|
||||
// </bitfield>
|
||||
// <bitfield name="ADC0_01_THRESHOLD2" range="1">
|
||||
// </bitfield>
|
||||
// <bitfield name="ADC0_23_THRESHOLD1" range="2">
|
||||
// </bitfield>
|
||||
// <bitfield name="ADC0_23_THRESHOLD2" range="3">
|
||||
// </bitfield>
|
||||
// <bitfield name="ADC1_01_THRESHOLD1" range="4">
|
||||
// </bitfield>
|
||||
// <bitfield name="ADC1_01_THRESHOLD2" range="5">
|
||||
// </bitfield>
|
||||
// <bitfield name="ADC1_23_THRESHOLD1" range="6">
|
||||
// </bitfield>
|
||||
// <bitfield name="ADC1_23_THRESHOLD2" range="7">
|
||||
// </bitfield>
|
||||
// <bitfield name="ADC2_01_THRESHOLD1" range="8">
|
||||
// </bitfield>
|
||||
// <bitfield name="ADC2_01_THRESHOLD2" range="9">
|
||||
// </bitfield>
|
||||
// <bitfield name="ADC2_23_THRESHOLD1" range="10">
|
||||
// </bitfield>
|
||||
// <bitfield name="ADC2_23_THRESHOLD2" range="11">
|
||||
// </bitfield>
|
||||
// <bitfield name="ADC3_01_THRESHOLD1" range="12">
|
||||
// </bitfield>
|
||||
// <bitfield name="ADC3_01_THRESHOLD2" range="13">
|
||||
// </bitfield>
|
||||
// <bitfield name="ADC3_23_THRESHOLD1" range="14">
|
||||
// </bitfield>
|
||||
// <bitfield name="ADC3_23_THRESHOLD2" range="15">
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="FABRIC_DSP_REG" offset="0x13008" typename="FABRIC_DSP_REGTYPE"/>
|
||||
// <register name="ADC_TILEMAP_REG" offset="0x17000" typename="ADC_TILEMAP_REGTYPE"/>
|
||||
// <register name="DAC_TILEMAP_REG" offset="0x17008" typename="DAC_TILEMAP_REGTYPE"/>
|
||||
// <register name="RFDC_INFO_REG" offset="0x18000" typename="RFDC_INFO_REGTYPE"/>
|
||||
//
|
||||
// </group>
|
||||
//</regmap>
|
||||
//XmlParse xml_off
|
||||
+98
-32
@@ -1,9 +1,9 @@
|
||||
------------------------------------------------------------------------------------------
|
||||
--
|
||||
-- File: x4xx_ps_rfdc_bd.vhd
|
||||
-- File: x440_ps_rfdc_bd.vhd
|
||||
-- Author: niBlockDesign::niBdExportStub
|
||||
-- Original Project: HwBuildTools
|
||||
-- Date: 27 September 2021
|
||||
-- Date: 06 September 2022
|
||||
--
|
||||
------------------------------------------------------------------------------------------
|
||||
-- (c) Copyright National Instruments Corporation
|
||||
@@ -12,7 +12,7 @@
|
||||
------------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Purpose: This is an automatically generated stub file to match the entity
|
||||
-- declaration for 'x4xx_ps_rfdc_bd'. This file was created using niBdExportStub
|
||||
-- declaration for 'x440_ps_rfdc_bd'. This file was created using niBdExportStub
|
||||
-- Do not modify this file directly!
|
||||
--
|
||||
------------------------------------------------------------------------------------------
|
||||
@@ -22,37 +22,44 @@ use ieee.std_logic_1164.all;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
entity x4xx_ps_rfdc_bd is
|
||||
entity x440_ps_rfdc_bd is
|
||||
port (
|
||||
adc_data_out_resetn_dclk : out STD_LOGIC;
|
||||
adc_enable_data_rclk : out STD_LOGIC;
|
||||
adc_reset_pulse_dclk : in STD_LOGIC;
|
||||
adc_rfdc_axi_resetn_rclk : out STD_LOGIC;
|
||||
adc_enable_data_r0clk : out STD_LOGIC;
|
||||
adc_enable_data_r1clk : out STD_LOGIC;
|
||||
adc_reset_pulse_r0clk : in STD_LOGIC;
|
||||
adc_reset_pulse_r1clk : in STD_LOGIC;
|
||||
adc_resetn_r0clk2x : out STD_LOGIC;
|
||||
adc_resetn_r1clk2x : out STD_LOGIC;
|
||||
adc_rfdc_axi_resetn_r0clk : out STD_LOGIC;
|
||||
adc_rfdc_axi_resetn_r1clk : out STD_LOGIC;
|
||||
bus_clk : in STD_LOGIC;
|
||||
bus_rstn : in STD_LOGIC;
|
||||
clk40 : in STD_LOGIC;
|
||||
clk40_rstn : in STD_LOGIC;
|
||||
dac_data_in_resetn_dclk : out STD_LOGIC;
|
||||
dac_data_in_resetn_dclk2x : out STD_LOGIC;
|
||||
dac_data_in_resetn_rclk : out STD_LOGIC;
|
||||
dac_data_in_resetn_rclk2x : out STD_LOGIC;
|
||||
dac_reset_pulse_dclk : in STD_LOGIC;
|
||||
data_clk : out STD_LOGIC;
|
||||
data_clk_2x : out STD_LOGIC;
|
||||
dac_data_in_resetn_r0clk : out STD_LOGIC;
|
||||
dac_data_in_resetn_r0clk2x : out STD_LOGIC;
|
||||
dac_data_in_resetn_r1clk : out STD_LOGIC;
|
||||
dac_data_in_resetn_r1clk2x : out STD_LOGIC;
|
||||
dac_reset_pulse_r0clk : in STD_LOGIC;
|
||||
dac_reset_pulse_r1clk : in STD_LOGIC;
|
||||
data_clock_locked : out STD_LOGIC;
|
||||
enable_gated_clocks_clk40 : in STD_LOGIC;
|
||||
enable_sysref_rclk : in STD_LOGIC;
|
||||
fir_resetn_rclk2x : out STD_LOGIC;
|
||||
enable_sysref_r0clk : in STD_LOGIC;
|
||||
enable_sysref_r1clk : in STD_LOGIC;
|
||||
gated_base_clks_valid_clk40 : out STD_LOGIC;
|
||||
invert_adc_iq_rclk2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
invert_dac_iq_rclk2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
invert_adc_iq_r0clk2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
invert_adc_iq_r1clk2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
invert_dac_iq_r0clk2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
invert_dac_iq_r1clk2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
irq0_lpd_rpu_n : in STD_LOGIC;
|
||||
irq1_lpd_rpu_n : in STD_LOGIC;
|
||||
jtag0_tck : inout STD_LOGIC;
|
||||
jtag0_tdi : inout STD_LOGIC;
|
||||
jtag0_tdo : in STD_LOGIC;
|
||||
jtag0_tms : inout STD_LOGIC;
|
||||
nco_reset_done_dclk : out STD_LOGIC;
|
||||
nco_reset_done_r0clk : out STD_LOGIC;
|
||||
nco_reset_done_r1clk : out STD_LOGIC;
|
||||
pl_clk40 : out STD_LOGIC;
|
||||
pl_clk100 : out STD_LOGIC;
|
||||
pl_clk166 : out STD_LOGIC;
|
||||
@@ -65,15 +72,18 @@ port (
|
||||
pl_resetn3 : out STD_LOGIC;
|
||||
pll_ref_clk_in : in STD_LOGIC;
|
||||
pll_ref_clk_out : out STD_LOGIC;
|
||||
radio0_rfdc_clk : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
radio0_rfdc_clk_2x : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
radio1_rfdc_clk : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
radio1_rfdc_clk_2x : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
rf_axi_status_clk40 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
rf_dsp_info_clk40 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
rfdc_clk : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
rfdc_clk_2x : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
rfdc_irq : out STD_LOGIC;
|
||||
s_axi_hp0_aclk : in STD_LOGIC;
|
||||
s_axi_hp1_aclk : in STD_LOGIC;
|
||||
s_axi_hpc0_aclk : in STD_LOGIC;
|
||||
start_nco_reset_dclk : in STD_LOGIC;
|
||||
start_nco_reset_r0clk : in STD_LOGIC;
|
||||
start_nco_reset_r1clk : in STD_LOGIC;
|
||||
sysref_out_pclk : out STD_LOGIC;
|
||||
sysref_out_rclk : out STD_LOGIC;
|
||||
sysref_pl_in : in STD_LOGIC;
|
||||
@@ -201,8 +211,20 @@ port (
|
||||
s_axi_hpc0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
adc0_clk_clk_n : in STD_LOGIC;
|
||||
adc0_clk_clk_p : in STD_LOGIC;
|
||||
adc1_clk_clk_n : in STD_LOGIC;
|
||||
adc1_clk_clk_p : in STD_LOGIC;
|
||||
adc2_clk_clk_n : in STD_LOGIC;
|
||||
adc2_clk_clk_p : in STD_LOGIC;
|
||||
adc3_clk_clk_n : in STD_LOGIC;
|
||||
adc3_clk_clk_p : in STD_LOGIC;
|
||||
adc_tile225_ch0_vin_v_n : in STD_LOGIC;
|
||||
adc_tile225_ch0_vin_v_p : in STD_LOGIC;
|
||||
adc_tile225_ch1_vin_v_n : in STD_LOGIC;
|
||||
adc_tile225_ch1_vin_v_p : in STD_LOGIC;
|
||||
adc_tile227_ch0_vin_v_n : in STD_LOGIC;
|
||||
adc_tile227_ch0_vin_v_p : in STD_LOGIC;
|
||||
adc_tile227_ch1_vin_v_n : in STD_LOGIC;
|
||||
adc_tile227_ch1_vin_v_p : in STD_LOGIC;
|
||||
m_axi_app_awaddr : out STD_LOGIC_VECTOR ( 39 downto 0 );
|
||||
m_axi_app_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axi_app_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
@@ -226,6 +248,18 @@ port (
|
||||
dac0_clk_clk_p : in STD_LOGIC;
|
||||
dac1_clk_clk_n : in STD_LOGIC;
|
||||
dac1_clk_clk_p : in STD_LOGIC;
|
||||
dac_tile228_ch2_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
|
||||
dac_tile228_ch2_din_tvalid : in STD_LOGIC;
|
||||
dac_tile228_ch2_din_tready : out STD_LOGIC;
|
||||
dac_tile228_ch3_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
|
||||
dac_tile228_ch3_din_tvalid : in STD_LOGIC;
|
||||
dac_tile228_ch3_din_tready : out STD_LOGIC;
|
||||
dac_tile229_ch2_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
|
||||
dac_tile229_ch2_din_tvalid : in STD_LOGIC;
|
||||
dac_tile229_ch2_din_tready : out STD_LOGIC;
|
||||
dac_tile229_ch3_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
|
||||
dac_tile229_ch3_din_tvalid : in STD_LOGIC;
|
||||
dac_tile229_ch3_din_tready : out STD_LOGIC;
|
||||
gpio_0_tri_i : in STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
gpio_0_tri_o : out STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
gpio_0_tri_t : out STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
@@ -310,6 +344,14 @@ port (
|
||||
m_axi_mpm_ep_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_mpm_ep_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
m_axi_mpm_ep_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
dac_tile228_ch0_vout_v_n : out STD_LOGIC;
|
||||
dac_tile228_ch0_vout_v_p : out STD_LOGIC;
|
||||
dac_tile228_ch1_vout_v_n : out STD_LOGIC;
|
||||
dac_tile228_ch1_vout_v_p : out STD_LOGIC;
|
||||
dac_tile229_ch0_vout_v_n : out STD_LOGIC;
|
||||
dac_tile229_ch0_vout_v_p : out STD_LOGIC;
|
||||
dac_tile229_ch1_vout_v_n : out STD_LOGIC;
|
||||
dac_tile229_ch1_vout_v_p : out STD_LOGIC;
|
||||
adc_tile224_ch0_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
|
||||
adc_tile224_ch0_dout_i_tready : in STD_LOGIC;
|
||||
adc_tile224_ch0_dout_i_tvalid : out STD_LOGIC;
|
||||
@@ -322,6 +364,18 @@ port (
|
||||
adc_tile224_ch1_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
|
||||
adc_tile224_ch1_dout_q_tready : in STD_LOGIC;
|
||||
adc_tile224_ch1_dout_q_tvalid : out STD_LOGIC;
|
||||
adc_tile225_ch0_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
|
||||
adc_tile225_ch0_dout_i_tready : in STD_LOGIC;
|
||||
adc_tile225_ch0_dout_i_tvalid : out STD_LOGIC;
|
||||
adc_tile225_ch0_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
|
||||
adc_tile225_ch0_dout_q_tready : in STD_LOGIC;
|
||||
adc_tile225_ch0_dout_q_tvalid : out STD_LOGIC;
|
||||
adc_tile225_ch1_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
|
||||
adc_tile225_ch1_dout_i_tready : in STD_LOGIC;
|
||||
adc_tile225_ch1_dout_i_tvalid : out STD_LOGIC;
|
||||
adc_tile225_ch1_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
|
||||
adc_tile225_ch1_dout_q_tready : in STD_LOGIC;
|
||||
adc_tile225_ch1_dout_q_tvalid : out STD_LOGIC;
|
||||
adc_tile226_ch0_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
|
||||
adc_tile226_ch0_dout_i_tready : in STD_LOGIC;
|
||||
adc_tile226_ch0_dout_i_tvalid : out STD_LOGIC;
|
||||
@@ -334,14 +388,26 @@ port (
|
||||
adc_tile226_ch1_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
|
||||
adc_tile226_ch1_dout_q_tready : in STD_LOGIC;
|
||||
adc_tile226_ch1_dout_q_tvalid : out STD_LOGIC;
|
||||
dac_tile228_ch0_vout_v_n : out STD_LOGIC;
|
||||
dac_tile228_ch0_vout_v_p : out STD_LOGIC;
|
||||
dac_tile228_ch1_vout_v_n : out STD_LOGIC;
|
||||
dac_tile228_ch1_vout_v_p : out STD_LOGIC;
|
||||
dac_tile229_ch0_vout_v_n : out STD_LOGIC;
|
||||
dac_tile229_ch0_vout_v_p : out STD_LOGIC;
|
||||
dac_tile229_ch1_vout_v_n : out STD_LOGIC;
|
||||
dac_tile229_ch1_vout_v_p : out STD_LOGIC;
|
||||
adc_tile227_ch0_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
|
||||
adc_tile227_ch0_dout_i_tready : in STD_LOGIC;
|
||||
adc_tile227_ch0_dout_i_tvalid : out STD_LOGIC;
|
||||
adc_tile227_ch0_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
|
||||
adc_tile227_ch0_dout_q_tready : in STD_LOGIC;
|
||||
adc_tile227_ch0_dout_q_tvalid : out STD_LOGIC;
|
||||
adc_tile227_ch1_dout_i_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
|
||||
adc_tile227_ch1_dout_i_tready : in STD_LOGIC;
|
||||
adc_tile227_ch1_dout_i_tvalid : out STD_LOGIC;
|
||||
adc_tile227_ch1_dout_q_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
|
||||
adc_tile227_ch1_dout_q_tready : in STD_LOGIC;
|
||||
adc_tile227_ch1_dout_q_tvalid : out STD_LOGIC;
|
||||
dac_tile228_ch2_vout_v_n : out STD_LOGIC;
|
||||
dac_tile228_ch2_vout_v_p : out STD_LOGIC;
|
||||
dac_tile228_ch3_vout_v_n : out STD_LOGIC;
|
||||
dac_tile228_ch3_vout_v_p : out STD_LOGIC;
|
||||
dac_tile229_ch2_vout_v_n : out STD_LOGIC;
|
||||
dac_tile229_ch2_vout_v_p : out STD_LOGIC;
|
||||
dac_tile229_ch3_vout_v_n : out STD_LOGIC;
|
||||
dac_tile229_ch3_vout_v_p : out STD_LOGIC;
|
||||
dac_tile228_ch0_din_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
|
||||
dac_tile228_ch0_din_tvalid : in STD_LOGIC;
|
||||
dac_tile228_ch0_din_tready : out STD_LOGIC;
|
||||
@@ -404,8 +470,8 @@ port (
|
||||
s_axi_hpc1_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_hpc1_awuser : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
end entity x4xx_ps_rfdc_bd;
|
||||
end entity x440_ps_rfdc_bd;
|
||||
|
||||
architecture stub of x4xx_ps_rfdc_bd is
|
||||
architecture stub of x440_ps_rfdc_bd is
|
||||
begin
|
||||
end architecture stub;
|
||||
+746
-257
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user