fpga: Add X440/FBX support
Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
This commit is contained in:
Javier Valenzuela
committed by
Aki Tomita
Aki Tomita
co-authored by
Martin Braun
Wade Fife
Ryan Marlow
Martin Braun
Wade Fife
Ryan Marlow
parent
a405111ce7
commit
5cadf901c7
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#
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# Copyright 2022 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir.
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BASE_DIR = ../../../../..
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# Include viv_sim_preample after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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# Define part using PART_ID (<device>/<package>/<speedgrade>)
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ARCH = zynquplusRFSOC
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PART_ID = xczu28dr/ffvg1517/-1/e
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# Include makefiles and sources for the DUT and its dependencies
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include $(BASE_DIR)/../lib/control/Makefile.srcs
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include $(BASE_DIR)/../lib/wishbone/Makefile.srcs
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DESIGN_SRCS += $(abspath \
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$(FIFO_SRCS) \
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$(AXI_SRCS) \
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$(CONTROL_LIB_SRCS) \
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$(WISHBONE_SRCS) \
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)
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DESIGN_SRCS += $(abspath \
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../../regmap/fbx_ctrl_regmap_utils.vh \
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../../regmap/rf_sync_regmap_utils.vh \
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../../ctrlport_to_i2c_sync_ctrl.v \
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)
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#-------------------------------------------------
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# IP Specific
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#-------------------------------------------------
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# If simulation contains IP, define the IP_DIR and point
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# it to the base level IP directory
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IP_DIR = $(BASE_DIR)/x400/ip
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LIB_IP_DIR = $(BASE_DIR)/../lib/ip
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# Include makefiles and sources for all IP components
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# *after* defining the IP_DIR
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#
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# These TBs don't use any IP yet :)
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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include $(BASE_DIR)/../sim/general/Makefile.srcs
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# Define only one top-level module
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SIM_TOP = ctrlport_to_i2c_sync_ctrl_tb
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# Simulation runtime in microseconds
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SIM_RUNTIME_US = 200000
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SIM_SRCS = \
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$(abspath ctrlport_to_i2c_sync_ctrl_tb.sv) \
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$(abspath $(BASE_DIR)/../lib/sim/wishbone/i2c/i2c_slave_model.v) \
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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@@ -0,0 +1,204 @@
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//
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// Copyright 2022 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_to_i2c_sync_ctrl_tb
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//
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// Description:
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// testbench for ctrlport_to_i2c_sync_ctrl module. Tasks defined for ctrlport write and
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// read transactions. Tests ability to write to SYNC/RFS_EN regs and then
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// initialize i2c_master and i2c peripheral and then configure io through the
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// i2c interface to the io expander.
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//
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`timescale 1ns / 1ps
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`define NS_PER_TICK 1
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`define NUM_TEST_CASES 5
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`include "sim_exec_report.vh"
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`include "sim_clks_rsts.vh"
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`define SIM_TIMEOUT_US 200000 //overwrite this def from sim_exec_report.vh
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module ctrlport_to_i2c_sync_ctrl_tb();
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import PkgRandom::*;
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`TEST_BENCH_INIT("ctrlport_to_i2c_sync_ctrl_tb", `NUM_TEST_CASES, `NS_PER_TICK);
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//sets up clock
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localparam CLK_PERIOD = $ceil(1e9/50.0e6);
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`DEFINE_CLK(clk50, CLK_PERIOD, 50);
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reg reset_clk50;
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reg s_ctrlport_req_wr;
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reg s_ctrlport_req_rd;
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reg [19:0] s_ctrlport_req_addr;
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reg [31:0] s_ctrlport_req_data;
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// Response
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wire s_ctrlport_resp_ack;
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wire [ 1:0] s_ctrlport_resp_status;
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wire [31:0] s_ctrlport_resp_data;
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wire i2c_scl_i, i2c_scl_o, i2c_scl_en_o;
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wire i2c_sda_i, i2c_sda_o, i2c_sda_en_o;
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PkgRandom::Rand #(3) rand_sync;
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PkgRandom::Rand #(1) rand_rfs_en;
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reg [2:0] sync1, sync2, sync3, sync4, sync5;
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reg rfs_en;
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`include "../../regmap/rf_sync_regmap_utils.vh"
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task cp_write;
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input [19:0] a;
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input [31:0] d;
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begin
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s_ctrlport_req_addr = a;
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s_ctrlport_req_data = d;
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@(posedge clk50);
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s_ctrlport_req_wr = 1;
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@(posedge clk50);
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while(~s_ctrlport_resp_ack) @(posedge clk50);
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s_ctrlport_req_wr = 0;
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@(posedge clk50);
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end
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endtask
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task cp_read;
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input [19:0] a;
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input [31:0] d;
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input debug;
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begin
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s_ctrlport_req_addr = a;
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s_ctrlport_req_rd = 1;
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@(posedge clk50);
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while(~s_ctrlport_resp_ack) @(posedge clk50);
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s_ctrlport_req_rd = 0;
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@(posedge clk50);
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if(debug) begin
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$display("status: read addr %h at %t value = %h", a, $time, s_ctrlport_resp_data);
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end
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`ASSERT_ERROR( s_ctrlport_resp_data == d, "CtrlPort read returned unexpected value.");
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end
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endtask
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task cp_poll;
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input [19:0] a;
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input [31:0] d;
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input debug;
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begin
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s_ctrlport_req_addr = a;
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s_ctrlport_req_rd = 1;
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@(posedge clk50);
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while(~s_ctrlport_resp_ack) @(posedge clk50);
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s_ctrlport_req_rd = 0;
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@(posedge clk50);
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while(s_ctrlport_resp_data != d && s_ctrlport_req_addr == a) begin
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s_ctrlport_req_addr = a;
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s_ctrlport_req_rd = 1;
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@(posedge clk50);
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while(~s_ctrlport_resp_ack) @(posedge clk50);
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s_ctrlport_req_rd = 0;
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@(posedge clk50);
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end
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if(debug) begin
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$display("status: read addr %h at %t value = %h", a, $time, s_ctrlport_resp_data);
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end
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end
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endtask
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ctrlport_to_i2c_sync_ctrl #(
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.BASE_ADDRESS(0)
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) ctrlport_to_i2c_inst (
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.ctrlport_clk (clk50),
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.ctrlport_rst (reset_clk50),
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.s_ctrlport_req_wr (s_ctrlport_req_wr),
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.s_ctrlport_req_rd (s_ctrlport_req_rd),
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.s_ctrlport_req_addr (s_ctrlport_req_addr),
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.s_ctrlport_req_data (s_ctrlport_req_data),
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.s_ctrlport_resp_ack (s_ctrlport_resp_ack),
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.s_ctrlport_resp_status (s_ctrlport_resp_status),
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.s_ctrlport_resp_data (s_ctrlport_resp_data),
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.scl_pad_i (i2c_scl_i),
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.scl_pad_o (i2c_scl_o),
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.scl_pad_en_o (i2c_scl_en_o),
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.sda_pad_i (i2c_sda_i),
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.sda_pad_o (i2c_sda_o),
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.sda_pad_en_o (i2c_sda_en_o)
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);
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// hookup i2c slave model
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i2c_slave_model #(
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ctrlport_to_i2c_inst.SYNC_IO_SLV_ADR
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) i2c_slave (
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.scl(i2c_scl_i),
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.sda(i2c_sda_i)
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);
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// create i2c lines
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delay m0_scl (i2c_scl_en_o ? 1'bz : i2c_scl_o, i2c_scl_i),
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m0_sda (i2c_sda_en_o ? 1'bz : i2c_sda_o, i2c_sda_i);
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pullup p1(i2c_scl_i); // pullup scl line
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pullup p2(i2c_sda_i); // pullup sda line
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initial begin : tb_main
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`TEST_CASE_START("initialize UUT");
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clk50 = 0;
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reset_clk50 = 1;
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s_ctrlport_req_wr = 0;
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s_ctrlport_req_rd = 0;
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s_ctrlport_req_addr = 0;
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s_ctrlport_req_data = 0;
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#100
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reset_clk50 = 0;
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$display("status: %t done reset here", $time);
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`TEST_CASE_DONE(~reset_clk50);
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// trigger setup
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`TEST_CASE_START("Initialize core and I2C peripheral");
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cp_write(SETUP_REG, 1);
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cp_poll(SETUP_STATUS_REG,1,1);
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`TEST_CASE_DONE(i2c_slave.mem[7] == 0 & i2c_slave.mem[6] == 0);
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$display("status: %t SETUP DONE", $time);
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// configure SYNC and RFS_EN Regs
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for (int i=0; i<3; i=i+1) begin
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`TEST_CASE_START("configure SYNC and RFS_EN Regs loop");
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$display("loop # %d", i);
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sync1 = rand_sync.rand_bit();
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sync2 = rand_sync.rand_bit();
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sync3 = rand_sync.rand_bit();
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sync4 = rand_sync.rand_bit();
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sync5 = rand_sync.rand_bit();
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rfs_en = rand_rfs_en.rand_bit();
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cp_write(SYNC_1_REG, sync1);
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cp_write(SYNC_2_REG, sync2);
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cp_write(SYNC_3_REG, sync3);
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cp_write(SYNC_4_REG, sync4);
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cp_write(SYNC_5_REG, sync5);
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cp_write(RFS_EN_REG, rfs_en);
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cp_read(SYNC_1_REG, {28'b0, sync1}, 1);
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cp_read(SYNC_2_REG, {28'b0, sync2}, 1);
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cp_read(SYNC_3_REG, {28'b0, sync3}, 1);
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cp_read(SYNC_4_REG, {28'b0, sync4}, 1);
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cp_read(SYNC_5_REG, {28'b0, sync5}, 1);
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cp_read(RFS_EN_REG, {31'b0, rfs_en}, 1);
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$display("status: %t Configured ControlPort regs, now configure I2C peripheral.", $time);
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cp_write(CONFIG_IO_REG, 1);
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cp_poll(CONFIG_IO_STATUS_REG,32'h1,1);
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`TEST_CASE_DONE(i2c_slave.mem[2] == {sync3[1:0], sync2, sync1} &
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i2c_slave.mem[3] == {rfs_en, sync5, sync4, sync3[2]});
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end
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`TEST_BENCH_DONE;
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end
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endmodule
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module delay (in, out);
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input in;
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output out;
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assign out = in;
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specify
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(in => out) = (600,600);
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endspecify
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endmodule
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