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fpga: Add X440/FBX support

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Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>


Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
This commit is contained in:
Javier Valenzuela
2023-06-12 10:27:29 -05:00
committed by Aki Tomita
co-authored by Martin Braun Wade Fife Ryan Marlow
parent a405111ce7
commit 5cadf901c7
121 changed files with 20670 additions and 8739 deletions
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top/x400/cpld/x440/led_control.v
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//
// Copyright 2022 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: led_control
//
// Description:
// Implements control over LED state via CtrlPort. The default state
// has the LEDs disabled.
//
`default_nettype none
module led_control #(
parameter BASE_ADDRESS = 0,
parameter REGMAP_SIZE = 8'h1
) (
// Clock and reset
input wire ctrlport_clk,
input wire ctrlport_rst,
// Request
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr,
input wire [31:0] s_ctrlport_req_data,
// Response
output reg s_ctrlport_resp_ack,
output reg [ 1:0] s_ctrlport_resp_status,
output reg [31:0] s_ctrlport_resp_data,
// LED Control (domain: ctrlport_clk)
output reg ch0_rx2_led,
output reg ch0_tx_led,
output reg ch0_rx_led,
output reg ch1_rx2_led,
output reg ch1_tx_led,
output reg ch1_rx_led,
output reg ch2_rx2_led,
output reg ch2_tx_led,
output reg ch2_rx_led,
output reg ch3_rx2_led,
output reg ch3_tx_led,
output reg ch3_rx_led
);
`include "../regmap/x440/led_setup_regmap_utils.vh"
`include "../../../../lib/rfnoc/core/ctrlport.vh"
//---------------------------------------------------------------
// ATR memory signals
//---------------------------------------------------------------
reg [31:0] led_ctrl_reg;
//---------------------------------------------------------------
// Handling of CtrlPort
//---------------------------------------------------------------
// Check of request address is targeted for this module.
wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + REGMAP_SIZE);
always @(posedge ctrlport_clk) begin
// reset internal registers and responses
if (ctrlport_rst) begin
s_ctrlport_resp_ack <= 1'b0;
s_ctrlport_resp_status <= 2'b0;
s_ctrlport_resp_data <= 32'b0;
end else begin
// write requests
if (s_ctrlport_req_wr) begin
// always issue an ack and no data
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_data <= {32{1'bx}};
s_ctrlport_resp_status <= CTRL_STS_OKAY;
case (s_ctrlport_req_addr)
BASE_ADDRESS + LED_CONTROL: begin
led_ctrl_reg <= s_ctrlport_req_data;
end
// error on undefined address
default: begin
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
// no response if out of range
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endcase
//req_rd not delayed
end else if (s_ctrlport_req_rd) begin
// default assumption: valid request
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_status <= CTRL_STS_OKAY;
s_ctrlport_resp_data <= {32{1'b0}};
case (s_ctrlport_req_addr)
BASE_ADDRESS : begin
s_ctrlport_resp_data <= led_ctrl_reg & LED_CONTROL_MASK;
end
// error on undefined address
default: begin
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
// no response if out of range
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endcase
// no request
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
end
always @(posedge ctrlport_clk) begin
//outputs
ch0_rx2_led <= led_ctrl_reg[CH0_RX2_LED_EN];
ch0_tx_led <= led_ctrl_reg[CH0_TRX1_LED_RED_EN];
ch0_rx_led <= led_ctrl_reg[CH0_TRX1_LED_GR_EN];
ch1_rx2_led <= led_ctrl_reg[CH1_RX2_LED_EN];
ch1_tx_led <= led_ctrl_reg[CH1_TRX1_LED_RED_EN];
ch1_rx_led <= led_ctrl_reg[CH1_TRX1_LED_GR_EN];
ch2_rx2_led <= led_ctrl_reg[CH2_RX2_LED_EN];
ch2_tx_led <= led_ctrl_reg[CH2_TRX1_LED_RED_EN];
ch2_rx_led <= led_ctrl_reg[CH2_TRX1_LED_GR_EN];
ch3_rx2_led <= led_ctrl_reg[CH3_RX2_LED_EN];
ch3_tx_led <= led_ctrl_reg[CH3_TRX1_LED_RED_EN];
ch3_rx_led <= led_ctrl_reg[CH3_TRX1_LED_GR_EN];
end
endmodule
`default_nettype wire
//XmlParse xml_on
//<regmap name="LED_SETUP_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
// <group name="LED_SETUP_REGISTERS">
// <info>
// Contains registers that control the LEDs.
// </info>
// <register name="LED_CONTROL" size="32" offset="0x0" attributes="Readable|Writable">
// <info>
// This register configures RF Frontend LEDs.
// </info>
// <bitfield name="CH0_RX2_LED_EN" range="0" initialvalue="0">
// <info>
// Enables the Ch0 Rx2 Green LED
// </info>
// </bitfield>
// <bitfield name="CH0_TRX1_LED_RED_EN" range="1" initialvalue="0">
// <info>
// Enables the Ch0 TRX (TX) Red LED
// </info>
// </bitfield>
// <bitfield name="CH0_TRX1_LED_GR_EN" range="2" initialvalue="0">
// <info>
// Enables the Ch0 TRX (RX) Green LED
// </info>
// </bitfield>
// <bitfield name="CH1_RX2_LED_EN" range="8" initialvalue="0">
// <info>
// Enables the Ch1 Rx2 Green LED
// </info>
// </bitfield>
// <bitfield name="CH1_TRX1_LED_RED_EN" range="9" initialvalue="0">
// <info>
// Enables the Ch1 TRX (TX) Red LED
// </info>
// </bitfield>
// <bitfield name="CH1_TRX1_LED_GR_EN" range="10" initialvalue="0">
// <info>
// Enables the Ch1 TRX (RX) Green LED
// </info>
// </bitfield>
// <bitfield name="CH2_RX2_LED_EN" range="16" initialvalue="0">
// <info>
// Enables the Ch2 Rx2 Green LED
// </info>
// </bitfield>
// <bitfield name="CH2_TRX1_LED_RED_EN" range="17" initialvalue="0">
// <info>
// Enables the Ch2 TRX (TX) Red LED
// </info>
// </bitfield>
// <bitfield name="CH2_TRX1_LED_GR_EN" range="18" initialvalue="0">
// <info>
// Enables the Ch2 TRX (RX) Green LED
// </info>
// </bitfield>
// <bitfield name="CH3_RX2_LED_EN" range="24" initialvalue="0">
// <info>
// Enables the Ch3 Rx2 Green LED
// </info>
// </bitfield>
// <bitfield name="CH3_TRX1_LED_RED_EN" range="25" initialvalue="0">
// <info>
// Enables the Ch3 TRX (TX) Red LED
// </info>
// </bitfield>
// <bitfield name="CH3_TRX1_LED_GR_EN" range="26" initialvalue="0">
// <info>
// Enables the Ch3 TRX (RX) Green LED
// </info>
// </bitfield>
// </register>
// </group>
//</regmap>
//XmlParse xml_off
top/x400/cpld/x440/mb_cpld.sdc
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#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
#
# Timing constraints for the x440's motherboard CPLD.
#
#####################################################################
# DB specific LED constraints
#####################################################################
# LED signals
set led_outputs [get_ports {QSFP0_LED_ACTIVE[*] QSFP0_LED_LINK[*] \
QSFP1_LED_ACTIVE[*] QSFP1_LED_LINK[*] CH*_RX2_LED[*] CH*_TX_LED[*] CH*_RX_LED[*] } ]
set_min_delay -to $led_outputs 0
set_max_delay -to $led_outputs $prc_clock_period
top/x400/cpld/x440/mb_cpld.v
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//
// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: mb_cpld
//
// Description:
//
// Top level file for the X440 motherboard CPLD.
//
// Parameters:
//
// SIMULATION : Set to 1 to speed up simulation.
//
`default_nettype none
module mb_cpld #(
parameter SIMULATION = 0
) (
//---------------------------------------------------------------------------
// Clocking
//---------------------------------------------------------------------------
// CPLD's PLL reference clock (differential input; abbreviation: pclk)
input wire PLL_REF_CLK,
// Reliable clock (100 MHz; differential input)
input wire CLK_100,
//---------------------------------------------------------------------------
// Power Supplies
//---------------------------------------------------------------------------
// Power supply clocks
output wire PWR_SUPPLY_CLK_CORE,
output wire PWR_SUPPLY_CLK_DDR4_S,
output wire PWR_SUPPLY_CLK_DDR4_N,
output wire PWR_SUPPLY_CLK_0P9V,
output wire PWR_SUPPLY_CLK_1P8V,
output wire PWR_SUPPLY_CLK_2P5V,
output wire PWR_SUPPLY_CLK_3P3V,
output wire PWR_SUPPLY_CLK_3P6V,
// Power supply control
output wire PWR_EN_5V_OSC_100,
output wire PWR_EN_5V_OSC_122_88,
output wire IPASS_POWER_DISABLE,
input wire [1:0] IPASS_POWER_EN_FAULT,
//---------------------------------------------------------------------------
// Interfaces from/to RFSoC
//---------------------------------------------------------------------------
// PL SPI slave interface
input wire PL_CPLD_SCLK,
input wire PL_CPLD_MOSI,
output reg PL_CPLD_MISO,
input wire [1:0] PL_CPLD_CS_N,
// IRQ to PL
output wire PL_CPLD_IRQ,
// PS SPI slave interface
// Chip Selects:
// PS_CPLD_CS_N(2:0) -> binary encoded chip select
// PS_CPLD_CS_N(3) -> chip select "enable"
input wire PS_CPLD_SCLK,
input wire PS_CPLD_MOSI,
output wire PS_CPLD_MISO,
input wire [3:0] PS_CPLD_CS_N,
//---------------------------------------------------------------------------
// PL Interfaces to/from Motherboard
//---------------------------------------------------------------------------
// Clocking AUX board SPI master interface
output wire CLK_DB_SCLK,
output wire CLK_DB_MOSI,
input wire CLK_DB_MISO,
output wire CLK_DB_CS_N,
// QSFP LEDs
// Port 0
output wire [3:0] QSFP0_LED_ACTIVE,
output wire [3:0] QSFP0_LED_LINK,
// Port 1
output wire [3:0] QSFP1_LED_ACTIVE,
output wire [3:0] QSFP1_LED_LINK,
// Daughterboard LED GPIO
// 1 -> DB1 / 0 -> DB0
output wire [1:0] CH0_RX2_LED,
output wire [1:0] CH0_TX_LED,
output wire [1:0] CH0_RX_LED,
output wire [1:0] CH1_RX2_LED,
output wire [1:0] CH1_TX_LED,
output wire [1:0] CH1_RX_LED,
output wire [1:0] CH2_RX2_LED,
output wire [1:0] CH2_TX_LED,
output wire [1:0] CH2_RX_LED,
output wire [1:0] CH3_RX2_LED,
output wire [1:0] CH3_TX_LED,
output wire [1:0] CH3_RX_LED,
//---------------------------------------------------------------------------
// PS Interfaces to/from Motherboard
//---------------------------------------------------------------------------
// LMK04832 SPI master interface
output wire LMK32_SCLK,
output wire LMK32_MOSI,
input wire LMK32_MISO,
output wire LMK32_CS_N,
// TPM 2.0 SPI master interface
// Note: TPM is not currently supported
output wire TPM_SCLK,
output wire TPM_MOSI,
input wire TPM_MISO,
output wire TPM_CS_N,
// Phase DAC SPI master interface
output wire PHASE_DAC_SCLK,
output wire PHASE_DAC_MOSI,
output wire PHASE_DAC_CS_N,
// DIO direction control
output wire [11:0] DIO_DIRECTION_A,
output wire [11:0] DIO_DIRECTION_B,
//---------------------------------------------------------------------------
// Miscellaneous
//---------------------------------------------------------------------------
// This signal enables the 1.8 V and 3.3 V power supply clocks.
output wire PS_CLK_ON_CPLD,
// iPASS control interface
input wire [1:0] IPASS_PRESENT_N,
inout wire [1:0] IPASS_SCL,
inout wire [1:0] IPASS_SDA,
// PCIe reset to FPGA
output wire PCIE_RESET,
// TPM reset
output wire TPM_RESET_n
);
// SPI masters (spi_top) are limited to 64 bit transmission length
`define SPI_MAX_CHAR_64
`include "../../../../lib/rfnoc/core/ctrlport.vh"
`include "../regmap/mb_cpld_ps_regmap_utils.vh"
`include "../regmap/x440/mb_cpld_pl_regmap_utils.vh"
//---------------------------------------------------------------------------
// Clocks and Resets
//---------------------------------------------------------------------------
wire clk40, clk50, clk250;
wire pll_ref_clk_int;
wire reset_clk50;
wire reset_clk40;
wire power_on_reset_clk100;
wire [0:0] pll_locked_async;
wire [0:0] pll_locked_clk50;
wire [0:0] pll_locked_clk40;
wire pll_ref_clk_en_clk50;
wire pll_ref_clk_en_pclk;
reset_generator reliable_reset_gen_inst (
.clk (CLK_100),
.power_on_reset (power_on_reset_clk100)
);
// Divide reliable clock by 2 since the design is not capable of running at
// 100 MHz. Multiple by 2.5 to get a fast clock to handle PS SPI chip select
// decoding.
pll pll_inst (
.inclk0 (CLK_100),
.c0 (clk50),
.c1 (clk250),
.c2 (clk40),
.locked (pll_locked_async)
);
// Bring pll_ref_clk enable signal to the same clock domain.
synchronizer #(
.WIDTH (1),
.STAGES (2),
.INITIAL_VAL (1'b0),
.FALSE_PATH_TO_IN (1)
) pll_ref_clk_en_sync (
.clk (PLL_REF_CLK),
.rst (1'b0),
.in (pll_ref_clk_en_clk50),
.out (pll_ref_clk_en_pclk)
);
// Enable clock using ALTCLKCTRL IP.
clkctrl pll_ref_clk_ctrl_inst (
.inclk (PLL_REF_CLK),
.ena (pll_ref_clk_en_pclk),
.outclk (pll_ref_clk_int)
);
// Use locked signal as reset for clk50 and clk40 clock domain
synchronizer #(
.WIDTH (1),
.STAGES (2),
.INITIAL_VAL (1'b0),
.FALSE_PATH_TO_IN (1)
) clk50_reset_sync (
.clk (clk50),
.rst (1'b0),
.in (pll_locked_async),
.out (pll_locked_clk50)
);
assign reset_clk50 = ~pll_locked_clk50;
synchronizer #(
.WIDTH (1),
.STAGES (2),
.INITIAL_VAL (1'b0),
.FALSE_PATH_TO_IN (1)
) clk40_reset_sync (
.clk (clk40),
.rst (1'b0),
.in (pll_locked_async),
.out (pll_locked_clk40)
);
assign reset_clk40 = ~pll_locked_clk40;
//---------------------------------------------------------------------------
// Power Supply Clock
//---------------------------------------------------------------------------
`ifdef MFG_SUPPORT
assign PWR_SUPPLY_CLK_CORE = 1'b0;
assign PWR_SUPPLY_CLK_DDR4_S = 1'b0;
assign PWR_SUPPLY_CLK_DDR4_N = 1'b0;
assign PWR_SUPPLY_CLK_0P9V = 1'b0;
assign PWR_SUPPLY_CLK_1P8V = 1'b0;
assign PWR_SUPPLY_CLK_2P5V = 1'b0;
assign PWR_SUPPLY_CLK_3P3V = 1'b0;
assign PWR_SUPPLY_CLK_3P6V = 1'b0;
`else
// Frequency definitions
localparam SOUCE_CLOCK_FREQUENCY = 100_000_000;
localparam TARGET_FREQUENCY_350k = 350_000;
localparam TARGET_FREQUENCY_450k = 450_000;
localparam TARGET_FREQUENCY_500k = 500_000;
localparam TARGET_FREQUENCY_600k = 600_000;
localparam TARGET_FREQUENCY_800k = 800_000;
localparam TARGET_FREQUENCY_1M = 1_000_000;
pwr_supply_clk_gen #(
.SOURCE_CLK_FREQ (SOUCE_CLOCK_FREQUENCY),
.TARGET_CLK_FREQ (TARGET_FREQUENCY_350k)
) freq_gen_350k (
.clk (CLK_100),
.rst (power_on_reset_clk100),
.pwr_supply_clk (PWR_SUPPLY_CLK_0P9V)
);
wire pwr_supply_clk_450k;
pwr_supply_clk_gen #(
.SOURCE_CLK_FREQ (SOUCE_CLOCK_FREQUENCY),
.TARGET_CLK_FREQ (TARGET_FREQUENCY_450k)
) freq_gen_450k (
.clk (CLK_100),
.rst (power_on_reset_clk100),
.pwr_supply_clk (pwr_supply_clk_450k)
);
assign PWR_SUPPLY_CLK_DDR4_S = pwr_supply_clk_450k;
assign PWR_SUPPLY_CLK_DDR4_N = pwr_supply_clk_450k;
pwr_supply_clk_gen #(
.SOURCE_CLK_FREQ (SOUCE_CLOCK_FREQUENCY),
.TARGET_CLK_FREQ (TARGET_FREQUENCY_500k)
) freq_gen_500k (
.clk (CLK_100),
.rst (power_on_reset_clk100),
.pwr_supply_clk (PWR_SUPPLY_CLK_CORE)
);
pwr_supply_clk_gen #(
.SOURCE_CLK_FREQ (SOUCE_CLOCK_FREQUENCY),
.TARGET_CLK_FREQ (TARGET_FREQUENCY_600k)
) freq_gen_600k (
.clk (CLK_100),
.rst (power_on_reset_clk100),
.pwr_supply_clk (PWR_SUPPLY_CLK_1P8V)
);
pwr_supply_clk_gen #(
.SOURCE_CLK_FREQ (SOUCE_CLOCK_FREQUENCY),
.TARGET_CLK_FREQ (TARGET_FREQUENCY_800k)
) freq_gen_800k (
.clk (CLK_100),
.rst (power_on_reset_clk100),
.pwr_supply_clk (PWR_SUPPLY_CLK_2P5V)
);
wire pwr_supply_clk_1M;
pwr_supply_clk_gen #(
.SOURCE_CLK_FREQ (SOUCE_CLOCK_FREQUENCY),
.TARGET_CLK_FREQ (TARGET_FREQUENCY_1M)
) freq_gen_1M (
.clk (CLK_100),
.rst (power_on_reset_clk100),
.pwr_supply_clk (pwr_supply_clk_1M)
);
assign PWR_SUPPLY_CLK_3P3V = pwr_supply_clk_1M;
assign PWR_SUPPLY_CLK_3P6V = pwr_supply_clk_1M;
`endif
//---------------------------------------------------------------------------
// PL Interfaces
//---------------------------------------------------------------------------
wire [1:0] db_clk_enable;
wire [1:0] db_reset;
wire [1:0] ipass_cable_present;
// PL SPI FPGA -> DB CPLD
reg mb_cpld_sclk, mb_cpld_mosi, mb_cpld_cs_n;
wire mb_cpld_miso;
// PL SPI chip select decoding
localparam PL_CS_MB_CPLD = 2'b00;
localparam PL_CS_DB0 = 2'b10;
localparam PL_CS_DB1 = 2'b01;
localparam PL_CS_IDLE = 2'b11;
// PL SPI registers do not have a separate reset.
// SW is expected to properly setup the DBs before issuing SPI transactions.
always @(posedge pll_ref_clk_int) begin : to_db
// Default chip selects
mb_cpld_cs_n <= 1'b1;
// MB CPLD
mb_cpld_sclk <= PL_CPLD_SCLK;
mb_cpld_mosi <= PL_CPLD_MOSI;
if (PL_CPLD_CS_N == PL_CS_MB_CPLD) begin
mb_cpld_cs_n <= 1'b0;
end
end
// SPI DB CPLD -> FPGA
always @(posedge pll_ref_clk_int) begin : from_db
case (PL_CPLD_CS_N)
PL_CS_MB_CPLD : PL_CPLD_MISO <= mb_cpld_miso; // MB CPLD
PL_CS_IDLE : PL_CPLD_MISO <= 1'bz; // Inactive
endcase
end
// Local PL SPI target
wire [19:0] pl_ctrlport_req_addr;
wire [31:0] pl_ctrlport_req_data;
wire pl_ctrlport_req_rd;
wire pl_ctrlport_req_wr;
wire pl_ctrlport_resp_ack;
wire [31:0] pl_ctrlport_resp_data;
wire [ 1:0] pl_ctrlport_resp_status;
spi_slave_to_ctrlport_master #(
.CLK_FREQUENCY (50_000_000),
.SPI_FREQUENCY (10_666_667)
) pl_spi_endpoint (
.ctrlport_clk (clk50),
.ctrlport_rst (reset_clk50),
.m_ctrlport_req_wr (pl_ctrlport_req_wr),
.m_ctrlport_req_rd (pl_ctrlport_req_rd),
.m_ctrlport_req_addr (pl_ctrlport_req_addr),
.m_ctrlport_req_data (pl_ctrlport_req_data),
.m_ctrlport_resp_ack (pl_ctrlport_resp_ack),
.m_ctrlport_resp_status (pl_ctrlport_resp_status),
.m_ctrlport_resp_data (pl_ctrlport_resp_data),
.sclk (mb_cpld_sclk),
.cs_n (mb_cpld_cs_n),
.mosi (mb_cpld_mosi),
.miso (mb_cpld_miso)
);
// Split up the PL control port
wire [19:0] pl_regs_ctrlport_req_addr;
wire [31:0] pl_regs_ctrlport_req_data;
wire pl_regs_ctrlport_req_rd;
wire pl_regs_ctrlport_req_wr;
wire pl_regs_ctrlport_resp_ack;
wire [31:0] pl_regs_ctrlport_resp_data;
wire [ 1:0] pl_regs_ctrlport_resp_status;
wire [19:0] db0_led_ctrlport_req_addr;
wire [31:0] db0_led_ctrlport_req_data;
wire db0_led_ctrlport_req_rd;
wire db0_led_ctrlport_req_wr;
wire db0_led_ctrlport_resp_ack;
wire [31:0] db0_led_ctrlport_resp_data;
wire [ 1:0] db0_led_ctrlport_resp_status;
wire [19:0] db1_led_ctrlport_req_addr;
wire [31:0] db1_led_ctrlport_req_data;
wire db1_led_ctrlport_req_rd;
wire db1_led_ctrlport_req_wr;
wire db1_led_ctrlport_resp_ack;
wire [31:0] db1_led_ctrlport_resp_data;
wire [ 1:0] db1_led_ctrlport_resp_status;
wire [19:0] pl_term_ctrlport_req_addr;
wire [31:0] pl_term_ctrlport_req_data;
wire pl_term_ctrlport_req_rd;
wire pl_term_ctrlport_req_wr;
wire pl_term_ctrlport_resp_ack;
wire [31:0] pl_term_ctrlport_resp_data;
wire [ 1:0] pl_term_ctrlport_resp_status;
ctrlport_splitter #(
.NUM_SLAVES (4)
) pl_ctrlport_splitter (
.ctrlport_clk (clk50),
.ctrlport_rst (reset_clk50),
.s_ctrlport_req_wr (pl_ctrlport_req_wr),
.s_ctrlport_req_rd (pl_ctrlport_req_rd),
.s_ctrlport_req_addr (pl_ctrlport_req_addr),
.s_ctrlport_req_data (pl_ctrlport_req_data),
.s_ctrlport_req_byte_en (),
.s_ctrlport_req_has_time (),
.s_ctrlport_req_time (),
.s_ctrlport_resp_ack (pl_ctrlport_resp_ack),
.s_ctrlport_resp_status (pl_ctrlport_resp_status),
.s_ctrlport_resp_data (pl_ctrlport_resp_data),
.m_ctrlport_req_wr ({pl_regs_ctrlport_req_wr, db0_led_ctrlport_req_wr, db1_led_ctrlport_req_wr, pl_term_ctrlport_req_wr}),
.m_ctrlport_req_rd ({pl_regs_ctrlport_req_rd, db0_led_ctrlport_req_rd, db1_led_ctrlport_req_rd, pl_term_ctrlport_req_rd}),
.m_ctrlport_req_addr ({pl_regs_ctrlport_req_addr, db0_led_ctrlport_req_addr, db1_led_ctrlport_req_addr, pl_term_ctrlport_req_addr}),
.m_ctrlport_req_data ({pl_regs_ctrlport_req_data, db0_led_ctrlport_req_data, db1_led_ctrlport_req_data, pl_term_ctrlport_req_data}),
.m_ctrlport_req_byte_en (),
.m_ctrlport_req_has_time (),
.m_ctrlport_req_time (),
.m_ctrlport_resp_ack ({pl_regs_ctrlport_resp_ack, db0_led_ctrlport_resp_ack, db1_led_ctrlport_resp_ack, pl_term_ctrlport_resp_ack}),
.m_ctrlport_resp_status ({pl_regs_ctrlport_resp_status, db0_led_ctrlport_resp_status, db1_led_ctrlport_resp_status, pl_term_ctrlport_resp_status}),
.m_ctrlport_resp_data ({pl_regs_ctrlport_resp_data, db0_led_ctrlport_resp_data, db1_led_ctrlport_resp_data, pl_term_ctrlport_resp_data})
);
pl_cpld_regs #(
.BASE_ADDRESS (PL_REGISTERS)
) pl_regs (
.ctrlport_clk (clk50),
.ctrlport_rst (reset_clk50),
.s_ctrlport_req_wr (pl_regs_ctrlport_req_wr),
.s_ctrlport_req_rd (pl_regs_ctrlport_req_rd),
.s_ctrlport_req_addr (pl_regs_ctrlport_req_addr),
.s_ctrlport_req_data (pl_regs_ctrlport_req_data),
.s_ctrlport_resp_ack (pl_regs_ctrlport_resp_ack),
.s_ctrlport_resp_status (pl_regs_ctrlport_resp_status),
.s_ctrlport_resp_data (pl_regs_ctrlport_resp_data),
.qsfp0_led_active (QSFP0_LED_ACTIVE),
.qsfp0_led_link (QSFP0_LED_LINK),
.qsfp1_led_active (QSFP1_LED_ACTIVE),
.qsfp1_led_link (QSFP1_LED_LINK),
.ipass_cable_present (ipass_cable_present)
);
led_control #(
.BASE_ADDRESS (PL_DB0_LED_REGISTERS),
.REGMAP_SIZE (PL_DB0_LED_REGISTERS_SIZE)
) led_control_db0 (
.ctrlport_clk (clk50),
.ctrlport_rst (reset_clk50),
.s_ctrlport_req_wr (db0_led_ctrlport_req_wr),
.s_ctrlport_req_rd (db0_led_ctrlport_req_rd),
.s_ctrlport_req_addr (db0_led_ctrlport_req_addr),
.s_ctrlport_req_data (db0_led_ctrlport_req_data),
.s_ctrlport_resp_ack (db0_led_ctrlport_resp_ack),
.s_ctrlport_resp_status (db0_led_ctrlport_resp_status),
.s_ctrlport_resp_data (db0_led_ctrlport_resp_data),
.ch0_rx2_led (CH0_RX2_LED[0]),
.ch0_tx_led (CH0_TX_LED[0]),
.ch0_rx_led (CH0_RX_LED[0]),
.ch1_rx2_led (CH1_RX2_LED[0]),
.ch1_tx_led (CH1_TX_LED[0]),
.ch1_rx_led (CH1_RX_LED[0]),
.ch2_rx2_led (CH2_RX2_LED[0]),
.ch2_tx_led (CH2_TX_LED[0]),
.ch2_rx_led (CH2_RX_LED[0]),
.ch3_rx2_led (CH3_RX2_LED[0]),
.ch3_tx_led (CH3_TX_LED[0]),
.ch3_rx_led (CH3_RX_LED[0])
);
led_control #(
.BASE_ADDRESS (PL_DB1_LED_REGISTERS),
.REGMAP_SIZE (PL_DB1_LED_REGISTERS_SIZE)
) led_control_db1 (
.ctrlport_clk (clk50),
.ctrlport_rst (reset_clk50),
.s_ctrlport_req_wr (db1_led_ctrlport_req_wr),
.s_ctrlport_req_rd (db1_led_ctrlport_req_rd),
.s_ctrlport_req_addr (db1_led_ctrlport_req_addr),
.s_ctrlport_req_data (db1_led_ctrlport_req_data),
.s_ctrlport_resp_ack (db1_led_ctrlport_resp_ack),
.s_ctrlport_resp_status (db1_led_ctrlport_resp_status),
.s_ctrlport_resp_data (db1_led_ctrlport_resp_data),
.ch0_rx2_led (CH0_RX2_LED[1]),
.ch0_tx_led (CH0_TX_LED[1]),
.ch0_rx_led (CH0_RX_LED[1]),
.ch1_rx2_led (CH1_RX2_LED[1]),
.ch1_tx_led (CH1_TX_LED[1]),
.ch1_rx_led (CH1_RX_LED[1]),
.ch2_rx2_led (CH2_RX2_LED[1]),
.ch2_tx_led (CH2_TX_LED[1]),
.ch2_rx_led (CH2_RX_LED[1]),
.ch3_rx2_led (CH3_RX2_LED[1]),
.ch3_tx_led (CH3_TX_LED[1]),
.ch3_rx_led (CH3_RX_LED[1])
);
// Termination of ctrlport request
ctrlport_terminator #(
.START_ADDRESS (PL_DB1_LED_REGISTERS + PL_DB1_LED_REGISTERS_SIZE),
.LAST_ADDRESS (2**CTRLPORT_ADDR_W-1)
) pl_terminator (
.ctrlport_clk (clk50),
.ctrlport_rst (reset_clk50),
.s_ctrlport_req_wr (pl_term_ctrlport_req_wr),
.s_ctrlport_req_rd (pl_term_ctrlport_req_rd),
.s_ctrlport_req_addr (pl_term_ctrlport_req_addr),
.s_ctrlport_req_data (pl_term_ctrlport_req_data),
.s_ctrlport_resp_ack (pl_term_ctrlport_resp_ack),
.s_ctrlport_resp_status (pl_term_ctrlport_resp_status),
.s_ctrlport_resp_data (pl_term_ctrlport_resp_data)
);
//---------------------------------------------------------------------------
// PS Interfaces
//---------------------------------------------------------------------------
// Local PS SPI target
wire [19:0] ps_ctrlport_req_addr;
wire [31:0] ps_ctrlport_req_data;
wire ps_ctrlport_req_rd;
wire ps_ctrlport_req_wr;
wire ps_ctrlport_resp_ack;
wire [31:0] ps_ctrlport_resp_data;
wire [ 1:0] ps_ctrlport_resp_status;
wire ps_spi_endpoint_sclk;
wire ps_spi_endpoint_mosi;
wire ps_spi_endpoint_miso;
wire ps_spi_endpoint_cs_n;
spi_slave_to_ctrlport_master #(
.CLK_FREQUENCY (50_000_000),
.SPI_FREQUENCY (5_000_000)
) ps_spi_endpoint (
.ctrlport_clk (clk50),
.ctrlport_rst (reset_clk50),
.m_ctrlport_req_wr (ps_ctrlport_req_wr),
.m_ctrlport_req_rd (ps_ctrlport_req_rd),
.m_ctrlport_req_addr (ps_ctrlport_req_addr),
.m_ctrlport_req_data (ps_ctrlport_req_data),
.m_ctrlport_resp_ack (ps_ctrlport_resp_ack),
.m_ctrlport_resp_status (ps_ctrlport_resp_status),
.m_ctrlport_resp_data (ps_ctrlport_resp_data),
.sclk (ps_spi_endpoint_sclk),
.cs_n (ps_spi_endpoint_cs_n),
.mosi (ps_spi_endpoint_mosi),
.miso (ps_spi_endpoint_miso)
);
// The PS SPI chip select signals are binary encoded.
//
// The internal SPI slaves as well as external slaves like the LMK04832
// trigger actions or resets based on edges of the chip select signal.
// Therefore this implementation has to avoid glitches on the chip select
// signal although the SPI protocol is synchronous.
//
// The chip signals are double synchronized to make sure there is no
// meta-stability. Due to different traces lengths there is no guarantee for
// the chip select signals to change at the same time. To overcome this issue
// register stage 2 and 3 are compared. Only in case of matching values the
// change is propagated to the slaves' chip select lines. Once the IDLE state
// (all ones) is detected in register stage 2 the slaves' chip select lines
// will be deasserted.
// Input sync registers (3 stages)
wire [3:0] ps_cpld_cs_n_shift2; // Resolving meta-stability, reset on IDLE
reg [3:0] ps_cpld_cs_n_shift3 = {4 {1'b1}}; // Stable state detection
synchronizer #(
.WIDTH (4),
.STAGES (2),
.INITIAL_VAL (4'b1111),
.FALSE_PATH_TO_IN (0)
) ps_spi_input_sync_inst (
.clk (clk250),
.rst (1'b0),
.in (PS_CPLD_CS_N),
.out (ps_cpld_cs_n_shift2)
);
always @(posedge clk250) begin
ps_cpld_cs_n_shift3 <= ps_cpld_cs_n_shift2;
end
// SPI binary decoding
reg [SPI_ENDPOINT_SIZE-2:0] ps_spi_cs_n_decoded = {SPI_ENDPOINT_SIZE-1 {1'b1}};
always @(posedge clk250) begin
// reset in case of IDLE state
if (ps_cpld_cs_n_shift2[2:0] == PS_CS_IDLE) begin
ps_spi_cs_n_decoded <= {SPI_ENDPOINT_SIZE-1 {1'b1}};
// only apply changes when stable state is detected
end else if (ps_cpld_cs_n_shift3[2:0] == ps_cpld_cs_n_shift2[2:0]) begin
ps_spi_cs_n_decoded[PS_CS_MB_CPLD] <= ps_cpld_cs_n_shift3[2:0] != PS_CS_MB_CPLD;
ps_spi_cs_n_decoded[PS_CS_LMK32] <= ps_cpld_cs_n_shift3[2:0] != PS_CS_LMK32;
ps_spi_cs_n_decoded[PS_CS_TPM] <= ps_cpld_cs_n_shift3[2:0] != PS_CS_TPM;
ps_spi_cs_n_decoded[PS_CS_PHASE_DAC] <= ps_cpld_cs_n_shift3[2:0] != PS_CS_PHASE_DAC;
ps_spi_cs_n_decoded[PS_CS_DB0_CAL_EEPROM] <= ps_cpld_cs_n_shift3[2:0] != PS_CS_DB0_CAL_EEPROM;
ps_spi_cs_n_decoded[PS_CS_DB1_CAL_EEPROM] <= ps_cpld_cs_n_shift3[2:0] != PS_CS_DB1_CAL_EEPROM;
ps_spi_cs_n_decoded[PS_CS_CLK_AUX_DB] <= ps_cpld_cs_n_shift3[2:0] != PS_CS_CLK_AUX_DB;
end
end
// Local SPI slave
assign ps_spi_endpoint_sclk = PS_CPLD_SCLK;
assign ps_spi_endpoint_mosi = PS_CPLD_MOSI;
assign ps_spi_endpoint_cs_n = ps_spi_cs_n_decoded[PS_CS_MB_CPLD];
// LMK04832 SPI signals
assign LMK32_SCLK = PS_CPLD_SCLK;
assign LMK32_MOSI = PS_CPLD_MOSI;
assign LMK32_CS_N = ps_spi_cs_n_decoded[PS_CS_LMK32];
// TPM SPI signals
// Note: TPM is not currently supported
assign TPM_SCLK = PS_CPLD_SCLK;
assign TPM_MOSI = PS_CPLD_MOSI;
assign TPM_CS_N = ps_spi_cs_n_decoded[PS_CS_TPM];
// Phase DAC SPI signals
assign PHASE_DAC_SCLK = PS_CPLD_SCLK;
assign PHASE_DAC_MOSI = PS_CPLD_MOSI;
assign PHASE_DAC_CS_N = ps_spi_cs_n_decoded[PS_CS_PHASE_DAC];
// CLK AUX DB SPI signals
assign CLK_DB_SCLK = PS_CPLD_SCLK;
assign CLK_DB_MOSI = PS_CPLD_MOSI;
assign CLK_DB_CS_N = ps_spi_cs_n_decoded[PS_CS_CLK_AUX_DB];
// Combine SPI responses based on inputs only as this path is captured
// synchronously to PS_CPLD_SCLK by the SPI master.
assign PS_CPLD_MISO = (PS_CPLD_CS_N[2:0] == PS_CS_MB_CPLD) ? ps_spi_endpoint_miso :
(PS_CPLD_CS_N[2:0] == PS_CS_LMK32) ? LMK32_MISO :
(PS_CPLD_CS_N[2:0] == PS_CS_TPM) ? TPM_MISO :
(PS_CPLD_CS_N[2:0] == PS_CS_CLK_AUX_DB) ? CLK_DB_MISO :
1'bz; // Default case and PHASE_DAC
// Split up the PS control port
wire [19:0] ps_regs_ctrlport_req_addr;
wire [31:0] ps_regs_ctrlport_req_data;
wire ps_regs_ctrlport_req_rd;
wire ps_regs_ctrlport_req_wr;
wire ps_regs_ctrlport_resp_ack;
wire [31:0] ps_regs_ctrlport_resp_data;
wire [ 1:0] ps_regs_ctrlport_resp_status;
wire [19:0] ps_term_ctrlport_req_addr;
wire [31:0] ps_term_ctrlport_req_data;
wire ps_term_ctrlport_req_rd;
wire ps_term_ctrlport_req_wr;
wire ps_term_ctrlport_resp_ack;
wire [31:0] ps_term_ctrlport_resp_data;
wire [ 1:0] ps_term_ctrlport_resp_status;
wire [19:0] ps_reconfig_ctrlport_req_addr;
wire [31:0] ps_reconfig_ctrlport_req_data;
wire ps_reconfig_ctrlport_req_rd;
wire ps_reconfig_ctrlport_req_wr;
wire ps_reconfig_ctrlport_resp_ack;
wire [31:0] ps_reconfig_ctrlport_resp_data;
wire [ 1:0] ps_reconfig_ctrlport_resp_status;
wire [19:0] ps_power_ctrlport_req_addr;
wire [31:0] ps_power_ctrlport_req_data;
wire ps_power_ctrlport_req_rd;
wire ps_power_ctrlport_req_wr;
wire ps_power_ctrlport_resp_ack;
wire [31:0] ps_power_ctrlport_resp_data;
wire [ 1:0] ps_power_ctrlport_resp_status;
ctrlport_splitter #(
.NUM_SLAVES (4)
) ps_ctrlport_splitter (
.ctrlport_clk (clk50),
.ctrlport_rst (reset_clk50),
.s_ctrlport_req_wr (ps_ctrlport_req_wr),
.s_ctrlport_req_rd (ps_ctrlport_req_rd),
.s_ctrlport_req_addr (ps_ctrlport_req_addr),
.s_ctrlport_req_data (ps_ctrlport_req_data),
.s_ctrlport_req_byte_en (),
.s_ctrlport_req_has_time (),
.s_ctrlport_req_time (),
.s_ctrlport_resp_ack (ps_ctrlport_resp_ack),
.s_ctrlport_resp_status (ps_ctrlport_resp_status),
.s_ctrlport_resp_data (ps_ctrlport_resp_data),
.m_ctrlport_req_wr ({ps_power_ctrlport_req_wr, ps_regs_ctrlport_req_wr, ps_term_ctrlport_req_wr, ps_reconfig_ctrlport_req_wr}),
.m_ctrlport_req_rd ({ps_power_ctrlport_req_rd, ps_regs_ctrlport_req_rd, ps_term_ctrlport_req_rd, ps_reconfig_ctrlport_req_rd}),
.m_ctrlport_req_addr ({ps_power_ctrlport_req_addr, ps_regs_ctrlport_req_addr, ps_term_ctrlport_req_addr, ps_reconfig_ctrlport_req_addr}),
.m_ctrlport_req_data ({ps_power_ctrlport_req_data, ps_regs_ctrlport_req_data, ps_term_ctrlport_req_data, ps_reconfig_ctrlport_req_data}),
.m_ctrlport_req_byte_en (),
.m_ctrlport_req_has_time (),
.m_ctrlport_req_time (),
.m_ctrlport_resp_ack ({ps_power_ctrlport_resp_ack, ps_regs_ctrlport_resp_ack, ps_term_ctrlport_resp_ack, ps_reconfig_ctrlport_resp_ack}),
.m_ctrlport_resp_status ({ps_power_ctrlport_resp_status, ps_regs_ctrlport_resp_status, ps_term_ctrlport_resp_status, ps_reconfig_ctrlport_resp_status}),
.m_ctrlport_resp_data ({ps_power_ctrlport_resp_data, ps_regs_ctrlport_resp_data, ps_term_ctrlport_resp_data, ps_reconfig_ctrlport_resp_data})
);
wire [39:0] serial_num_clk50;
wire cmi_ready_clk50;
wire cmi_other_side_detected_clk50;
ps_cpld_regs #(
.BASE_ADDRESS (PS_REGISTERS)
) ps_regs (
.ctrlport_clk (clk50),
.ctrlport_rst (reset_clk50),
.s_ctrlport_req_wr (ps_regs_ctrlport_req_wr),
.s_ctrlport_req_rd (ps_regs_ctrlport_req_rd),
.s_ctrlport_req_addr (ps_regs_ctrlport_req_addr),
.s_ctrlport_req_data (ps_regs_ctrlport_req_data),
.s_ctrlport_resp_ack (ps_regs_ctrlport_resp_ack),
.s_ctrlport_resp_status (ps_regs_ctrlport_resp_status),
.s_ctrlport_resp_data (ps_regs_ctrlport_resp_data),
.db_clk_enable (db_clk_enable),
.db_reset (db_reset),
.pll_ref_clk_enable (pll_ref_clk_en_clk50),
.dio_direction_a (DIO_DIRECTION_A),
.dio_direction_b (DIO_DIRECTION_B),
.serial_num (serial_num_clk50),
.cmi_ready (cmi_ready_clk50),
.cmi_other_side_detected (cmi_other_side_detected_clk50)
);
ps_power_regs #(
.BASE_ADDRESS (POWER_REGISTERS),
.NUM_ADDRESSES (POWER_REGISTERS_SIZE)
) ps_power_regs_inst (
.ctrlport_clk (clk50),
.ctrlport_rst (reset_clk50),
.s_ctrlport_req_wr (ps_power_ctrlport_req_wr),
.s_ctrlport_req_rd (ps_power_ctrlport_req_rd),
.s_ctrlport_req_addr (ps_power_ctrlport_req_addr),
.s_ctrlport_req_data (ps_power_ctrlport_req_data),
.s_ctrlport_resp_ack (ps_power_ctrlport_resp_ack),
.s_ctrlport_resp_status (ps_power_ctrlport_resp_status),
.s_ctrlport_resp_data (ps_power_ctrlport_resp_data),
.ipass_power_disable (IPASS_POWER_DISABLE),
.ipass_power_fault_n (IPASS_POWER_EN_FAULT),
.osc_100_en (PWR_EN_5V_OSC_100),
.osc_122_88_en (PWR_EN_5V_OSC_122_88)
);
// Termination of ctrlport request
ctrlport_terminator #(
.START_ADDRESS (POWER_REGISTERS + POWER_REGISTERS_SIZE),
.LAST_ADDRESS (2**CTRLPORT_ADDR_W-1)
) ps_terminator (
.ctrlport_clk (clk50),
.ctrlport_rst (reset_clk50),
.s_ctrlport_req_wr (ps_term_ctrlport_req_wr),
.s_ctrlport_req_rd (ps_term_ctrlport_req_rd),
.s_ctrlport_req_addr (ps_term_ctrlport_req_addr),
.s_ctrlport_req_data (ps_term_ctrlport_req_data),
.s_ctrlport_resp_ack (ps_term_ctrlport_resp_ack),
.s_ctrlport_resp_status (ps_term_ctrlport_resp_status),
.s_ctrlport_resp_data (ps_term_ctrlport_resp_data)
);
//---------------------------------------------------------------------------
// Reconfiguration
//---------------------------------------------------------------------------
// On-chip flash interface
//
// Naming is according to Avalon Memory-Mapped Interfaces:
// https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf
wire csr_addr;
wire csr_read;
wire [31:0] csr_readdata;
wire csr_write;
wire [31:0] csr_writedata;
wire [16:0] data_addr;
wire data_read;
wire [31:0] data_readdata;
wire data_readdatavalid;
wire data_waitrequest;
wire data_write;
wire [31:0] data_writedata;
wire reset_clk50_n;
assign reset_clk50_n = ~reset_clk50;
on_chip_flash flash_inst (
.clock (clk50),
.avmm_csr_addr (csr_addr),
.avmm_csr_read (csr_read),
.avmm_csr_writedata (csr_writedata),
.avmm_csr_write (csr_write),
.avmm_csr_readdata (csr_readdata),
.avmm_data_addr (data_addr),
.avmm_data_read (data_read),
.avmm_data_writedata (data_writedata),
.avmm_data_write (data_write),
.avmm_data_readdata (data_readdata),
.avmm_data_waitrequest (data_waitrequest),
.avmm_data_readdatavalid (data_readdatavalid),
.avmm_data_burstcount (4'b0001),
.reset_n (reset_clk50_n)
);
reconfig_engine #(
.BASE_ADDRESS (RECONFIG),
.NUM_ADDRESSES (RECONFIG_SIZE),
.MEM_INIT (0)
) reconfig_engine_inst (
.ctrlport_clk (clk50),
.ctrlport_rst (reset_clk50),
.s_ctrlport_req_wr (ps_reconfig_ctrlport_req_wr),
.s_ctrlport_req_rd (ps_reconfig_ctrlport_req_rd),
.s_ctrlport_req_addr (ps_reconfig_ctrlport_req_addr),
.s_ctrlport_req_data (ps_reconfig_ctrlport_req_data),
.s_ctrlport_resp_ack (ps_reconfig_ctrlport_resp_ack),
.s_ctrlport_resp_status (ps_reconfig_ctrlport_resp_status),
.s_ctrlport_resp_data (ps_reconfig_ctrlport_resp_data),
.csr_addr (csr_addr),
.csr_read (csr_read),
.csr_writedata (csr_writedata),
.csr_write (csr_write),
.csr_readdata (csr_readdata),
.data_addr (data_addr),
.data_read (data_read),
.data_writedata (data_writedata),
.data_write (data_write),
.data_readdata (data_readdata),
.data_waitrequest (data_waitrequest),
.data_readdatavalid (data_readdatavalid)
);
//---------------------------------------------------------------------------
// CMI Interface
//---------------------------------------------------------------------------
// Control and status information clock transition
wire [39:0] serial_num_clk40;
wire cmi_ready_clk40;
wire cmi_other_side_detected_clk40;
handshake #(
.WIDTH (41)
) cmi_control_hs (
.clk_a (clk50),
.rst_a (reset_clk50),
.valid_a (1'b1),
.data_a ({cmi_ready_clk50, serial_num_clk50}),
.busy_a (),
.clk_b (clk40),
.valid_b (),
.data_b ({cmi_ready_clk40, serial_num_clk40})
);
synchronizer #(
.WIDTH (1),
.STAGES (2),
.INITIAL_VAL (1'b0),
.FALSE_PATH_TO_IN (1)
) cmi_status_sync (
.clk (clk50),
.rst (reset_clk50),
.in (cmi_other_side_detected_clk40),
.out (cmi_other_side_detected_clk50)
);
wire scl_out;
wire sda_out;
wire [1:0] ipass_cable_present_n = ~ipass_cable_present;
PcieCmiWrapper #(
.kSimulation (SIMULATION)
) pcie_cmi_inst (
.Clk (clk40),
.acReset (reset_clk40),
.cSerialNumber (serial_num_clk40),
.cBoardIsReady (cmi_ready_clk40),
.cCmiReset (PCIE_RESET),
.cOtherSideDetected (cmi_other_side_detected_clk40),
.aCblPrsnt_n (ipass_cable_present_n[0]),
.aSdaIn (IPASS_SDA[0]),
.aSdaOut (sda_out),
.aSclIn (IPASS_SCL[0]),
.aSclOut (scl_out)
);
// External pull-ups are used to drive the signal high
assign IPASS_SDA[0] = sda_out ? 1'bz : 1'b0;
assign IPASS_SCL[0] = scl_out ? 1'bz : 1'b0;
// No CMI controller for second interface
assign IPASS_SCL[1] = 1'bz;
assign IPASS_SDA[1] = 1'bz;
//---------------------------------------------------------------------------
// Miscellaneous
//---------------------------------------------------------------------------
// Constants
assign PS_CLK_ON_CPLD = 1'b0; // Active-low driving of PS clocks
assign TPM_RESET_n = 1'b1;
// Currently unused ports
assign PL_CPLD_IRQ = 1'b0;
endmodule
`default_nettype wire
//XmlParse xml_on
//<top name="X440_MB_CPLD">
// <regmapcfg readablestrobes="false">
// <map name="MB_CPLD_PS_REGMAP"/>
// <map name="MB_CPLD_PL_REGMAP"/>
// </regmapcfg>
//</top>
//<regmap name="MB_CPLD_PS_REGMAP" readablestrobes="false" markdown="true" generatevhdl="true" ettusguidelines="true">
// <info>
// This register map is available using the PS CPLD SPI interface.
// </info>
// <group name="MB_CPLD_PS_WINDOWS">
// <window name="PS_REGISTERS" offset="0x00" size="0x40" targetregmap="PS_CPLD_BASE_REGMAP"/>
// <window name="RECONFIG" offset="0x40" size="0x20" targetregmap="RECONFIG_REGMAP"/>
// <window name="POWER_REGISTERS" offset="0x60" size="0x20" targetregmap="PS_POWER_REGMAP"/>
// </group>
// <group name="PS_SPI_ENDPOINTS">
// <enumeratedtype name="SPI_ENDPOINT">
// <value name="PS_CS_MB_CPLD" integer="0"/>
// <value name="PS_CS_LMK32" integer="1"/>
// <value name="PS_CS_TPM" integer="2"/>
// <value name="PS_CS_PHASE_DAC" integer="3"/>
// <value name="PS_CS_DB0_CAL_EEPROM" integer="4"/>
// <value name="PS_CS_DB1_CAL_EEPROM" integer="5"/>
// <value name="PS_CS_CLK_AUX_DB" integer="6"/>
// <value name="PS_CS_IDLE" integer="7"/>
// </enumeratedtype>
// </group>
//</regmap>
//<regmap name="MB_CPLD_PL_REGMAP" readablestrobes="false" markdown="true" generatevhdl="true" ettusguidelines="true">
// <info>
// This register map is available using the PL CPLD SPI interface.
// All protocol masters controller by this register map are running with a clock frequency of 50 MHz.
// </info>
// <group name="MB_CPLD_PL_WINDOWS">
// <window name="PL_REGISTERS" offset="0x0" size="0x40" targetregmap="PL_CPLD_BASE_REGMAP"/>
// <window name="PL_DB0_LED_REGISTERS" offset="0x50" size="0x10" targetregmap="LED_SETUP_REGMAP"/>
// <window name="PL_DB1_LED_REGISTERS" offset="0x60" size="0x10" targetregmap="LED_SETUP_REGMAP"/>
// </group>
//</regmap>
//<regmap name="CONSTANTS_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
// <group name="CONSTANTS_GROUP">
// <info>
// Basic registers containing version and capabilities information.
// </info>
// <enumeratedtype name="CONSTANTS_ENUM" showhexvalue="true">
// <info>
// This enumeration is used to create the constants held in the basic registers.
// </info>
// <value name="PS_CPLD_SIGNATURE" integer="0x0A522D28"/>
// <value name="PL_CPLD_SIGNATURE" integer="0x3FDC5C47"/>
// <value name="CPLD_REVISION" integer="0x22080414"/>
// <value name="OLDEST_CPLD_REVISION" integer="0x22080414"/>
// </enumeratedtype>
// </group>
//</regmap>
//XmlParse xml_off
top/x400/cpld/x440/quartus/mb_cpld.qpf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 13:40:17 August 15, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "18.1"
DATE = "13:40:17 August 15, 2019"
# Revisions
PROJECT_REVISION = "mb_cpld"
top/x400/cpld/x440/quartus/mb_cpld.qsf
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@@ -0,0 +1,416 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 12:02:17 February 20, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# TopCpld_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
#--------------------------------------------------------------------------
# Project properties/settings
#--------------------------------------------------------------------------
set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M04SAU169I7G
set_global_assignment -name TOP_LEVEL_ENTITY mb_cpld
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:02:17 FEBRUARY 20, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Standard Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_JTAG_PIN_SHARING ON
set_global_assignment -name GENERATE_SVF_FILE OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name NUM_PARALLEL_PROCESSORS 2
#--------------------------------------------------------------------------
# Pin constraints
#--------------------------------------------------------------------------
# Clocking.
#------------------------------------------
# CPLD's PLL reference clock.
set_location_assignment PIN_H6 -to PLL_REF_CLK
set_location_assignment PIN_G5 -to "PLL_REF_CLK(n)"
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL LVPECL" -to PLL_REF_CLK
# Reliable clock (100 MHz).
set_location_assignment PIN_H4 -to CLK_100
set_location_assignment PIN_H5 -to "CLK_100(n)"
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL LVPECL" -to CLK_100
# Power supply clocks.
set_location_assignment PIN_H8 -to PWR_SUPPLY_CLK_CORE
set_location_assignment PIN_H9 -to PWR_SUPPLY_CLK_DDR4_S
set_location_assignment PIN_G12 -to PWR_SUPPLY_CLK_DDR4_N
set_location_assignment PIN_L13 -to PWR_SUPPLY_CLK_0P9V
set_location_assignment PIN_G13 -to PWR_SUPPLY_CLK_1P8V
set_location_assignment PIN_K10 -to PWR_SUPPLY_CLK_2P5V
set_location_assignment PIN_J10 -to PWR_SUPPLY_CLK_3P3V
set_location_assignment PIN_L12 -to PWR_SUPPLY_CLK_3P6V
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_0P9V
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_1P8V
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_2P5V
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_3P3V
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_3P6V
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_CORE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_DDR4_N
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_DDR4_S
# Oscillator power supply
set_location_assignment PIN_L2 -to PWR_EN_5V_OSC_100
set_location_assignment PIN_N2 -to PWR_EN_5V_OSC_122_88
set_instance_assignment -name IO_STANDARD "2.5 V" -to PWR_EN_5V_OSC_100
set_instance_assignment -name IO_STANDARD "2.5 V" -to PWR_EN_5V_OSC_122_88
# Interfaces from/to RFSoC.
#------------------------------------------
# PL SPI slave interface.
set_location_assignment PIN_G2 -to PL_CPLD_SCLK
set_location_assignment PIN_F5 -to PL_CPLD_MOSI
set_location_assignment PIN_F6 -to PL_CPLD_MISO
set_location_assignment PIN_G1 -to PL_CPLD_CS_N[0]
set_location_assignment PIN_G4 -to PL_CPLD_CS_N[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to PL_CPLD_SCLK
set_instance_assignment -name IO_STANDARD "1.8 V" -to PL_CPLD_MOSI
set_instance_assignment -name IO_STANDARD "1.8 V" -to PL_CPLD_MISO
set_instance_assignment -name IO_STANDARD "1.8 V" -to PL_CPLD_CS_N[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to PL_CPLD_CS_N[1]
# IRQ to PL.
set_location_assignment PIN_F4 -to PL_CPLD_IRQ
set_instance_assignment -name IO_STANDARD "1.8 V" -to PL_CPLD_IRQ
# PS SPI slave interface.
set_location_assignment PIN_E3 -to PS_CPLD_SCLK
set_location_assignment PIN_E1 -to PS_CPLD_MOSI
set_location_assignment PIN_F1 -to PS_CPLD_MISO
set_location_assignment PIN_B1 -to PS_CPLD_CS_N[0]
set_location_assignment PIN_C1 -to PS_CPLD_CS_N[1]
set_location_assignment PIN_E4 -to PS_CPLD_CS_N[2]
set_location_assignment PIN_D1 -to PS_CPLD_CS_N[3]
set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_SCLK
set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_MOSI
set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_MISO
set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_CS_N[0]
set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_CS_N[1]
set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_CS_N[2]
set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_CS_N[3]
# PL Interfaces to/from motherboard.
#------------------------------------------
# White Rabbit DAC SPI master interface.
set_location_assignment PIN_A12 -to CLK_DB_SCLK
set_location_assignment PIN_B13 -to CLK_DB_MOSI
set_location_assignment PIN_D12 -to CLK_DB_MISO
set_location_assignment PIN_D9 -to CLK_DB_CS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLK_DB_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLK_DB_MOSI
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLK_DB_MISO
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLK_DB_CS_N
# iPASS interfaces.
set_location_assignment PIN_A6 -to IPASS_SCL[0]
set_location_assignment PIN_H2 -to IPASS_SCL[1]
set_location_assignment PIN_A7 -to IPASS_SDA[0]
set_location_assignment PIN_H3 -to IPASS_SDA[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to IPASS_SCL[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to IPASS_SCL[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to IPASS_SDA[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to IPASS_SDA[1]
set_location_assignment PIN_B11 -to IPASS_PRESENT_N[0]
set_location_assignment PIN_F8 -to IPASS_PRESENT_N[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to IPASS_PRESENT_N[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to IPASS_PRESENT_N[1]
# QSFP LEDs.
set_location_assignment PIN_E12 -to QSFP0_LED_ACTIVE[0]
set_location_assignment PIN_F12 -to QSFP0_LED_ACTIVE[1]
set_location_assignment PIN_E9 -to QSFP0_LED_ACTIVE[2]
set_location_assignment PIN_J1 -to QSFP0_LED_ACTIVE[3]
set_location_assignment PIN_F10 -to QSFP0_LED_LINK[0]
set_location_assignment PIN_F9 -to QSFP0_LED_LINK[1]
set_location_assignment PIN_N11 -to QSFP0_LED_LINK[2]
set_location_assignment PIN_D13 -to QSFP0_LED_LINK[3]
set_location_assignment PIN_M1 -to QSFP1_LED_ACTIVE[0]
set_location_assignment PIN_N3 -to QSFP1_LED_ACTIVE[1]
set_location_assignment PIN_L3 -to QSFP1_LED_ACTIVE[2]
set_location_assignment PIN_K2 -to QSFP1_LED_ACTIVE[3]
set_location_assignment PIN_M2 -to QSFP1_LED_LINK[0]
set_location_assignment PIN_M3 -to QSFP1_LED_LINK[1]
set_location_assignment PIN_K1 -to QSFP1_LED_LINK[2]
set_location_assignment PIN_L1 -to QSFP1_LED_LINK[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_ACTIVE[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_ACTIVE[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_ACTIVE[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP0_LED_ACTIVE[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_LINK[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_LINK[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_LINK[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_LINK[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_ACTIVE[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_ACTIVE[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_ACTIVE[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_ACTIVE[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_LINK[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_LINK[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_LINK[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_LINK[3]
# DIO direction control.
set_location_assignment PIN_N12 -to DIO_DIRECTION_A[0]
set_location_assignment PIN_N10 -to DIO_DIRECTION_A[1]
set_location_assignment PIN_N9 -to DIO_DIRECTION_A[2]
set_location_assignment PIN_M4 -to DIO_DIRECTION_A[3]
set_location_assignment PIN_M5 -to DIO_DIRECTION_A[4]
set_location_assignment PIN_N4 -to DIO_DIRECTION_A[5]
set_location_assignment PIN_N5 -to DIO_DIRECTION_A[6]
set_location_assignment PIN_N7 -to DIO_DIRECTION_A[7]
set_location_assignment PIN_N8 -to DIO_DIRECTION_A[8]
set_location_assignment PIN_M8 -to DIO_DIRECTION_A[9]
set_location_assignment PIN_M9 -to DIO_DIRECTION_A[10]
set_location_assignment PIN_M13 -to DIO_DIRECTION_A[11]
set_location_assignment PIN_L5 -to DIO_DIRECTION_B[0]
set_location_assignment PIN_L4 -to DIO_DIRECTION_B[1]
set_location_assignment PIN_K5 -to DIO_DIRECTION_B[2]
set_location_assignment PIN_J5 -to DIO_DIRECTION_B[3]
set_location_assignment PIN_N6 -to DIO_DIRECTION_B[4]
set_location_assignment PIN_M7 -to DIO_DIRECTION_B[5]
set_location_assignment PIN_J6 -to DIO_DIRECTION_B[6]
set_location_assignment PIN_K6 -to DIO_DIRECTION_B[7]
set_location_assignment PIN_J7 -to DIO_DIRECTION_B[8]
set_location_assignment PIN_K7 -to DIO_DIRECTION_B[9]
set_location_assignment PIN_M12 -to DIO_DIRECTION_B[10]
set_location_assignment PIN_M11 -to DIO_DIRECTION_B[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[11]
# PS Interfaces to/from motherboard.
#------------------------------------------
# LMK04832 SPI master interface.
set_location_assignment PIN_J9 -to LMK32_SCLK
set_location_assignment PIN_H13 -to LMK32_MOSI
set_location_assignment PIN_L11 -to LMK32_MISO
set_location_assignment PIN_J13 -to LMK32_CS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LMK32_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LMK32_MOSI
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LMK32_MISO
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LMK32_CS_N
# TPM 2.0 SPI master interface.
set_location_assignment PIN_D11 -to TPM_SCLK
set_location_assignment PIN_E10 -to TPM_MOSI
set_location_assignment PIN_C13 -to TPM_MISO
set_location_assignment PIN_L10 -to TPM_CS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TPM_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TPM_MOSI
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TPM_MISO
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TPM_CS_N
# Phase DAC SPI master interface.
set_location_assignment PIN_K8 -to PHASE_DAC_SCLK
set_location_assignment PIN_J8 -to PHASE_DAC_MOSI
set_location_assignment PIN_M10 -to PHASE_DAC_CS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHASE_DAC_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHASE_DAC_MOSI
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHASE_DAC_CS_N
# DB0 TX/RX LEDS per chan
#-------------------------------------------
set_location_assignment PIN_A11 -to CH0_TX_LED[0]
set_location_assignment PIN_C10 -to CH0_RX_LED[0]
set_location_assignment PIN_A9 -to CH0_RX2_LED[0]
set_location_assignment PIN_E8 -to CH1_TX_LED[0]
set_location_assignment PIN_D8 -to CH1_RX_LED[0]
set_location_assignment PIN_A8 -to CH1_RX2_LED[0]
set_location_assignment PIN_C9 -to CH2_TX_LED[0]
set_location_assignment PIN_A10 -to CH2_RX_LED[0]
set_location_assignment PIN_B10 -to CH2_RX2_LED[0]
set_location_assignment PIN_K12 -to CH3_TX_LED[0]
set_location_assignment PIN_K11 -to CH3_RX_LED[0]
set_location_assignment PIN_J12 -to CH3_RX2_LED[0]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH0_TX_LED[0]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH0_RX_LED[0]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH0_RX2_LED[0]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH1_TX_LED[0]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH1_RX_LED[0]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH1_RX2_LED[0]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH2_TX_LED[0]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH2_RX_LED[0]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH2_RX2_LED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH3_TX_LED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH3_RX_LED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH3_RX2_LED[0]
# DB0 TX/RX LEDS per chan
#-------------------------------------------
set_location_assignment PIN_D6 -to CH0_TX_LED[1]
set_location_assignment PIN_E6 -to CH0_RX_LED[1]
set_location_assignment PIN_A4 -to CH0_RX2_LED[1]
set_location_assignment PIN_A5 -to CH1_TX_LED[1]
set_location_assignment PIN_A3 -to CH1_RX_LED[1]
set_location_assignment PIN_B2 -to CH1_RX2_LED[1]
set_location_assignment PIN_B3 -to CH2_TX_LED[1]
set_location_assignment PIN_B6 -to CH2_RX_LED[1]
set_location_assignment PIN_B5 -to CH2_RX2_LED[1]
set_location_assignment PIN_E13 -to CH3_TX_LED[1]
set_location_assignment PIN_G10 -to CH3_RX_LED[1]
set_location_assignment PIN_G9 -to CH3_RX2_LED[1]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH0_TX_LED[1]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH0_RX_LED[1]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH0_RX2_LED[1]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH1_TX_LED[1]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH1_RX_LED[1]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH1_RX2_LED[1]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH2_TX_LED[1]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH2_RX_LED[1]
set_instance_assignment -name IO_STANDARD "1.8-V" -to CH2_RX2_LED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH3_TX_LED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH3_RX_LED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH3_RX2_LED[1]
# Miscellaneous.
#------------------------------------------
# Power supply clocks switch.
set_location_assignment PIN_J2 -to PS_CLK_ON_CPLD
set_instance_assignment -name IO_STANDARD "2.5 V" -to PS_CLK_ON_CPLD
# iPASS misc.
set_location_assignment PIN_B12 -to IPASS_POWER_DISABLE
set_location_assignment PIN_C11 -to IPASS_POWER_EN_FAULT[0]
set_location_assignment PIN_C12 -to IPASS_POWER_EN_FAULT[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to IPASS_POWER_DISABLE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to IPASS_POWER_EN_FAULT[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to IPASS_POWER_EN_FAULT[1]
# PCIe reset to FPGA.
set_location_assignment PIN_A2 -to PCIE_RESET
set_instance_assignment -name IO_STANDARD "1.8 V" -to PCIE_RESET
# TPM reset.
set_location_assignment PIN_K13 -to TPM_RESET_n
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TPM_RESET_n
# File list.
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE"
set_global_assignment -name EN_USER_IO_WEAK_PULLUP OFF
set_global_assignment -name EN_SPI_IO_WEAK_PULLUP OFF
set_global_assignment -name VHDL_FILE ../ip/cmi/PcieCmiWrapper.vhd
set_global_assignment -name VHDL_FILE ../ip/cmi/PcieCmi.vhd
set_global_assignment -name QSYS_FILE ../ip/clkctrl/clkctrl.qsys
set_global_assignment -name QSYS_FILE ../ip/on_chip_flash/on_chip_flash.qsys
set_global_assignment -name SDC_FILE ../common/common.sdc
set_global_assignment -name SDC_FILE ../x440/mb_cpld.sdc
set_global_assignment -name VERILOG_FILE ../x440/mb_cpld.v
set_global_assignment -name VERILOG_FILE ../x440/led_control.v
set_global_assignment -name VERILOG_FILE ../common/reconfig_engine.v
set_global_assignment -name VERILOG_FILE ../common/ctrlport_to_spi.v
set_global_assignment -name VERILOG_FILE ../common/pl_cpld_regs.v
set_global_assignment -name VERILOG_FILE ../common/pwr_supply_clk_gen.v
set_global_assignment -name VERILOG_FILE ../common/ps_cpld_regs.v
set_global_assignment -name VERILOG_FILE ../common/ps_power_regs.v
set_global_assignment -name VERILOG_FILE ../common/reset_generator.v
set_global_assignment -name VERILOG_FILE ../common/spi_slave_to_ctrlport_master.v
set_global_assignment -name VERILOG_FILE ../common/spi_slave.v
set_global_assignment -name QIP_FILE ../ip/pll/pll.qip
set_global_assignment -name VERILOG_FILE ../../../../lib/control/synchronizer_impl.v
set_global_assignment -name VERILOG_FILE ../../../../lib/control/synchronizer.v
set_global_assignment -name VERILOG_FILE ../../../../lib/rfnoc/utils/ctrlport_splitter.v
set_global_assignment -name VERILOG_FILE ../../../../lib/rfnoc/utils/ctrlport_terminator.v
set_global_assignment -name VERILOG_FILE ../../../../lib/wb_spi/rtl/verilog/spi_top.v
set_global_assignment -name VERILOG_FILE ../../../../lib/wb_spi/rtl/verilog/spi_shift.v
set_global_assignment -name VERILOG_FILE ../../../../lib/wb_spi/rtl/verilog/spi_defines.v
set_global_assignment -name VERILOG_FILE ../../../../lib/wb_spi/rtl/verilog/spi_clgen.v
set_global_assignment -name VERILOG_FILE ../../../../lib/control/pulse_synchronizer.v
set_global_assignment -name VERILOG_FILE ../../../../lib/control/handshake.v
set_global_assignment -name VHDL_FILE ../../../../lib/vivado_ipi/axi_bitq/bitq_fsm.vhd
set_global_assignment -name VHDL_FILE ../../../../lib/vivado_ipi/axi_bitq/axi_bitq.vhd
set_global_assignment -name SOURCE_FILE db/mb_cpld.cmp.rdb
set_global_assignment -name PARTITION_NETLIST_TYPE POST_FIT -section_id "PcieCmi:PcieCmix"
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id "PcieCmi:PcieCmix"
set_global_assignment -name PARTITION_COLOR 52377 -section_id "PcieCmi:PcieCmix"
set_global_assignment -name PARTITION_IMPORT_FILE ../../ip/cmi/PcieCmi.qxp -section_id "PcieCmi:PcieCmix"
set_global_assignment -name PARTITION_LAST_IMPORTED_FILE ip/cmi/PcieCmi.qxp -section_id "PcieCmi:PcieCmix"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY pciec_5b6b1 -to "PcieCmiWrapper:pcie_cmi_inst|PcieCmi:PcieCmix" -section_id "PcieCmi:PcieCmix"