miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fpga: Add X440/FBX support

Browse Source 
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>


Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
This commit is contained in:
Javier Valenzuela
2023-06-12 10:27:29 -05:00
committed by Aki Tomita
co-authored by Martin Braun Wade Fife Ryan Marlow
parent a405111ce7
commit 5cadf901c7
121 changed files with 20670 additions and 8739 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/x400/constraints/timing/x440_clocks_1600.xdc
+20
View File
@@ -0,0 +1,20 @@
#
# Copyright 2023 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# Clock definition constraints for X440 1600 type images
#
# Data clocks: Generated by the MMCM, used for data paths between the RFDC output
# and RFNoC. Maximum supported master clock rate is 2.048 Gsps @8SPC => 256 MHz.
set rfdc_data_clk_period 3.906
create_clock -name rfdc_r0_clk -add \
-period $rfdc_data_clk_period \
[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT2]
create_clock -name rfdc_r1_clk -add \
-period $rfdc_data_clk_period \
[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT5]