fpga: Add X440/FBX support
Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
This commit is contained in:
Javier Valenzuela
committed by
Aki Tomita
Aki Tomita
co-authored by
Martin Braun
Wade Fife
Ryan Marlow
Martin Braun
Wade Fife
Ryan Marlow
parent
a405111ce7
commit
5cadf901c7
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#
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# Copyright 2022 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Description:
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# Timing constraints exclusive to X440. These should be used
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# in conjunction with ./common.xdc
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#
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###############################################################################
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# DB GPIO
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# This interface is defined as system synchronous to pll_ref_clk.
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# Some timing constants in this section are declared in
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# <repo>/fpga/usrp3/top/x400/constraints/timing/shared_constants.sdc
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###############################################################################
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# In the current db_gpio_interface implementation, all GPIOs are received asynchronously
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# by the DB, so we add a very relax constraint for these signals.
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set db_gpio_min 0
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set db_gpio_max [expr {$pll_ref_clk_period/2}]
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set db_gpio_sync_max 3.500
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# Set constraints for all ports.
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set db_gpio_ports [get_ports {DB0_GPIO[*] DB1_GPIO[*]}]
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set db_gpio_sync_ports [get_ports {DB0_GPIO[12] DB0_GPIO[13] DB1_GPIO[16] DB1_GPIO[17]}]
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set_output_delay -clock [get_clocks pll_ref_clk] -min $db_gpio_min $db_gpio_ports
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set_output_delay -clock [get_clocks pll_ref_clk] -max $db_gpio_max $db_gpio_ports
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# Should just overwrite the setting for the sync clock ports that are also in db_gpio_ports
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set_output_delay -clock [get_clocks ref_clk] -max $db_gpio_sync_max $db_gpio_sync_ports
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set_input_delay -clock [get_clocks pll_ref_clk] -max $db_gpio_min $db_gpio_ports
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set_input_delay -clock [get_clocks pll_ref_clk] -min $db_gpio_max $db_gpio_ports
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# Use multi cycle path constraint to relax timing on these pins.
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set_multicycle_path -setup 2 -from [get_pins db_gpio_gen[*].db_gpio_interface_i/ctrlport_to_i2c_inst/i2c_master/byte_controller/bit_controller/*_oen_reg/C]
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set_multicycle_path -end -hold 7 -from [get_pins db_gpio_gen[*].db_gpio_interface_i/ctrlport_to_i2c_inst/i2c_master/byte_controller/bit_controller/*_oen_reg/C]
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###############################################################################
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# x440_ps_rfdc_bd
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###############################################################################
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# This property tells Vivado that we require these clocks to be well aligned.
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# We have synchronous clock domain crossings between these clocks that can have
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# large hold violations after placement due to uneven clock loading.
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set_property CLOCK_DELAY_GROUP DataClkGroup [get_nets -hier -filter {\
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NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk ||\
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NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk_2x ||\
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NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/pll_ref_clk_out ||\
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NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/radio0_rfdc_clk ||\
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NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/radio0_rfdc_clk_2x ||\
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NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/radio1_rfdc_clk ||\
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NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/radio1_rfdc_clk_2x \
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}]
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# We treat rfdc_clk buffers as asynchronous, with knowledge that
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# code clocked in this domain will be reset after this clocked is enabled. This
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# will make timing easier to meet on these clock domains.
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set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdc0Bufg1x*/C}] \
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-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rf0_clk_1x_buf/*BUFGCE*/CE}]
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set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdc0Bufg2x*/C}] \
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-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rf0_clk_2x_buf/*BUFGCE*/CE}]
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set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdc1Bufg1x*/C}] \
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-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rf1_clk_1x_buf/*BUFGCE*/CE}]
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set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdc1Bufg2x*/C}] \
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-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rf1_clk_2x_buf/*BUFGCE*/CE}]
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###############################################################################
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# SPLL SYSREF Capture
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###############################################################################
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# SYSREF is generated by the LMK04832 clocking chip (SPLL), which also produces
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# the PLL reference clock (PRC) used to generate data clocks with a MMCM. Both
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# SYSREF and PLL reference clock are directly fed into the RFSoC.
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# SYSREF is captured by the FPGA fabric in the PRC clock domain (MMCM's PRC
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# output) with a double synchronizer and then transfered to the RFDC clock
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# domain. Both SYSREF versions (PRC and RFDC) are used by downstream logic for
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# sync. purposes.
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# SYSREF is a continuous signal intentionally shifted in the LMK chip to align
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# it closer to the PRC's falling edge.
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# The highest PRC frequency supported in MPM (64 MHz) is used for
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# timing constraints. Therefore, SYSREF LMK's delay = (1/64e6)/2.
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set sysref_lmk_delay 7.8125
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#
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# These are the signals' lengths and corresponding delays (assuming 170 ps/in):
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# - SYSREF --> 5794 mils (5.794 inches) = 0.985 ns
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# - PRC --> 5668 mils (5.668 inches) = 0.964 ns
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#
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# For min/max input delay calculations, it is assumed min prop. delay of 0 ns,
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# which essentially over-constrains SYSREF.
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#
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# The max input delay is the latest that SYSREF may arrive w.r.t PRC, and it is
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# calculated as follows:
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# Input delay (max) = SYSREF's LMK delay + SYSREF prop. delay (max)
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# - PRC prop. delay (min)
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set sysref_max_input_delay [expr {$sysref_lmk_delay + 0.985 - 0}]
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#
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# The min input delay is the earliest that SYSREF may arrive w.r.t PRC, and it
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# is calculated as follows:
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# Input delay (min) = SYSREF's LMK delay + SYSREF prop. delay (min)
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# - PRC prop. delay (min)
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set sysref_min_input_delay [expr {$sysref_lmk_delay + 0 - 0.964}]
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set_input_delay -clock pll_ref_clk -max $sysref_max_input_delay [get_ports {SYSREF_FABRIC_P}]
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set_input_delay -clock pll_ref_clk -min $sysref_min_input_delay [get_ports {SYSREF_FABRIC_P}]
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###############################################################################
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# SPI to MB CPLD (PL)
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# This interface is defined as system synchronous to pll_ref_clk.
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###############################################################################
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# The output delays are chosen to allow a large time window of valid data for
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# the MB CPLD logic.
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set spi_min_out_delay -1.500
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set spi_max_out_delay 9.500
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# Set output constraints for all ports.
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set spi_out_ports [get_ports {PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_CS0_n PL_CPLD_CS1_n}]
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set_output_delay -clock [get_clocks pll_ref_clk] -min $spi_min_out_delay $spi_out_ports
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set_output_delay -clock [get_clocks pll_ref_clk] -max $spi_max_out_delay $spi_out_ports
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@@ -0,0 +1,37 @@
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#
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# Copyright 2022 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Description:
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# Clock definition constraints for X440
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#
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###############################################################################
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# MMCM-Related Clocks
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#
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# Note: Vivado will create generated clocks based on the default MMCM settings
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# configured in the clocking wizard, but we are going to dynamically change
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# those clocks, and so we need to provide worst-case values in here.
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###############################################################################
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# PLL Reference Clock (PRC) input. This goes from the LMK straight to the MMCM
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# input, and is used to generate the internal PRC as well as RFDC/data clocks.
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set pll_ref_clk_in_period 15.625
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create_clock -name pll_ref_in_clk -period $pll_ref_clk_in_period [get_ports PLL_REFCLK_FPGA_P]
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# Internal PLL Reference Clock (PRC). Used to derive data clocks. Constrain to
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# the fastest possible clock rate supported in the driver.
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set pll_ref_clk_period 15.625
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create_clock -name pll_ref_clk \
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-period $pll_ref_clk_period \
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[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT0]
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###############################################################################
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# Generated Clocks
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###############################################################################
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create_generated_clock -name sync_ref_clk \
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-source [get_ports BASE_REFCLK_FPGA_P] \
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-divide_by 2 [get_pins clock_div_5mhz/clk_out_reg/Q]
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@@ -0,0 +1,20 @@
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#
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# Copyright 2023 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Description:
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# Clock definition constraints for X440 1600 type images
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#
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# Data clocks: Generated by the MMCM, used for data paths between the RFDC output
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# and RFNoC. Maximum supported master clock rate is 2.048 Gsps @8SPC => 256 MHz.
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set rfdc_data_clk_period 3.906
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create_clock -name rfdc_r0_clk -add \
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-period $rfdc_data_clk_period \
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[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT2]
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create_clock -name rfdc_r1_clk -add \
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-period $rfdc_data_clk_period \
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[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT5]
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@@ -0,0 +1,21 @@
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#
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# Copyright 2023 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Description:
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# Clock definition constraints for X440 400 type images
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#
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# Data clocks: Generated by the MMCM, used for data paths between the RFDC output
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# and RFNoC. Maximum supported master clock rate is 500 Msps @8SPC => 62.5 MHz.
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# Theoretical maximum converter rate is 4.096 GSps, so really, 512 Msps @ 8SPC => 64 MHz.
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set rfdc_data_clk_period 15.625
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create_clock -name rfdc_r0_clk -add \
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-period $rfdc_data_clk_period \
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[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT2]
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create_clock -name rfdc_r1_clk -add \
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-period $rfdc_data_clk_period \
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[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT5]
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