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fpga: Add X440/FBX support

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Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>


Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
This commit is contained in:
Javier Valenzuela
2023-06-12 10:27:29 -05:00
committed by Aki Tomita
co-authored by Martin Braun Wade Fife Ryan Marlow
parent a405111ce7
commit 5cadf901c7
121 changed files with 20670 additions and 8739 deletions
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top/x400/constraints/pins/qsfp1_0.xdc
-1
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@@ -26,4 +26,3 @@ set_property PACKAGE_PIN Y36 [get_ports {QSFP1_0_TX_N}]
set_property PACKAGE_PIN Y31 [get_ports {GTY_RCV_CLK_P}]
set_property PACKAGE_PIN Y32 [get_ports {GTY_RCV_CLK_N}]
set_property IOSTANDARD DIFF_SSTL12 [get_ports {GTY_RCV_CLK_*}]
top/x400/constraints/pins/rfdc_4x4.xdc
+87
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@@ -0,0 +1,87 @@
#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# RF data converters pin constraints for X440.
# Converter pin mapping can be found at(redirected from UG1075):
# https://www.xilinx.com/support/packagefiles/zuppackages/xczu28drffvg1517pkg.txt
#
# SYSREF input for data converters.
set_property PACKAGE_PIN U4 [get_ports {SYSREF_RF_N}]
set_property PACKAGE_PIN U5 [get_ports {SYSREF_RF_P}]
###############################################################################
# Pin constraints for the ADCs
###############################################################################
# ADC Reference Clocks for Slot 0 (DBA)
set_property PACKAGE_PIN AF5 [get_ports {ADC_CLK_P[0]}]
set_property PACKAGE_PIN AF4 [get_ports {ADC_CLK_N[0]}]
set_property PACKAGE_PIN AD5 [get_ports {ADC_CLK_P[1]}]
set_property PACKAGE_PIN AD4 [get_ports {ADC_CLK_N[1]}]
# ADC Reference Clocks for Slot 1 (DBB)
set_property PACKAGE_PIN AB5 [get_ports {ADC_CLK_P[2]}]
set_property PACKAGE_PIN AB4 [get_ports {ADC_CLK_N[2]}]
set_property PACKAGE_PIN Y5 [get_ports {ADC_CLK_P[3]}]
set_property PACKAGE_PIN Y4 [get_ports {ADC_CLK_N[3]}]
# ADC Inputs for Slot 0 (DBA)
# Note: numbering here does NOT match schematic, but it is the right order
# according to RF BD Connection spec.
set_property PACKAGE_PIN AH2 [get_ports {DB0_RX_P[3]}]
set_property PACKAGE_PIN AH1 [get_ports {DB0_RX_N[3]}]
set_property PACKAGE_PIN AK2 [get_ports {DB0_RX_P[2]}]
set_property PACKAGE_PIN AK1 [get_ports {DB0_RX_N[2]}]
set_property PACKAGE_PIN AM2 [get_ports {DB0_RX_P[1]}]
set_property PACKAGE_PIN AM1 [get_ports {DB0_RX_N[1]}]
set_property PACKAGE_PIN AP2 [get_ports {DB0_RX_P[0]}]
set_property PACKAGE_PIN AP1 [get_ports {DB0_RX_N[0]}]
# ADC Inputs for Slot 1 (DBB)
# Note: numbering here does NOT match schematic, but it is the right order
# according to RF BD Connection spec.
set_property PACKAGE_PIN Y2 [get_ports {DB1_RX_P[3]}]
set_property PACKAGE_PIN Y1 [get_ports {DB1_RX_N[3]}]
set_property PACKAGE_PIN AB2 [get_ports {DB1_RX_P[2]}]
set_property PACKAGE_PIN AB1 [get_ports {DB1_RX_N[2]}]
set_property PACKAGE_PIN AD2 [get_ports {DB1_RX_P[1]}]
set_property PACKAGE_PIN AD1 [get_ports {DB1_RX_N[1]}]
set_property PACKAGE_PIN AF2 [get_ports {DB1_RX_P[0]}]
set_property PACKAGE_PIN AF1 [get_ports {DB1_RX_N[0]}]
###############################################################################
# Pin constraints for the DACs
###############################################################################
# DAC Reference Clock for Slot 0 (DBA)
set_property PACKAGE_PIN R5 [get_ports {DAC_CLK_P[0]}]
set_property PACKAGE_PIN R4 [get_ports {DAC_CLK_N[0]}]
# DAC Reference Clock for Slot 1 (DBB)
set_property PACKAGE_PIN N5 [get_ports {DAC_CLK_P[1]}]
set_property PACKAGE_PIN N4 [get_ports {DAC_CLK_N[1]}]
# DAC Outputs for Slot 0 (DBA)
set_property PACKAGE_PIN U2 [get_ports {DB0_TX_P[0]}]
set_property PACKAGE_PIN U1 [get_ports {DB0_TX_N[0]}]
set_property PACKAGE_PIN R2 [get_ports {DB0_TX_P[1]}]
set_property PACKAGE_PIN R1 [get_ports {DB0_TX_N[1]}]
set_property PACKAGE_PIN N2 [get_ports {DB0_TX_P[2]}]
set_property PACKAGE_PIN N1 [get_ports {DB0_TX_N[2]}]
set_property PACKAGE_PIN L2 [get_ports {DB0_TX_P[3]}]
set_property PACKAGE_PIN L1 [get_ports {DB0_TX_N[3]}]
# DAC Outputs for Slot 1 (DBB)
set_property PACKAGE_PIN J2 [get_ports {DB1_TX_P[0]}]
set_property PACKAGE_PIN J1 [get_ports {DB1_TX_N[0]}]
set_property PACKAGE_PIN G2 [get_ports {DB1_TX_P[1]}]
set_property PACKAGE_PIN G1 [get_ports {DB1_TX_N[1]}]
set_property PACKAGE_PIN E2 [get_ports {DB1_TX_P[2]}]
set_property PACKAGE_PIN E1 [get_ports {DB1_TX_N[2]}]
set_property PACKAGE_PIN C2 [get_ports {DB1_TX_P[3]}]
set_property PACKAGE_PIN C1 [get_ports {DB1_TX_N[3]}]
top/x400/constraints/pins/x440/db_gpio.xdc
+180
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@@ -0,0 +1,180 @@
#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# DB GPIO pin constraints for X440.
#
###############################################################################
# Pin constraints for the other PL pins (1.8 V)
###############################################################################
set_property PACKAGE_PIN F6 [get_ports {DB1_GPIO[0]}]
set_property PACKAGE_PIN E6 [get_ports {DB1_GPIO[1]}]
set_property PACKAGE_PIN E9 [get_ports {DB1_GPIO[2]}]
set_property PACKAGE_PIN E8 [get_ports {DB1_GPIO[3]}]
set_property PACKAGE_PIN E7 [get_ports {DB1_GPIO[4]}]
set_property PACKAGE_PIN D6 [get_ports {DB1_GPIO[5]}]
set_property PACKAGE_PIN D10 [get_ports {DB1_GPIO[6]}]
set_property PACKAGE_PIN C10 [get_ports {DB1_GPIO[7]}]
set_property PACKAGE_PIN C8 [get_ports {DB1_GPIO[8]}]
set_property PACKAGE_PIN C7 [get_ports {DB1_GPIO[9]}]
set_property PACKAGE_PIN D9 [get_ports {DB1_GPIO[10]}]
set_property PACKAGE_PIN D8 [get_ports {DB1_GPIO[11]}]
set_property PACKAGE_PIN B8 [get_ports {DB1_GPIO[12]}]
set_property PACKAGE_PIN B7 [get_ports {DB1_GPIO[13]}]
set_property PACKAGE_PIN B10 [get_ports {DB1_GPIO[14]}]
set_property PACKAGE_PIN B9 [get_ports {DB1_GPIO[15]}]
set_property PACKAGE_PIN C6 [get_ports {DB1_GPIO[16]}]
set_property PACKAGE_PIN C5 [get_ports {DB1_GPIO[17]}]
set_property PACKAGE_PIN B5 [get_ports {DB1_GPIO[18]}]
set_property PACKAGE_PIN A5 [get_ports {DB1_GPIO[19]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[0]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[0]}]
set_property IOB TRUE [get_ports {DB1_GPIO[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[1]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[1]}]
set_property IOB TRUE [get_ports {DB1_GPIO[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[2]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[2]}]
set_property IOB TRUE [get_ports {DB1_GPIO[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[3]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[3]}]
set_property IOB TRUE [get_ports {DB1_GPIO[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[4]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[4]}]
set_property IOB TRUE [get_ports {DB1_GPIO[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[5]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[5]}]
set_property IOB TRUE [get_ports {DB1_GPIO[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[6]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[6]}]
set_property IOB TRUE [get_ports {DB1_GPIO[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[7]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[7]}]
set_property IOB TRUE [get_ports {DB1_GPIO[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[8]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[8]}]
set_property IOB TRUE [get_ports {DB1_GPIO[8]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[9]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[9]}]
set_property IOB TRUE [get_ports {DB1_GPIO[9]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[10]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[10]}]
set_property IOB TRUE [get_ports {DB1_GPIO[10]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[11]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[11]}]
set_property IOB TRUE [get_ports {DB1_GPIO[11]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[12]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[12]}]
set_property IOB TRUE [get_ports {DB1_GPIO[12]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[13]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[13]}]
set_property IOB TRUE [get_ports {DB1_GPIO[13]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[14]}]
set_property PULLUP TRUE [get_ports {DB1_GPIO[14]}]
set_property IOB TRUE [get_ports {DB1_GPIO[14]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[15]}]
set_property PULLUP TRUE [get_ports {DB1_GPIO[15]}]
set_property IOB TRUE [get_ports {DB1_GPIO[15]}]
# DB1_GPIO[17] connects to D, DB1_GPIO[16] connects to D#
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[16]}]
set_property PULLDOWN FALSE [get_ports {DB1_GPIO[16]}]
set_property SLEW SLOW [get_ports {DB1_GPIO[16]}]
set_property DRIVE 16 [get_ports {DB1_GPIO[16]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[17]}]
set_property PULLDOWN FALSE [get_ports {DB1_GPIO[17]}]
set_property SLEW SLOW [get_ports {DB1_GPIO[17]}]
set_property DRIVE 16 [get_ports {DB1_GPIO[17]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[18]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[18]}]
set_property IOB TRUE [get_ports {DB1_GPIO[18]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[19]}]
set_property PULLDOWN TRUE [get_ports {DB1_GPIO[19]}]
set_property IOB TRUE [get_ports {DB1_GPIO[19]}]
set_property PACKAGE_PIN AW6 [get_ports {DB0_GPIO[0]}]
set_property PACKAGE_PIN AW5 [get_ports {DB0_GPIO[1]}]
set_property PACKAGE_PIN AW4 [get_ports {DB0_GPIO[2]}]
set_property PACKAGE_PIN AW3 [get_ports {DB0_GPIO[3]}]
set_property PACKAGE_PIN AV3 [get_ports {DB0_GPIO[4]}]
set_property PACKAGE_PIN AV2 [get_ports {DB0_GPIO[5]}]
set_property PACKAGE_PIN AU2 [get_ports {DB0_GPIO[6]}]
set_property PACKAGE_PIN AU1 [get_ports {DB0_GPIO[7]}]
set_property PACKAGE_PIN AV6 [get_ports {DB0_GPIO[8]}]
set_property PACKAGE_PIN AV5 [get_ports {DB0_GPIO[9]}]
set_property PACKAGE_PIN AU4 [get_ports {DB0_GPIO[10]}]
set_property PACKAGE_PIN AU3 [get_ports {DB0_GPIO[11]}]
set_property PACKAGE_PIN AT5 [get_ports {DB0_GPIO[12]}]
set_property PACKAGE_PIN AU5 [get_ports {DB0_GPIO[13]}]
set_property PACKAGE_PIN AT7 [get_ports {DB0_GPIO[14]}]
set_property PACKAGE_PIN AT6 [get_ports {DB0_GPIO[15]}]
set_property PACKAGE_PIN AU8 [get_ports {DB0_GPIO[16]}]
set_property PACKAGE_PIN AV8 [get_ports {DB0_GPIO[17]}]
set_property PACKAGE_PIN AU7 [get_ports {DB0_GPIO[18]}]
set_property PACKAGE_PIN AV7 [get_ports {DB0_GPIO[19]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[0]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[0]}]
set_property IOB TRUE [get_ports {DB0_GPIO[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[1]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[1]}]
set_property IOB TRUE [get_ports {DB0_GPIO[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[2]}]
set_property PULLUP TRUE [get_ports {DB0_GPIO[2]}]
set_property IOB TRUE [get_ports {DB0_GPIO[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[3]}]
set_property PULLUP TRUE [get_ports {DB0_GPIO[3]}]
set_property IOB TRUE [get_ports {DB0_GPIO[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[4]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[4]}]
set_property IOB TRUE [get_ports {DB0_GPIO[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[5]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[5]}]
set_property IOB TRUE [get_ports {DB0_GPIO[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[6]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[6]}]
set_property IOB TRUE [get_ports {DB0_GPIO[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[7]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[7]}]
set_property IOB TRUE [get_ports {DB0_GPIO[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[8]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[8]}]
set_property IOB TRUE [get_ports {DB0_GPIO[8]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[9]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[9]}]
set_property IOB TRUE [get_ports {DB0_GPIO[9]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[10]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[10]}]
set_property IOB TRUE [get_ports {DB0_GPIO[10]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[11]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[11]}]
set_property IOB TRUE [get_ports {DB0_GPIO[11]}]
# DB0_GPIO[13] connects to D, DB0_GPIO[12] connects to D#
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[12]}]
set_property PULLDOWN FALSE [get_ports {DB0_GPIO[12]}]
set_property SLEW SLOW [get_ports {DB0_GPIO[12]}]
set_property DRIVE 16 [get_ports {DB0_GPIO[12]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[13]}]
set_property PULLDOWN FALSE [get_ports {DB0_GPIO[13]}]
set_property SLEW SLOW [get_ports {DB0_GPIO[13]}]
set_property DRIVE 16 [get_ports {DB0_GPIO[13]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[14]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[14]}]
set_property IOB TRUE [get_ports {DB0_GPIO[14]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[15]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[15]}]
set_property IOB TRUE [get_ports {DB0_GPIO[15]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[16]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[16]}]
set_property IOB TRUE [get_ports {DB0_GPIO[16]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[17]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[17]}]
set_property IOB TRUE [get_ports {DB0_GPIO[17]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[18]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[18]}]
set_property IOB TRUE [get_ports {DB0_GPIO[18]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[19]}]
set_property PULLDOWN TRUE [get_ports {DB0_GPIO[19]}]
set_property IOB TRUE [get_ports {DB0_GPIO[19]}]