fpga: Add X440/FBX support
Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
This commit is contained in:
Javier Valenzuela
committed by
Aki Tomita
Aki Tomita
co-authored by
Martin Braun
Wade Fife
Ryan Marlow
Martin Braun
Wade Fife
Ryan Marlow
parent
a405111ce7
commit
5cadf901c7
@@ -26,4 +26,3 @@ set_property PACKAGE_PIN Y36 [get_ports {QSFP1_0_TX_N}]
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set_property PACKAGE_PIN Y31 [get_ports {GTY_RCV_CLK_P}]
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set_property PACKAGE_PIN Y32 [get_ports {GTY_RCV_CLK_N}]
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set_property IOSTANDARD DIFF_SSTL12 [get_ports {GTY_RCV_CLK_*}]
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@@ -0,0 +1,87 @@
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#
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# Copyright 2022 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Description:
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# RF data converters pin constraints for X440.
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# Converter pin mapping can be found at(redirected from UG1075):
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# https://www.xilinx.com/support/packagefiles/zuppackages/xczu28drffvg1517pkg.txt
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#
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# SYSREF input for data converters.
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set_property PACKAGE_PIN U4 [get_ports {SYSREF_RF_N}]
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set_property PACKAGE_PIN U5 [get_ports {SYSREF_RF_P}]
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###############################################################################
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# Pin constraints for the ADCs
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###############################################################################
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# ADC Reference Clocks for Slot 0 (DBA)
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set_property PACKAGE_PIN AF5 [get_ports {ADC_CLK_P[0]}]
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set_property PACKAGE_PIN AF4 [get_ports {ADC_CLK_N[0]}]
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set_property PACKAGE_PIN AD5 [get_ports {ADC_CLK_P[1]}]
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set_property PACKAGE_PIN AD4 [get_ports {ADC_CLK_N[1]}]
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# ADC Reference Clocks for Slot 1 (DBB)
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set_property PACKAGE_PIN AB5 [get_ports {ADC_CLK_P[2]}]
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set_property PACKAGE_PIN AB4 [get_ports {ADC_CLK_N[2]}]
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set_property PACKAGE_PIN Y5 [get_ports {ADC_CLK_P[3]}]
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set_property PACKAGE_PIN Y4 [get_ports {ADC_CLK_N[3]}]
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# ADC Inputs for Slot 0 (DBA)
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# Note: numbering here does NOT match schematic, but it is the right order
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# according to RF BD Connection spec.
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set_property PACKAGE_PIN AH2 [get_ports {DB0_RX_P[3]}]
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set_property PACKAGE_PIN AH1 [get_ports {DB0_RX_N[3]}]
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set_property PACKAGE_PIN AK2 [get_ports {DB0_RX_P[2]}]
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set_property PACKAGE_PIN AK1 [get_ports {DB0_RX_N[2]}]
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set_property PACKAGE_PIN AM2 [get_ports {DB0_RX_P[1]}]
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set_property PACKAGE_PIN AM1 [get_ports {DB0_RX_N[1]}]
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set_property PACKAGE_PIN AP2 [get_ports {DB0_RX_P[0]}]
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set_property PACKAGE_PIN AP1 [get_ports {DB0_RX_N[0]}]
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# ADC Inputs for Slot 1 (DBB)
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# Note: numbering here does NOT match schematic, but it is the right order
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# according to RF BD Connection spec.
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set_property PACKAGE_PIN Y2 [get_ports {DB1_RX_P[3]}]
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set_property PACKAGE_PIN Y1 [get_ports {DB1_RX_N[3]}]
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set_property PACKAGE_PIN AB2 [get_ports {DB1_RX_P[2]}]
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set_property PACKAGE_PIN AB1 [get_ports {DB1_RX_N[2]}]
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set_property PACKAGE_PIN AD2 [get_ports {DB1_RX_P[1]}]
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set_property PACKAGE_PIN AD1 [get_ports {DB1_RX_N[1]}]
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set_property PACKAGE_PIN AF2 [get_ports {DB1_RX_P[0]}]
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set_property PACKAGE_PIN AF1 [get_ports {DB1_RX_N[0]}]
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###############################################################################
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# Pin constraints for the DACs
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###############################################################################
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# DAC Reference Clock for Slot 0 (DBA)
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set_property PACKAGE_PIN R5 [get_ports {DAC_CLK_P[0]}]
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set_property PACKAGE_PIN R4 [get_ports {DAC_CLK_N[0]}]
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# DAC Reference Clock for Slot 1 (DBB)
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set_property PACKAGE_PIN N5 [get_ports {DAC_CLK_P[1]}]
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set_property PACKAGE_PIN N4 [get_ports {DAC_CLK_N[1]}]
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# DAC Outputs for Slot 0 (DBA)
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set_property PACKAGE_PIN U2 [get_ports {DB0_TX_P[0]}]
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set_property PACKAGE_PIN U1 [get_ports {DB0_TX_N[0]}]
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set_property PACKAGE_PIN R2 [get_ports {DB0_TX_P[1]}]
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set_property PACKAGE_PIN R1 [get_ports {DB0_TX_N[1]}]
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set_property PACKAGE_PIN N2 [get_ports {DB0_TX_P[2]}]
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set_property PACKAGE_PIN N1 [get_ports {DB0_TX_N[2]}]
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set_property PACKAGE_PIN L2 [get_ports {DB0_TX_P[3]}]
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set_property PACKAGE_PIN L1 [get_ports {DB0_TX_N[3]}]
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# DAC Outputs for Slot 1 (DBB)
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set_property PACKAGE_PIN J2 [get_ports {DB1_TX_P[0]}]
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set_property PACKAGE_PIN J1 [get_ports {DB1_TX_N[0]}]
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set_property PACKAGE_PIN G2 [get_ports {DB1_TX_P[1]}]
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set_property PACKAGE_PIN G1 [get_ports {DB1_TX_N[1]}]
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set_property PACKAGE_PIN E2 [get_ports {DB1_TX_P[2]}]
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set_property PACKAGE_PIN E1 [get_ports {DB1_TX_N[2]}]
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set_property PACKAGE_PIN C2 [get_ports {DB1_TX_P[3]}]
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set_property PACKAGE_PIN C1 [get_ports {DB1_TX_N[3]}]
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@@ -0,0 +1,180 @@
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#
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# Copyright 2022 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Description:
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# DB GPIO pin constraints for X440.
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#
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###############################################################################
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# Pin constraints for the other PL pins (1.8 V)
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###############################################################################
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set_property PACKAGE_PIN F6 [get_ports {DB1_GPIO[0]}]
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set_property PACKAGE_PIN E6 [get_ports {DB1_GPIO[1]}]
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set_property PACKAGE_PIN E9 [get_ports {DB1_GPIO[2]}]
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set_property PACKAGE_PIN E8 [get_ports {DB1_GPIO[3]}]
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set_property PACKAGE_PIN E7 [get_ports {DB1_GPIO[4]}]
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set_property PACKAGE_PIN D6 [get_ports {DB1_GPIO[5]}]
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set_property PACKAGE_PIN D10 [get_ports {DB1_GPIO[6]}]
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set_property PACKAGE_PIN C10 [get_ports {DB1_GPIO[7]}]
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set_property PACKAGE_PIN C8 [get_ports {DB1_GPIO[8]}]
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set_property PACKAGE_PIN C7 [get_ports {DB1_GPIO[9]}]
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set_property PACKAGE_PIN D9 [get_ports {DB1_GPIO[10]}]
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set_property PACKAGE_PIN D8 [get_ports {DB1_GPIO[11]}]
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set_property PACKAGE_PIN B8 [get_ports {DB1_GPIO[12]}]
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set_property PACKAGE_PIN B7 [get_ports {DB1_GPIO[13]}]
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set_property PACKAGE_PIN B10 [get_ports {DB1_GPIO[14]}]
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set_property PACKAGE_PIN B9 [get_ports {DB1_GPIO[15]}]
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set_property PACKAGE_PIN C6 [get_ports {DB1_GPIO[16]}]
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set_property PACKAGE_PIN C5 [get_ports {DB1_GPIO[17]}]
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set_property PACKAGE_PIN B5 [get_ports {DB1_GPIO[18]}]
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set_property PACKAGE_PIN A5 [get_ports {DB1_GPIO[19]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[0]}]
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set_property PULLDOWN TRUE [get_ports {DB1_GPIO[0]}]
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set_property IOB TRUE [get_ports {DB1_GPIO[0]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[1]}]
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set_property PULLDOWN TRUE [get_ports {DB1_GPIO[1]}]
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set_property IOB TRUE [get_ports {DB1_GPIO[1]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[2]}]
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set_property PULLDOWN TRUE [get_ports {DB1_GPIO[2]}]
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set_property IOB TRUE [get_ports {DB1_GPIO[2]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[3]}]
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set_property PULLDOWN TRUE [get_ports {DB1_GPIO[3]}]
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set_property IOB TRUE [get_ports {DB1_GPIO[3]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[4]}]
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set_property PULLDOWN TRUE [get_ports {DB1_GPIO[4]}]
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set_property IOB TRUE [get_ports {DB1_GPIO[4]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[5]}]
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set_property PULLDOWN TRUE [get_ports {DB1_GPIO[5]}]
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set_property IOB TRUE [get_ports {DB1_GPIO[5]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[6]}]
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set_property PULLDOWN TRUE [get_ports {DB1_GPIO[6]}]
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set_property IOB TRUE [get_ports {DB1_GPIO[6]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[7]}]
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set_property PULLDOWN TRUE [get_ports {DB1_GPIO[7]}]
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set_property IOB TRUE [get_ports {DB1_GPIO[7]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[8]}]
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set_property PULLDOWN TRUE [get_ports {DB1_GPIO[8]}]
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set_property IOB TRUE [get_ports {DB1_GPIO[8]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[9]}]
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set_property PULLDOWN TRUE [get_ports {DB1_GPIO[9]}]
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set_property IOB TRUE [get_ports {DB1_GPIO[9]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[10]}]
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set_property PULLDOWN TRUE [get_ports {DB1_GPIO[10]}]
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set_property IOB TRUE [get_ports {DB1_GPIO[10]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[11]}]
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set_property PULLDOWN TRUE [get_ports {DB1_GPIO[11]}]
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set_property IOB TRUE [get_ports {DB1_GPIO[11]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[12]}]
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set_property PULLDOWN TRUE [get_ports {DB1_GPIO[12]}]
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set_property IOB TRUE [get_ports {DB1_GPIO[12]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[13]}]
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set_property PULLDOWN TRUE [get_ports {DB1_GPIO[13]}]
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set_property IOB TRUE [get_ports {DB1_GPIO[13]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[14]}]
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set_property PULLUP TRUE [get_ports {DB1_GPIO[14]}]
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set_property IOB TRUE [get_ports {DB1_GPIO[14]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[15]}]
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set_property PULLUP TRUE [get_ports {DB1_GPIO[15]}]
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set_property IOB TRUE [get_ports {DB1_GPIO[15]}]
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# DB1_GPIO[17] connects to D, DB1_GPIO[16] connects to D#
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set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[16]}]
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set_property PULLDOWN FALSE [get_ports {DB1_GPIO[16]}]
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set_property SLEW SLOW [get_ports {DB1_GPIO[16]}]
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set_property DRIVE 16 [get_ports {DB1_GPIO[16]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[17]}]
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set_property PULLDOWN FALSE [get_ports {DB1_GPIO[17]}]
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set_property SLEW SLOW [get_ports {DB1_GPIO[17]}]
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set_property DRIVE 16 [get_ports {DB1_GPIO[17]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[18]}]
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set_property PULLDOWN TRUE [get_ports {DB1_GPIO[18]}]
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set_property IOB TRUE [get_ports {DB1_GPIO[18]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[19]}]
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set_property PULLDOWN TRUE [get_ports {DB1_GPIO[19]}]
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set_property IOB TRUE [get_ports {DB1_GPIO[19]}]
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set_property PACKAGE_PIN AW6 [get_ports {DB0_GPIO[0]}]
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set_property PACKAGE_PIN AW5 [get_ports {DB0_GPIO[1]}]
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set_property PACKAGE_PIN AW4 [get_ports {DB0_GPIO[2]}]
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set_property PACKAGE_PIN AW3 [get_ports {DB0_GPIO[3]}]
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set_property PACKAGE_PIN AV3 [get_ports {DB0_GPIO[4]}]
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set_property PACKAGE_PIN AV2 [get_ports {DB0_GPIO[5]}]
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set_property PACKAGE_PIN AU2 [get_ports {DB0_GPIO[6]}]
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set_property PACKAGE_PIN AU1 [get_ports {DB0_GPIO[7]}]
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set_property PACKAGE_PIN AV6 [get_ports {DB0_GPIO[8]}]
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set_property PACKAGE_PIN AV5 [get_ports {DB0_GPIO[9]}]
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set_property PACKAGE_PIN AU4 [get_ports {DB0_GPIO[10]}]
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set_property PACKAGE_PIN AU3 [get_ports {DB0_GPIO[11]}]
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set_property PACKAGE_PIN AT5 [get_ports {DB0_GPIO[12]}]
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set_property PACKAGE_PIN AU5 [get_ports {DB0_GPIO[13]}]
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set_property PACKAGE_PIN AT7 [get_ports {DB0_GPIO[14]}]
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set_property PACKAGE_PIN AT6 [get_ports {DB0_GPIO[15]}]
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set_property PACKAGE_PIN AU8 [get_ports {DB0_GPIO[16]}]
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set_property PACKAGE_PIN AV8 [get_ports {DB0_GPIO[17]}]
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set_property PACKAGE_PIN AU7 [get_ports {DB0_GPIO[18]}]
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set_property PACKAGE_PIN AV7 [get_ports {DB0_GPIO[19]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[0]}]
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set_property PULLDOWN TRUE [get_ports {DB0_GPIO[0]}]
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set_property IOB TRUE [get_ports {DB0_GPIO[0]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[1]}]
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set_property PULLDOWN TRUE [get_ports {DB0_GPIO[1]}]
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set_property IOB TRUE [get_ports {DB0_GPIO[1]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[2]}]
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set_property PULLUP TRUE [get_ports {DB0_GPIO[2]}]
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set_property IOB TRUE [get_ports {DB0_GPIO[2]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[3]}]
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set_property PULLUP TRUE [get_ports {DB0_GPIO[3]}]
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set_property IOB TRUE [get_ports {DB0_GPIO[3]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[4]}]
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set_property PULLDOWN TRUE [get_ports {DB0_GPIO[4]}]
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set_property IOB TRUE [get_ports {DB0_GPIO[4]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[5]}]
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set_property PULLDOWN TRUE [get_ports {DB0_GPIO[5]}]
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set_property IOB TRUE [get_ports {DB0_GPIO[5]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[6]}]
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set_property PULLDOWN TRUE [get_ports {DB0_GPIO[6]}]
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set_property IOB TRUE [get_ports {DB0_GPIO[6]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[7]}]
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set_property PULLDOWN TRUE [get_ports {DB0_GPIO[7]}]
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set_property IOB TRUE [get_ports {DB0_GPIO[7]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[8]}]
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set_property PULLDOWN TRUE [get_ports {DB0_GPIO[8]}]
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set_property IOB TRUE [get_ports {DB0_GPIO[8]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[9]}]
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set_property PULLDOWN TRUE [get_ports {DB0_GPIO[9]}]
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set_property IOB TRUE [get_ports {DB0_GPIO[9]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[10]}]
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set_property PULLDOWN TRUE [get_ports {DB0_GPIO[10]}]
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set_property IOB TRUE [get_ports {DB0_GPIO[10]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[11]}]
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set_property PULLDOWN TRUE [get_ports {DB0_GPIO[11]}]
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set_property IOB TRUE [get_ports {DB0_GPIO[11]}]
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# DB0_GPIO[13] connects to D, DB0_GPIO[12] connects to D#
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set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[12]}]
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set_property PULLDOWN FALSE [get_ports {DB0_GPIO[12]}]
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set_property SLEW SLOW [get_ports {DB0_GPIO[12]}]
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set_property DRIVE 16 [get_ports {DB0_GPIO[12]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[13]}]
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set_property PULLDOWN FALSE [get_ports {DB0_GPIO[13]}]
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set_property SLEW SLOW [get_ports {DB0_GPIO[13]}]
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set_property DRIVE 16 [get_ports {DB0_GPIO[13]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[14]}]
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set_property PULLDOWN TRUE [get_ports {DB0_GPIO[14]}]
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set_property IOB TRUE [get_ports {DB0_GPIO[14]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[15]}]
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set_property PULLDOWN TRUE [get_ports {DB0_GPIO[15]}]
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set_property IOB TRUE [get_ports {DB0_GPIO[15]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[16]}]
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set_property PULLDOWN TRUE [get_ports {DB0_GPIO[16]}]
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set_property IOB TRUE [get_ports {DB0_GPIO[16]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[17]}]
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set_property PULLDOWN TRUE [get_ports {DB0_GPIO[17]}]
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set_property IOB TRUE [get_ports {DB0_GPIO[17]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[18]}]
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set_property PULLDOWN TRUE [get_ports {DB0_GPIO[18]}]
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set_property IOB TRUE [get_ports {DB0_GPIO[18]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[19]}]
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set_property PULLDOWN TRUE [get_ports {DB0_GPIO[19]}]
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set_property IOB TRUE [get_ports {DB0_GPIO[19]}]
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@@ -0,0 +1,124 @@
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#
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# Copyright 2022 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Description:
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# Timing constraints exclusive to X440. These should be used
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# in conjunction with ./common.xdc
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#
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###############################################################################
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# DB GPIO
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# This interface is defined as system synchronous to pll_ref_clk.
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# Some timing constants in this section are declared in
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# <repo>/fpga/usrp3/top/x400/constraints/timing/shared_constants.sdc
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###############################################################################
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# In the current db_gpio_interface implementation, all GPIOs are received asynchronously
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# by the DB, so we add a very relax constraint for these signals.
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set db_gpio_min 0
|
||||
set db_gpio_max [expr {$pll_ref_clk_period/2}]
|
||||
set db_gpio_sync_max 3.500
|
||||
|
||||
# Set constraints for all ports.
|
||||
set db_gpio_ports [get_ports {DB0_GPIO[*] DB1_GPIO[*]}]
|
||||
set db_gpio_sync_ports [get_ports {DB0_GPIO[12] DB0_GPIO[13] DB1_GPIO[16] DB1_GPIO[17]}]
|
||||
|
||||
set_output_delay -clock [get_clocks pll_ref_clk] -min $db_gpio_min $db_gpio_ports
|
||||
set_output_delay -clock [get_clocks pll_ref_clk] -max $db_gpio_max $db_gpio_ports
|
||||
# Should just overwrite the setting for the sync clock ports that are also in db_gpio_ports
|
||||
set_output_delay -clock [get_clocks ref_clk] -max $db_gpio_sync_max $db_gpio_sync_ports
|
||||
|
||||
set_input_delay -clock [get_clocks pll_ref_clk] -max $db_gpio_min $db_gpio_ports
|
||||
set_input_delay -clock [get_clocks pll_ref_clk] -min $db_gpio_max $db_gpio_ports
|
||||
|
||||
# Use multi cycle path constraint to relax timing on these pins.
|
||||
set_multicycle_path -setup 2 -from [get_pins db_gpio_gen[*].db_gpio_interface_i/ctrlport_to_i2c_inst/i2c_master/byte_controller/bit_controller/*_oen_reg/C]
|
||||
set_multicycle_path -end -hold 7 -from [get_pins db_gpio_gen[*].db_gpio_interface_i/ctrlport_to_i2c_inst/i2c_master/byte_controller/bit_controller/*_oen_reg/C]
|
||||
###############################################################################
|
||||
# x440_ps_rfdc_bd
|
||||
###############################################################################
|
||||
|
||||
# This property tells Vivado that we require these clocks to be well aligned.
|
||||
# We have synchronous clock domain crossings between these clocks that can have
|
||||
# large hold violations after placement due to uneven clock loading.
|
||||
set_property CLOCK_DELAY_GROUP DataClkGroup [get_nets -hier -filter {\
|
||||
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk ||\
|
||||
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk_2x ||\
|
||||
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/pll_ref_clk_out ||\
|
||||
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/radio0_rfdc_clk ||\
|
||||
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/radio0_rfdc_clk_2x ||\
|
||||
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/radio1_rfdc_clk ||\
|
||||
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/radio1_rfdc_clk_2x \
|
||||
}]
|
||||
|
||||
# We treat rfdc_clk buffers as asynchronous, with knowledge that
|
||||
# code clocked in this domain will be reset after this clocked is enabled. This
|
||||
# will make timing easier to meet on these clock domains.
|
||||
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdc0Bufg1x*/C}] \
|
||||
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rf0_clk_1x_buf/*BUFGCE*/CE}]
|
||||
|
||||
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdc0Bufg2x*/C}] \
|
||||
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rf0_clk_2x_buf/*BUFGCE*/CE}]
|
||||
|
||||
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdc1Bufg1x*/C}] \
|
||||
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rf1_clk_1x_buf/*BUFGCE*/CE}]
|
||||
|
||||
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdc1Bufg2x*/C}] \
|
||||
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rf1_clk_2x_buf/*BUFGCE*/CE}]
|
||||
|
||||
|
||||
###############################################################################
|
||||
# SPLL SYSREF Capture
|
||||
###############################################################################
|
||||
|
||||
# SYSREF is generated by the LMK04832 clocking chip (SPLL), which also produces
|
||||
# the PLL reference clock (PRC) used to generate data clocks with a MMCM. Both
|
||||
# SYSREF and PLL reference clock are directly fed into the RFSoC.
|
||||
# SYSREF is captured by the FPGA fabric in the PRC clock domain (MMCM's PRC
|
||||
# output) with a double synchronizer and then transfered to the RFDC clock
|
||||
# domain. Both SYSREF versions (PRC and RFDC) are used by downstream logic for
|
||||
# sync. purposes.
|
||||
# SYSREF is a continuous signal intentionally shifted in the LMK chip to align
|
||||
# it closer to the PRC's falling edge.
|
||||
# The highest PRC frequency supported in MPM (64 MHz) is used for
|
||||
# timing constraints. Therefore, SYSREF LMK's delay = (1/64e6)/2.
|
||||
set sysref_lmk_delay 7.8125
|
||||
#
|
||||
# These are the signals' lengths and corresponding delays (assuming 170 ps/in):
|
||||
# - SYSREF --> 5794 mils (5.794 inches) = 0.985 ns
|
||||
# - PRC --> 5668 mils (5.668 inches) = 0.964 ns
|
||||
#
|
||||
# For min/max input delay calculations, it is assumed min prop. delay of 0 ns,
|
||||
# which essentially over-constrains SYSREF.
|
||||
#
|
||||
# The max input delay is the latest that SYSREF may arrive w.r.t PRC, and it is
|
||||
# calculated as follows:
|
||||
# Input delay (max) = SYSREF's LMK delay + SYSREF prop. delay (max)
|
||||
# - PRC prop. delay (min)
|
||||
set sysref_max_input_delay [expr {$sysref_lmk_delay + 0.985 - 0}]
|
||||
#
|
||||
# The min input delay is the earliest that SYSREF may arrive w.r.t PRC, and it
|
||||
# is calculated as follows:
|
||||
# Input delay (min) = SYSREF's LMK delay + SYSREF prop. delay (min)
|
||||
# - PRC prop. delay (min)
|
||||
set sysref_min_input_delay [expr {$sysref_lmk_delay + 0 - 0.964}]
|
||||
|
||||
set_input_delay -clock pll_ref_clk -max $sysref_max_input_delay [get_ports {SYSREF_FABRIC_P}]
|
||||
set_input_delay -clock pll_ref_clk -min $sysref_min_input_delay [get_ports {SYSREF_FABRIC_P}]
|
||||
|
||||
###############################################################################
|
||||
# SPI to MB CPLD (PL)
|
||||
# This interface is defined as system synchronous to pll_ref_clk.
|
||||
###############################################################################
|
||||
|
||||
# The output delays are chosen to allow a large time window of valid data for
|
||||
# the MB CPLD logic.
|
||||
set spi_min_out_delay -1.500
|
||||
set spi_max_out_delay 9.500
|
||||
|
||||
# Set output constraints for all ports.
|
||||
set spi_out_ports [get_ports {PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_CS0_n PL_CPLD_CS1_n}]
|
||||
set_output_delay -clock [get_clocks pll_ref_clk] -min $spi_min_out_delay $spi_out_ports
|
||||
set_output_delay -clock [get_clocks pll_ref_clk] -max $spi_max_out_delay $spi_out_ports
|
||||
@@ -0,0 +1,37 @@
|
||||
#
|
||||
# Copyright 2022 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
||||
# Description:
|
||||
# Clock definition constraints for X440
|
||||
#
|
||||
|
||||
###############################################################################
|
||||
# MMCM-Related Clocks
|
||||
#
|
||||
# Note: Vivado will create generated clocks based on the default MMCM settings
|
||||
# configured in the clocking wizard, but we are going to dynamically change
|
||||
# those clocks, and so we need to provide worst-case values in here.
|
||||
###############################################################################
|
||||
|
||||
# PLL Reference Clock (PRC) input. This goes from the LMK straight to the MMCM
|
||||
# input, and is used to generate the internal PRC as well as RFDC/data clocks.
|
||||
set pll_ref_clk_in_period 15.625
|
||||
create_clock -name pll_ref_in_clk -period $pll_ref_clk_in_period [get_ports PLL_REFCLK_FPGA_P]
|
||||
|
||||
# Internal PLL Reference Clock (PRC). Used to derive data clocks. Constrain to
|
||||
# the fastest possible clock rate supported in the driver.
|
||||
set pll_ref_clk_period 15.625
|
||||
create_clock -name pll_ref_clk \
|
||||
-period $pll_ref_clk_period \
|
||||
[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT0]
|
||||
|
||||
###############################################################################
|
||||
# Generated Clocks
|
||||
###############################################################################
|
||||
|
||||
create_generated_clock -name sync_ref_clk \
|
||||
-source [get_ports BASE_REFCLK_FPGA_P] \
|
||||
-divide_by 2 [get_pins clock_div_5mhz/clk_out_reg/Q]
|
||||
|
||||
@@ -0,0 +1,20 @@
|
||||
#
|
||||
# Copyright 2023 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
||||
# Description:
|
||||
# Clock definition constraints for X440 1600 type images
|
||||
#
|
||||
|
||||
# Data clocks: Generated by the MMCM, used for data paths between the RFDC output
|
||||
# and RFNoC. Maximum supported master clock rate is 2.048 Gsps @8SPC => 256 MHz.
|
||||
set rfdc_data_clk_period 3.906
|
||||
|
||||
create_clock -name rfdc_r0_clk -add \
|
||||
-period $rfdc_data_clk_period \
|
||||
[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT2]
|
||||
create_clock -name rfdc_r1_clk -add \
|
||||
-period $rfdc_data_clk_period \
|
||||
[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT5]
|
||||
|
||||
@@ -0,0 +1,21 @@
|
||||
#
|
||||
# Copyright 2023 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
||||
# Description:
|
||||
# Clock definition constraints for X440 400 type images
|
||||
#
|
||||
|
||||
# Data clocks: Generated by the MMCM, used for data paths between the RFDC output
|
||||
# and RFNoC. Maximum supported master clock rate is 500 Msps @8SPC => 62.5 MHz.
|
||||
# Theoretical maximum converter rate is 4.096 GSps, so really, 512 Msps @ 8SPC => 64 MHz.
|
||||
set rfdc_data_clk_period 15.625
|
||||
|
||||
create_clock -name rfdc_r0_clk -add \
|
||||
-period $rfdc_data_clk_period \
|
||||
[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT2]
|
||||
create_clock -name rfdc_r1_clk -add \
|
||||
-period $rfdc_data_clk_period \
|
||||
[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT5]
|
||||
|
||||
Reference in New Issue
Block a user