sim: Update chdr_16sc_to_sc12 testbench

Modified to send 2 packets back to back at each packet size to test
output during sequential input packets.  Also fixed whitespace.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 439770b964be45e6160cf99a0b1551fdd2002fa9

lib/vita_200/chdr_16sc_to_12sc_tb.v

@@ -51,14 +51,15 @@ module chdr_16sc_to_12sc_tb();
   reg [63:0]  data[0:7];
   initial $readmemh("from16_to_x.hex", data);
 
-   //test packet loop
+  //test packets loop
-   task test_packet;
+  task test_packets;
      input [15:0] len;
      input [31:0] sid;
      reg [1:0]    index;
       
      begin
        index <= 0;
+       //first packet
        @(posedge clk) ;
        //send header
        i_tdata = {1'b0, 1'b0, 1'b1, 1'b0, 12'h0, len + 16'd16,sid};
@@ -77,31 +78,55 @@ module chdr_16sc_to_12sc_tb();
          begin
            i_tdata <= {data[index]}; 
            index <= index+1;
-	      //while (i_tready != 1)
-		//@(posedge clk);
            @(posedge clk);
            while (i_tready != 1)
              @(posedge clk);
-	      
       end
       i_tlast <= 1'b1;
       i_tdata <= {data[index]}; 
 
       @(posedge clk);
+	 
+      // second packet
+      index <= 0;
+      //send header 
+      i_tdata = {1'b0, 1'b0, 1'b1, 1'b0, 12'h0, len + 16'd16,sid};
+      i_tvalid <= 1;
+      i_tlast <= 0;
+      @(posedge clk);
+      while (i_tready != 1)
+        @(posedge clk);
+      i_tdata <= {64'b0};
+      @(posedge clk);
+      while (i_tready != 1)
+        @(posedge clk);
+
+      //-1 for last bit accounting
+      repeat (len[15:3] + (len[2]|len[1]|len[0]) - 1)
+      begin
+        i_tdata <= {data[index]}; 
+        index <= index+1;
+        @(posedge clk);
+          while (i_tready != 1)
+        @(posedge clk);
+      end
+      i_tlast <= 1'b1;
+      i_tdata <= {data[index]};
+      @(posedge clk);
+
       while (i_tready != 1)
         @(posedge clk);
 	 
       i_tvalid <= 0;
+      i_tlast <= 0;
     end
   endtask // test_packet
 
   //test_destination loop
-
   task test_destination;
     input enable;
     input [15:0] dest_home;
 
-      
     begin
       @(posedge clk);
 
@@ -115,9 +140,6 @@ module chdr_16sc_to_12sc_tb();
   endtask
 
 
-
-   
-   
   //main loop	
   initial
     begin
@@ -130,41 +152,41 @@ module chdr_16sc_to_12sc_tb();
       @(posedge clk);
       @(posedge clk);
 
-//end on line one
+      //Set SID
-//1
       test_destination(1,16'hFEED);
-	test_packet(4, 32'hDEAD_BEEF);
-//2
-	test_destination(1,16'hFEED);
-	test_packet(8, 32'hDEAD_BEEF);
-//3
-	test_destination(1,16'hFEED);
-	test_packet(12, 32'hDEAD_BEEF);
-//4
 
-	test_destination(1,16'hFEED);
+      //1 sample
-	test_packet(16, 32'hDEAD_BEEF);
+      test_destination(1,16'h1111);
-//5
+      test_packets(4, 32'hDEAD_BEEF);
-	test_destination(1,16'hFEED);
-	test_packet(20, 32'hDEAD_BEEF);
-//6
-	test_destination(1,16'hFEED);
-	test_packet(24, 32'hDEAD_BEEF);
 
-//end on line two 
+      //2 samples
+      test_destination(1,16'h2222);
+      test_packets(8, 32'hDEAD_BEEF);
 
-//7
+      //3 samples
+      test_destination(1,16'h3333);
+      test_packets(12, 32'hDEAD_BEEF);
 
-	test_destination(1,16'hFEED);
+      //4 samples
-	test_packet(28, 32'hDEAD_BEEF);
+      test_destination(1,16'h4444);
-//8
+      test_packets(16, 32'hDEAD_BEEF);
 
-	test_destination(1,16'hFEED);
+      //5 samples
-	test_packet(32, 32'hDEAD_BEEF);
+      test_destination(1,16'h5555);
+      test_packets(20, 32'hDEAD_BEEF);
 
+      //6 samples
+      test_destination(1,16'h6666);
+      test_packets(24, 32'hDEAD_BEEF);
+
+      //7 samples
+      test_destination(1,16'h7777);
+      test_packets(28, 32'hDEAD_BEEF);
+
+      //8 samples
+      test_destination(1,16'h8888);
+      test_packets(32, 32'hDEAD_BEEF);
 
     end
 
-
-
 endmodule