b200: import original Kintex-7 clone port
This commit is contained in:
@@ -0,0 +1 @@
|
||||
`define TARGET_B210
|
||||
+72
-25
@@ -16,10 +16,10 @@ module b200 (
|
||||
output cat_mosi,
|
||||
output cat_sclk,
|
||||
|
||||
input fx3_ce,
|
||||
output fx3_miso,
|
||||
input fx3_mosi,
|
||||
input fx3_sclk,
|
||||
// input fx3_ce,
|
||||
// output fx3_miso,
|
||||
// input fx3_mosi,
|
||||
// input fx3_sclk,
|
||||
|
||||
output pll_ce,
|
||||
output pll_mosi,
|
||||
@@ -58,8 +58,8 @@ module b200 (
|
||||
input codec_main_clk_n,
|
||||
|
||||
// Debug Bus
|
||||
output [31:0] debug,
|
||||
output [1:0] debug_clk,
|
||||
// output [31:0] debug,
|
||||
// output [1:0] debug_clk,
|
||||
|
||||
// GPIF, FX3 Slave FIFO
|
||||
output IFCLK, // pclk
|
||||
@@ -79,10 +79,10 @@ module b200 (
|
||||
input GPIF_CTL9, // global_reset
|
||||
|
||||
// GPS
|
||||
input gps_lock,
|
||||
output gps_rxd,
|
||||
input gps_txd, // FPGA has pullup for unpopulated GPS
|
||||
input gps_txd_nmea, // FPGA has pullup for unpopulated GPS
|
||||
// input gps_lock,
|
||||
// output gps_rxd,
|
||||
// input gps_txd, // FPGA has pullup for unpopulated GPS
|
||||
// input gps_txd_nmea, // FPGA has pullup for unpopulated GPS
|
||||
|
||||
// LEDS
|
||||
output LED_RX1,
|
||||
@@ -102,8 +102,8 @@ module b200 (
|
||||
// Misc Hardware Control
|
||||
output ref_sel,
|
||||
input pll_lock,
|
||||
input FPGA_CFG_CS, // Driven by FX3 gpio.
|
||||
input AUX_PWR_ON, // Driven by FX3 gpio.
|
||||
// input FPGA_CFG_CS, // Driven by FX3 gpio.
|
||||
// input AUX_PWR_ON, // Driven by FX3 gpio.
|
||||
|
||||
// PPS
|
||||
input PPS_IN_EXT,
|
||||
@@ -124,9 +124,14 @@ module b200 (
|
||||
output tx_enable2,
|
||||
output rx_bandsel_a,
|
||||
output rx_bandsel_b,
|
||||
output rx_bandsel_c
|
||||
output rx_bandsel_c,
|
||||
|
||||
output LED_STATUS,
|
||||
output LED_CLK_G,
|
||||
output LED_CLK_R
|
||||
);
|
||||
|
||||
|
||||
wire reset_global = GPIF_CTL9;
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
@@ -136,9 +141,13 @@ module b200 (
|
||||
wire locked;
|
||||
b200_clk_gen gen_clks
|
||||
(
|
||||
.CLK_IN1_40_P(codec_main_clk_p), .CLK_IN1_40_N(codec_main_clk_n),
|
||||
.CLK_OUT1_40_int(), .CLK_OUT2_100_gpif(gpif_clk), .CLK_OUT3_100_bus(),
|
||||
.RESET(reset_global), .LOCKED(locked)
|
||||
.clk_in1_p(codec_main_clk_p),
|
||||
.clk_in1_n(codec_main_clk_n),
|
||||
.CLK_OUT1_40_int(),
|
||||
.CLK_OUT2_100_gpif(gpif_clk),
|
||||
.CLK_OUT3_100_bus(),
|
||||
.reset(reset_global),
|
||||
.locked(locked)
|
||||
);
|
||||
|
||||
// Bus Clock and GPIF Clock both same 100MHz clock.
|
||||
@@ -165,8 +174,27 @@ module b200 (
|
||||
wire [1:0] debug_clk_int;
|
||||
//S6CLK2PIN S6CLK2PIN_dbg0 (.I(debug_clk_int[0]), .O(debug_clk[0]));
|
||||
//S6CLK2PIN S6CLK2PIN_dbg1 (.I(debug_clk_int[1]), .O(debug_clk[1]));
|
||||
assign debug_clk[1:0] = 2'b0;
|
||||
S6CLK2PIN S6CLK2PIN_gpif (.I(gpif_clk), .O(IFCLK));
|
||||
// assign debug_clk[1:0] = 2'b0;
|
||||
// S6CLK2PIN S6CLK2PIN_gpif (.I(gpif_clk), .O(IFCLK));
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// drive output clocks
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
ODDR #(
|
||||
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
|
||||
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
|
||||
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
||||
)
|
||||
ODDR_U
|
||||
(
|
||||
.Q(IFCLK), // 1-bit DDR output data
|
||||
.C(gpif_clk), // 1-bit clock input
|
||||
.CE(1'b1), // 1-bit clock enable input
|
||||
.D1(1'b1), // 1-bit data input (associated with C0)
|
||||
.D2(1'b0), // 1-bit data input (associated with C1)
|
||||
.R(1'b0), // 1-bit reset input
|
||||
.S(1'b0) // 1-bit set input
|
||||
);
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// Create sync reset signals
|
||||
@@ -176,6 +204,19 @@ module b200 (
|
||||
reset_sync bus_sync(.clk(bus_clk), .reset_in(!clocks_ready), .reset_out(bus_rst));
|
||||
reset_sync radio_sync(.clk(radio_clk), .reset_in(!clocks_ready), .reset_out(radio_rst));
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// PPS Switch 1.GPS_PPS 2.EXT_PPS
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
wire pps_ext_int;
|
||||
pps_switch u_pps_switch (
|
||||
.clk (gpif_clk),
|
||||
.rst_n (!gpif_rst),
|
||||
.gps_pps (PPS_IN_INT),
|
||||
.ext_pps (PPS_IN_EXT),
|
||||
.pps_out (pps_ext_int)
|
||||
);
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// I/O
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
@@ -185,11 +226,12 @@ module b200 (
|
||||
|
||||
b200_io b200_io_i0
|
||||
(
|
||||
.reset(reset),
|
||||
.areset(reset_global),
|
||||
.mimo(mimo),
|
||||
|
||||
// Baseband sample interface
|
||||
.radio_clk(radio_clk),
|
||||
// .radio_rst(radio_rst),
|
||||
|
||||
.rx_i0(rx_data0[31:20]),
|
||||
.rx_q0(rx_data0[15:4]),
|
||||
@@ -234,7 +276,7 @@ module b200 (
|
||||
//The following signals are routed to the FX3 and were used by an obsolete
|
||||
//bit-banging SPI engine.
|
||||
// fx3_ce, fx3_sclk, fx3_mosi <Unused>
|
||||
assign fx3_miso = 1'bZ; //Safe state because we cannot guarantee the
|
||||
// assign fx3_miso = 1'bZ; //Safe state because we cannot guarantee the
|
||||
//direction of this pin in the FX3
|
||||
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
@@ -294,10 +336,10 @@ module b200 (
|
||||
.tx0(tx_data0), .tx1(tx_data1),
|
||||
.fe0_gpio_out(radio0_gpio), .fe1_gpio_out(radio1_gpio),
|
||||
.fp_gpio_in(fp_gpio_in), .fp_gpio_out(fp_gpio_out), .fp_gpio_ddr(fp_gpio_ddr),
|
||||
|
||||
.pps_int(PPS_IN_INT), .pps_ext(PPS_IN_EXT),
|
||||
|
||||
.rxd(gps_txd), .txd(gps_rxd),
|
||||
|
||||
.pps_int(pps_ext_int), .pps_ext(pps_ext_int),
|
||||
// .rxd(gps_txd), .txd(gps_rxd),
|
||||
.pps(LED_CLK_R),
|
||||
.sclk(sclk), .sen(sen), .mosi(mosi), .miso(miso),
|
||||
.rb_misc({31'b0, pll_lock}), .misc_outs(misc_outs),
|
||||
|
||||
@@ -360,6 +402,11 @@ module b200 (
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// Debug port
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
assign debug = 0;
|
||||
// assign debug = 0;
|
||||
assign LED_STATUS = 'd1;
|
||||
assign LED_CLK_G = 'd0;
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule // B200
|
||||
|
||||
@@ -21,7 +21,6 @@ module b200_core
|
||||
parameter EXTRA_BUFF_SIZE = 0,
|
||||
parameter RADIO_FIFO_SIZE = 11,
|
||||
parameter SAMPLE_FIFO_SIZE = 11
|
||||
|
||||
)
|
||||
(
|
||||
////////////////////////////////////////////////////////////////////
|
||||
@@ -73,7 +72,9 @@ module b200_core
|
||||
////////////////////////////////////////////////////////////////////
|
||||
// debug signals
|
||||
////////////////////////////////////////////////////////////////////
|
||||
output [63:0] debug
|
||||
output [63:0] debug,
|
||||
|
||||
output pps
|
||||
);
|
||||
localparam SR_CORE_SPI = 8'd8;
|
||||
localparam SR_CORE_MISC = 8'd16;
|
||||
@@ -111,7 +112,7 @@ module b200_core
|
||||
|
||||
// PPS mux
|
||||
wire [1:0] pps_select;
|
||||
wire pps = (pps_select == 2'b00)? gpsdo_pps_del[1] :
|
||||
assign pps = (pps_select == 2'b00)? gpsdo_pps_del[1] :
|
||||
(pps_select == 2'b01)? ext_pps_del[1] :
|
||||
(pps_select == 2'b10)? int_pps_del[1] :
|
||||
1'b0;
|
||||
@@ -307,7 +308,7 @@ module b200_core
|
||||
.NEW_HB_DECIM(1),
|
||||
.SOURCE_FLOW_CONTROL(0),
|
||||
.USER_SETTINGS(0),
|
||||
.DEVICE("SPARTAN6")
|
||||
.DEVICE("7SERIES")
|
||||
) radio_0 (
|
||||
.radio_clk(radio_clk), .radio_rst(radio_rst),
|
||||
.rx(rx0), .tx(tx0), .pps(pps), .time_sync(time_sync_r),
|
||||
@@ -339,7 +340,7 @@ module b200_core
|
||||
.NEW_HB_DECIM(1),
|
||||
.SOURCE_FLOW_CONTROL(0),
|
||||
.USER_SETTINGS(0),
|
||||
.DEVICE("SPARTAN6")
|
||||
.DEVICE("7SERIES")
|
||||
) radio_1 (
|
||||
.radio_clk(radio_clk), .radio_rst(radio_rst),
|
||||
.rx(rx1), .tx(tx1), .pps(pps), .time_sync(time_sync_r),
|
||||
|
||||
+145
-538
@@ -1,554 +1,161 @@
|
||||
//
|
||||
// Copyright 2013 Ettus Research LLC
|
||||
// Copyright 2017 Ettus Research, a National Instruments Company
|
||||
// Copyright 2015 Ettus Research, A National Instruments Company
|
||||
// SPDX-License-Identifier: LGPL-3.0
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
// Description: E31X IO for CMOS interface
|
||||
//
|
||||
//
|
||||
//------------------------------------------------------------------
|
||||
//
|
||||
// In SISO mode, we output a clock thats 1x the frequency of the Catalina
|
||||
// source-synchronous bus clock to be used as the radio_clk.
|
||||
// In MIMO mode, we output a clock thats 1/2 the frequency of the Catalina
|
||||
// source-synchronous bus clock to be used as the radio_clk.
|
||||
//
|
||||
//------------------------------------------------------------------
|
||||
|
||||
module b200_io
|
||||
(
|
||||
input reset,
|
||||
input mimo,
|
||||
module b200_io (
|
||||
input areset,
|
||||
input mimo,
|
||||
// Baseband sample interface
|
||||
output radio_clk,
|
||||
output radio_rst,
|
||||
output reg [11:0] rx_i0,
|
||||
output reg [11:0] rx_q0,
|
||||
output reg [11:0] rx_i1,
|
||||
output reg [11:0] rx_q1,
|
||||
output reg rx_stb,
|
||||
input [11:0] tx_i0,
|
||||
input [11:0] tx_q0,
|
||||
input [11:0] tx_i1,
|
||||
input [11:0] tx_q1,
|
||||
output reg tx_stb,
|
||||
// AD9361 interface
|
||||
input rx_clk,
|
||||
input rx_frame,
|
||||
input [11:0] rx_data,
|
||||
output tx_clk,
|
||||
output tx_frame,
|
||||
output [11:0] tx_data
|
||||
);
|
||||
|
||||
// Baseband sample interface
|
||||
output radio_clk,
|
||||
output [11:0] rx_i0,
|
||||
output [11:0] rx_q0,
|
||||
output [11:0] rx_i1,
|
||||
output [11:0] rx_q1,
|
||||
input [11:0] tx_i0,
|
||||
input [11:0] tx_q0,
|
||||
input [11:0] tx_i1,
|
||||
input [11:0] tx_q1,
|
||||
// Synchronize asynchronous reset and MIMO
|
||||
synchronizer #(.STAGES(3), .INITIAL_VAL(1'b1)) sychronizer_radio_rst (
|
||||
.clk(radio_clk), .rst(areset), .in(1'b0), .out(radio_rst));
|
||||
|
||||
// Catalina interface
|
||||
input rx_clk,
|
||||
input rx_frame,
|
||||
input [11:0] rx_data,
|
||||
output tx_clk,
|
||||
output tx_frame,
|
||||
output [11:0] tx_data
|
||||
);
|
||||
wire mimo_sync;
|
||||
synchronizer synchronizer_mimo (.clk(radio_clk), .rst(radio_rst), .in(mimo), .out(mimo_sync));
|
||||
|
||||
/****************************************************************************
|
||||
** RX Capture Interface
|
||||
****************************************************************************/
|
||||
wire rx_clk_bufr; // Capture clock
|
||||
wire rx_clk_mimo_bufr;
|
||||
|
||||
BUFG bufr_rx_clk (.I(rx_clk), .O(rx_clk_bufr));
|
||||
|
||||
BUFR #(
|
||||
.BUFR_DIVIDE("2"), // Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
|
||||
.SIM_DEVICE("7SERIES") // Must be set to "7SERIES"
|
||||
)
|
||||
BUFR_inst (
|
||||
.O(rx_clk_mimo_bufr),
|
||||
.CE(1'b1),
|
||||
.CLR(areset),
|
||||
.I(rx_clk)
|
||||
);
|
||||
|
||||
BUFGMUX #(
|
||||
)
|
||||
BUFGMUX_inst (
|
||||
.O(radio_clk),
|
||||
.I0(rx_clk_bufr),
|
||||
.I1(rx_clk_mimo_bufr),
|
||||
.S(mimo_sync)
|
||||
);
|
||||
|
||||
|
||||
genvar z;
|
||||
wire [11:0] rx_i, rx_q;
|
||||
genvar n;
|
||||
generate
|
||||
for (n = 0; n < 12; n = n + 1) begin
|
||||
IDDR #(.DDR_CLK_EDGE("SAME_EDGE")) iddr (
|
||||
.C(rx_clk_bufr), .CE(1'b1), .R(1'b0), .S(1'b0),
|
||||
.D(rx_data[n]), .Q1(rx_q[n]), .Q2(rx_i[n]));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
//------------------------------------------------------------------
|
||||
//
|
||||
// Synchronize MIMO signal from bus_clk to siso_clk.
|
||||
//
|
||||
//------------------------------------------------------------------
|
||||
reg mimo_sync, mimo_sync2;
|
||||
wire rx_frame_rising, rx_frame_falling;
|
||||
IDDR #(.DDR_CLK_EDGE("SAME_EDGE")) iddr_frame (
|
||||
.C(rx_clk_bufr), .CE(1'b1), .R(1'b0), .S(1'b0),
|
||||
.D(rx_frame), .Q1(rx_frame_rising), .Q2(rx_frame_falling));
|
||||
|
||||
always @(posedge siso_clk) begin
|
||||
mimo_sync <= mimo_sync2;
|
||||
mimo_sync2 <= mimo;
|
||||
end
|
||||
always @(posedge rx_clk_bufr or posedge radio_rst) begin
|
||||
if (radio_rst) begin
|
||||
rx_stb <= 1'b0;
|
||||
end else begin
|
||||
if (mimo_sync) begin
|
||||
if (rx_frame_rising) begin
|
||||
rx_i0 <= rx_i;
|
||||
rx_q0 <= rx_q;
|
||||
end else begin
|
||||
rx_i1 <= rx_i;
|
||||
rx_q1 <= rx_q;
|
||||
end
|
||||
rx_stb <= ~rx_frame_rising;
|
||||
end else begin
|
||||
rx_i0 <= rx_i;
|
||||
rx_q0 <= rx_q;
|
||||
rx_i1 <= rx_i;
|
||||
rx_q1 <= rx_q;
|
||||
rx_stb <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
/****************************************************************************
|
||||
** TX Output Interface
|
||||
****************************************************************************/
|
||||
reg [11:0] tx_i, tx_q;
|
||||
reg tx_frame_int = 1'b1;
|
||||
generate
|
||||
for (n = 0; n < 12; n = n + 1) begin
|
||||
ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr (
|
||||
.C(rx_clk_bufr), .CE(1'b1), .R(1'b0), .S(1'b0),
|
||||
.D1(tx_i[n]), .D2(tx_q[n]), .Q(tx_data[n]));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// Clock Buffering.
|
||||
// BUFIO2 drives all IDDR2 and ODDR2 cells directly in bank3.
|
||||
// Need two pairs of BUFIO2 one pair each for Top Left and Bottom Left half banks.
|
||||
//------------------------------------------------------------------
|
||||
wire rx_clk_buf;
|
||||
wire mimo_clk_unbuf;
|
||||
wire siso_clk_unbuf;
|
||||
wire siso2_clk_unbuf;
|
||||
ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr_frame (
|
||||
.C(rx_clk_bufr), .CE(1'b1), .R(1'b0), .S(1'b0),
|
||||
// In SISO mode, TX frame is asserted only on the falling edge
|
||||
.D1(tx_frame_int), .D2(tx_frame_int & mimo_sync), .Q(tx_frame));
|
||||
|
||||
IBUFG clk_ibufg (.O(rx_clk_buf), .I(rx_clk));
|
||||
ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr_clk (
|
||||
.C(rx_clk_bufr), .CE(1'b1), .R(1'b0), .S(1'b0),
|
||||
.D1(1'b1), .D2(1'b0), .Q(tx_clk));
|
||||
|
||||
//------------------------------------------------------------------
|
||||
//
|
||||
// Buffers for LEFT TOP half bank pins
|
||||
// BUFIO2_X0Y22
|
||||
//
|
||||
//------------------------------------------------------------------
|
||||
BUFIO2 #(
|
||||
.DIVIDE(4),
|
||||
.DIVIDE_BYPASS("FALSE"),
|
||||
.I_INVERT("FALSE"),
|
||||
.USE_DOUBLER("TRUE"))
|
||||
clk_bufio_lt
|
||||
(
|
||||
.IOCLK(io_clk_lt),
|
||||
.DIVCLK(mimo_clk_unbuf), // Non-inverted source of 1/2x interface clock for radio_clk
|
||||
.SERDESSTROBE(),
|
||||
.I(rx_clk_buf)
|
||||
);
|
||||
reg [11:0] tx_i1_hold, tx_q1_hold;
|
||||
always @(posedge rx_clk_bufr or posedge radio_rst) begin
|
||||
if (radio_rst) begin
|
||||
tx_stb <= 1'b0;
|
||||
tx_frame_int <= 1'b1;
|
||||
end else begin
|
||||
if (mimo_sync) begin
|
||||
tx_stb <= ~tx_stb;
|
||||
tx_frame_int <= tx_stb;
|
||||
if (tx_stb) begin
|
||||
tx_i <= tx_i0;
|
||||
tx_q <= tx_q0;
|
||||
tx_i1_hold <= tx_i1;
|
||||
tx_q1_hold <= tx_q1;
|
||||
end else begin
|
||||
tx_i <= tx_i1_hold;
|
||||
tx_q <= tx_q1_hold;
|
||||
end
|
||||
end else begin
|
||||
tx_stb <= 1'b1;
|
||||
tx_frame_int <= 1'b1;
|
||||
if ({tx_i0,tx_q0} != 24'd0) begin
|
||||
tx_i <= tx_i0;
|
||||
tx_q <= tx_q0;
|
||||
end else begin
|
||||
tx_i <= tx_i1;
|
||||
tx_q <= tx_q1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// BUFIO2_X0Y23
|
||||
BUFIO2 #(
|
||||
.DIVIDE(1),
|
||||
.DIVIDE_BYPASS("FALSE"),
|
||||
.I_INVERT("TRUE"),
|
||||
.USE_DOUBLER("FALSE"))
|
||||
clk_bufio_lt_b
|
||||
(
|
||||
.IOCLK(io_clk_lt_b),
|
||||
.DIVCLK(siso_clk2_unbuf), // Inverted source of 1x interface clock for radio_clk
|
||||
.SERDESSTROBE(),
|
||||
.I(rx_clk_buf)
|
||||
);
|
||||
|
||||
//------------------------------------------------------------------
|
||||
//
|
||||
// Buffers for LEFT BOTTOM half bank pins
|
||||
// BUFIO2_X1Y14
|
||||
//
|
||||
//------------------------------------------------------------------
|
||||
BUFIO2 #(
|
||||
.DIVIDE(1),
|
||||
.DIVIDE_BYPASS("FALSE"),
|
||||
.I_INVERT("FALSE"),
|
||||
.USE_DOUBLER("FALSE"))
|
||||
clk_bufio_lb
|
||||
(
|
||||
.IOCLK(io_clk_lb),
|
||||
.DIVCLK(siso_clk_unbuf), // Non-inverted source of 1x interface clock for local IO use
|
||||
.SERDESSTROBE(),
|
||||
.I(rx_clk_buf)
|
||||
);
|
||||
|
||||
// BUFIO2_X1Y15
|
||||
BUFIO2 #(
|
||||
.DIVIDE(1),
|
||||
.DIVIDE_BYPASS("FALSE"),
|
||||
.I_INVERT("TRUE"),
|
||||
.USE_DOUBLER("FALSE"))
|
||||
clk_bufio_lb_b
|
||||
(
|
||||
.IOCLK(io_clk_lb_b),
|
||||
.DIVCLK(),
|
||||
.SERDESSTROBE(),
|
||||
.I(rx_clk_buf)
|
||||
);
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// Always-on SISO clk needed to load/unload DDR2 I/O Regs
|
||||
//------------------------------------------------------------------
|
||||
BUFG siso_clk_bufg (
|
||||
.I(siso_clk_unbuf),
|
||||
.O(siso_clk)
|
||||
);
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// 2-1 mux combined with BUFG to drive global radio_clk.
|
||||
// Note: Not addressed setup/hold constraints of S input ...unsure if anything "bad" can happen here.
|
||||
//------------------------------------------------------------------
|
||||
BUFGMUX #(
|
||||
.CLK_SEL_TYPE("SYNC"))
|
||||
radio_clk_bufg (
|
||||
.I0(siso_clk2_unbuf),
|
||||
.I1(mimo_clk_unbuf),
|
||||
.S(mimo_sync),
|
||||
.O(radio_clk)
|
||||
);
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// RX Frame Signal - In bank 3 LB
|
||||
//------------------------------------------------------------------
|
||||
wire rx_frame_0, rx_frame_1;
|
||||
|
||||
IDDR2 #(
|
||||
.DDR_ALIGNMENT("C0"))
|
||||
iddr2_frame (
|
||||
.Q0(rx_frame_1),
|
||||
.Q1(rx_frame_0),
|
||||
.C0(io_clk_lb),
|
||||
.C1(io_clk_lb_b),
|
||||
.CE(1'b1),
|
||||
.D(rx_frame),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
reg rx_frame_d1, rx_frame_d2;
|
||||
always @(posedge siso_clk)
|
||||
if(~mimo_sync)
|
||||
{ rx_frame_d2, rx_frame_d1 } <= { rx_frame_1, 1'b0 };
|
||||
else
|
||||
{ rx_frame_d2, rx_frame_d1 } <= { rx_frame_d1, rx_frame_1 };
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// RX Data Bus - In bank3 both LT and LB
|
||||
//------------------------------------------------------------------
|
||||
wire [11:0] rx_i,rx_q;
|
||||
|
||||
// Bit0 LB
|
||||
IDDR2 #(
|
||||
.DDR_ALIGNMENT("C0"))
|
||||
iddr2_i0 (
|
||||
.Q0(rx_q[0]),
|
||||
.Q1(rx_i[0]),
|
||||
.C0(io_clk_lb),
|
||||
.C1(io_clk_lb_b),
|
||||
.CE(1'b1),
|
||||
.D(rx_data[0]),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
// Bit1 LB
|
||||
IDDR2 #(
|
||||
.DDR_ALIGNMENT("C0"))
|
||||
iddr2_i1 (
|
||||
.Q0(rx_q[1]),
|
||||
.Q1(rx_i[1]),
|
||||
.C0(io_clk_lb),
|
||||
.C1(io_clk_lb_b),
|
||||
.CE(1'b1),
|
||||
.D(rx_data[1]),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
// Bit2 LB
|
||||
IDDR2 #(
|
||||
.DDR_ALIGNMENT("C0"))
|
||||
iddr2_i2 (
|
||||
.Q0(rx_q[2]),
|
||||
.Q1(rx_i[2]),
|
||||
.C0(io_clk_lb),
|
||||
.C1(io_clk_lb_b),
|
||||
.CE(1'b1),
|
||||
.D(rx_data[2]),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
// Bit3 LT
|
||||
IDDR2 #(
|
||||
.DDR_ALIGNMENT("C0"))
|
||||
iddr2_i3 (
|
||||
.Q0(rx_q[3]),
|
||||
.Q1(rx_i[3]),
|
||||
.C0(io_clk_lt),
|
||||
.C1(io_clk_lt_b),
|
||||
.CE(1'b1),
|
||||
.D(rx_data[3]),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
// Bit4 LB
|
||||
IDDR2 #(
|
||||
.DDR_ALIGNMENT("C0"))
|
||||
iddr2_i4 (
|
||||
.Q0(rx_q[4]),
|
||||
.Q1(rx_i[4]),
|
||||
.C0(io_clk_lb),
|
||||
.C1(io_clk_lb_b),
|
||||
.CE(1'b1),
|
||||
.D(rx_data[4]),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
// Bit5 LT
|
||||
IDDR2 #(
|
||||
.DDR_ALIGNMENT("C0"))
|
||||
iddr2_i5 (
|
||||
.Q0(rx_q[5]),
|
||||
.Q1(rx_i[5]),
|
||||
.C0(io_clk_lt),
|
||||
.C1(io_clk_lt_b),
|
||||
.CE(1'b1),
|
||||
.D(rx_data[5]),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
// Bit6 LB
|
||||
IDDR2 #(
|
||||
.DDR_ALIGNMENT("C0"))
|
||||
iddr2_i6 (
|
||||
.Q0(rx_q[6]),
|
||||
.Q1(rx_i[6]),
|
||||
.C0(io_clk_lb),
|
||||
.C1(io_clk_lb_b),
|
||||
.CE(1'b1),
|
||||
.D(rx_data[6]),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
// Bit7 LT
|
||||
IDDR2 #(
|
||||
.DDR_ALIGNMENT("C0"))
|
||||
iddr2_i7 (
|
||||
.Q0(rx_q[7]),
|
||||
.Q1(rx_i[7]),
|
||||
.C0(io_clk_lt),
|
||||
.C1(io_clk_lt_b),
|
||||
.CE(1'b1),
|
||||
.D(rx_data[7]),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
// Bit8 LB
|
||||
IDDR2 #(
|
||||
.DDR_ALIGNMENT("C0"))
|
||||
iddr2_i8 (
|
||||
.Q0(rx_q[8]),
|
||||
.Q1(rx_i[8]),
|
||||
.C0(io_clk_lb),
|
||||
.C1(io_clk_lb_b),
|
||||
.CE(1'b1),
|
||||
.D(rx_data[8]),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
// Bit9 LT
|
||||
IDDR2 #(
|
||||
.DDR_ALIGNMENT("C0"))
|
||||
iddr2_i9 (
|
||||
.Q0(rx_q[9]),
|
||||
.Q1(rx_i[9]),
|
||||
.C0(io_clk_lt),
|
||||
.C1(io_clk_lt_b),
|
||||
.CE(1'b1),
|
||||
.D(rx_data[9]),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
// Bit10 LB
|
||||
IDDR2 #(
|
||||
.DDR_ALIGNMENT("C0"))
|
||||
iddr2_i10 (
|
||||
.Q0(rx_q[10]),
|
||||
.Q1(rx_i[10]),
|
||||
.C0(io_clk_lb),
|
||||
.C1(io_clk_lb_b),
|
||||
.CE(1'b1),
|
||||
.D(rx_data[10]),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
// Bit11 LB
|
||||
IDDR2 #(
|
||||
.DDR_ALIGNMENT("C0"))
|
||||
iddr2_i11 (
|
||||
.Q0(rx_q[11]),
|
||||
.Q1(rx_i[11]),
|
||||
.C0(io_clk_lb),
|
||||
.C1(io_clk_lb_b),
|
||||
.CE(1'b1),
|
||||
.D(rx_data[11]),
|
||||
.R(1'b0),
|
||||
.S(1'b0));
|
||||
|
||||
//------------------------------------------------------------------
|
||||
//
|
||||
// De-mux I & Q, Ch A & B onto fullrate clock.
|
||||
//
|
||||
// In all modes we grab data from the IDDR2 using negedge of siso_clk.
|
||||
// IDDR2 updates all Q pins on posedge of io_clk. siso_clk does not have aligned phase
|
||||
// with siso_clk...siso_clk is always a little more delayed than io_clk.
|
||||
// This small delay is always much smaller than half a clk cycle. Thus by sampling the Q outputs
|
||||
// with negedge siso_clk we avoid any risk of a race condition (hold violation on receiveing register).
|
||||
//
|
||||
// In SISO mode data is replicated onto both CH0 and CH1 for max flexibility in using the DDC's.
|
||||
//
|
||||
//------------------------------------------------------------------
|
||||
reg [11:0] rx_i_del, rx_q_del;
|
||||
reg [11:0] rx_i0_siso_pos;
|
||||
reg [11:0] rx_q0_siso_pos;
|
||||
reg [11:0] rx_i1_siso_pos;
|
||||
reg [11:0] rx_q1_siso_pos;
|
||||
reg [11:0] rx_i0_siso_neg;
|
||||
reg [11:0] rx_q0_siso_neg;
|
||||
reg [11:0] rx_i1_siso_neg;
|
||||
reg [11:0] rx_q1_siso_neg;
|
||||
reg [11:0] rx_i0_siso;
|
||||
reg [11:0] rx_q0_siso;
|
||||
reg [11:0] rx_i1_siso;
|
||||
reg [11:0] rx_q1_siso;
|
||||
|
||||
|
||||
always @(negedge siso_clk)
|
||||
if(mimo_sync)
|
||||
// rx_frame_0 was sampled by same falling io_clk edge as rx_i[x]
|
||||
// rx_frame_0 == 0 causes I & Q to be allocated to CH0
|
||||
if(rx_frame_0) begin
|
||||
rx_i_del[11:0] <= rx_i[11:0];
|
||||
rx_q_del[11:0] <= rx_q[11:0];
|
||||
end
|
||||
else begin
|
||||
// Deal with the fact that Ch A and Ch B are labelled in silkscreen opposite to their documentation in AD9361.
|
||||
rx_i0_siso[11:0] <= rx_i[11:0];
|
||||
rx_q0_siso[11:0] <= rx_q[11:0];
|
||||
rx_i1_siso[11:0] <= rx_i_del[11:0];
|
||||
rx_q1_siso[11:0] <= rx_q_del[11:0];
|
||||
end
|
||||
else begin
|
||||
rx_i0_siso[11:0] <= rx_i[11:0];
|
||||
rx_q0_siso[11:0] <= rx_q[11:0];
|
||||
rx_i1_siso[11:0] <= rx_i[11:0];
|
||||
rx_q1_siso[11:0] <= rx_q[11:0];
|
||||
end // else: !if(rx_frame_0)
|
||||
|
||||
//------------------------------------------------------------------
|
||||
//
|
||||
// Now prepare data for crossing into radio_clk domain which can be for SISO mode (inverted) siso_clk or for MIMO mode siso_clk/2.
|
||||
// In MIMO mode tx_strobe is used to maintain a known phase relationship betwwen siso_clk and radio_clk.
|
||||
// (Note: Negedge or posedge is used conditionally so that we have massive margin against a fast-path race condition
|
||||
// betwwen siso_clk and radio_clk). This kind of arrangement could still lead to confusion in timing analysis
|
||||
// even if it works in the real world depending on how well the STA tool can do automatic case analysis.
|
||||
//
|
||||
//------------------------------------------------------------------
|
||||
// This code lock only relevent in MIMO mode.
|
||||
always @(negedge siso_clk)
|
||||
if (tx_strobe)
|
||||
begin
|
||||
rx_i0_siso_neg[11:0] <= rx_i0_siso[11:0];
|
||||
rx_q0_siso_neg[11:0] <= rx_q0_siso[11:0];
|
||||
rx_i1_siso_neg[11:0] <= rx_i1_siso[11:0];
|
||||
rx_q1_siso_neg[11:0] <= rx_q1_siso[11:0];
|
||||
end
|
||||
// This code block only relevent in SISO mode.
|
||||
always @(posedge siso_clk)
|
||||
begin
|
||||
rx_i0_siso_pos[11:0] <= rx_i0_siso[11:0];
|
||||
rx_q0_siso_pos[11:0] <= rx_q0_siso[11:0];
|
||||
rx_i1_siso_pos[11:0] <= rx_i1_siso[11:0];
|
||||
rx_q1_siso_pos[11:0] <= rx_q1_siso[11:0];
|
||||
end
|
||||
|
||||
assign rx_i0 = (mimo_sync) ? rx_i0_siso_neg : rx_i0_siso_pos;
|
||||
assign rx_q0 = (mimo_sync) ? rx_q0_siso_neg : rx_q0_siso_pos;
|
||||
assign rx_i1 = (mimo_sync) ? rx_i1_siso_neg : rx_i1_siso_pos;
|
||||
assign rx_q1 = (mimo_sync) ? rx_q1_siso_neg : rx_q1_siso_pos;
|
||||
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// TX Data Bus - In bank3 LB
|
||||
//------------------------------------------------------------------
|
||||
reg [11:0] tx_i,tx_q;
|
||||
reg tx_strobe_del;
|
||||
|
||||
generate
|
||||
for(z = 0; z < 12; z = z + 1)
|
||||
begin : gen_pins
|
||||
ODDR2 #(
|
||||
.DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC"))
|
||||
oddr2 (
|
||||
.Q(tx_data[z]), .C0(io_clk_lb), .C1(io_clk_lb_b),
|
||||
.CE(1'b1), .D0(tx_i[z]), .D1(tx_q[z]), .R(1'b0), .S(1'b0));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// TX Frame Signal - In bank 3 LB
|
||||
//------------------------------------------------------------------
|
||||
ODDR2 #(
|
||||
.DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC"))
|
||||
oddr2_frame (
|
||||
.Q(tx_frame), .C0(io_clk_lb), .C1(io_clk_lb_b),
|
||||
.CE(1'b1), .D0(tx_strobe_del), .D1(mimo_sync & tx_strobe_del), .R(1'b0), .S(1'b0));
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// TX Clock Signal - In bank 3 LB
|
||||
//------------------------------------------------------------------
|
||||
ODDR2 #(
|
||||
.DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC"))
|
||||
oddr2_clk (
|
||||
.Q(tx_clk), .C0(io_clk_lb), .C1(io_clk_lb_b),
|
||||
.CE(1'b1), .D0(1'b1), .D1(1'b0), .R(1'b0), .S(1'b0));
|
||||
|
||||
//------------------------------------------------------------------
|
||||
//
|
||||
// Mux I & Q, Ch A & B onto fullrate clockTX bus to AD9361
|
||||
//
|
||||
//------------------------------------------------------------------
|
||||
wire tx_strobe;
|
||||
reg [11:0] tx_i_del, tx_q_del;
|
||||
|
||||
reg find_radio_clk_phase = 1'b0;
|
||||
reg find_radio_clk_phase_del;
|
||||
|
||||
|
||||
always @(posedge radio_clk)
|
||||
find_radio_clk_phase <= ~find_radio_clk_phase;
|
||||
|
||||
always @(negedge radio_clk)
|
||||
find_radio_clk_phase_del <= find_radio_clk_phase;
|
||||
|
||||
assign tx_strobe = mimo_sync ? (find_radio_clk_phase_del ^ find_radio_clk_phase) : 1'b1;
|
||||
|
||||
always @(posedge siso_clk)
|
||||
tx_strobe_del <= tx_strobe;
|
||||
|
||||
// This strange piece of logic allows either USRP DUC to drive the AD9361 in SISO mode.
|
||||
// This is principly used in the CODEC loopback test.
|
||||
wire [11:0] tx_im = (mimo_sync || tx_i0 != 12'h0) ? tx_i0 : tx_i1;
|
||||
wire [11:0] tx_qm = (mimo_sync || tx_q0 != 12'h0) ? tx_q0 : tx_q1;
|
||||
|
||||
|
||||
// Deal with the fact that Ch A and Ch B are labelled in silkscreen opposite to their documentation in AD9361.
|
||||
// (Except on B200 based on AD9364 where only the true Ch A is stuffed)
|
||||
always @(posedge siso_clk)
|
||||
if(tx_strobe)
|
||||
begin
|
||||
{tx_i,tx_q} <= mimo_sync ? {tx_i1,tx_q1} : {tx_im,tx_qm};
|
||||
{tx_i_del,tx_q_del} <= {tx_i0,tx_q0};
|
||||
end
|
||||
else
|
||||
{tx_i,tx_q} <= {tx_i_del,tx_q_del};
|
||||
//
|
||||
// Debug
|
||||
//
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
wire [35:0] CONTROL0;
|
||||
reg [11:0] tx_i_del_debug, tx_q_del_debug;
|
||||
reg [11:0] tx_i_debug,tx_q_debug;
|
||||
reg [11:0] tx_i0_debug,tx_q0_debug;
|
||||
reg find_radio_clk_phase_debug;
|
||||
reg find_radio_clk_phase_del_debug;
|
||||
reg tx_strobe_debug;
|
||||
reg tx_strobe_del_debug;
|
||||
|
||||
|
||||
always @(posedge siso_clk) begin
|
||||
tx_i_del_debug <= tx_i_del;
|
||||
tx_q_del_debug <= tx_q_del;
|
||||
tx_i_debug <= tx_i;
|
||||
tx_q_debug <= tx_q;
|
||||
tx_i0_debug <=tx_i0;
|
||||
tx_q0_debug <= tx_q0;
|
||||
find_radio_clk_phase_debug <= find_radio_clk_phase;
|
||||
find_radio_clk_phase_del_debug <= find_radio_clk_phase_del;
|
||||
tx_strobe_debug <= tx_strobe;
|
||||
tx_strobe_del_debug <= tx_strobe_del;
|
||||
end
|
||||
|
||||
|
||||
|
||||
chipscope_icon chipscope_icon_i0
|
||||
(
|
||||
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
|
||||
);
|
||||
|
||||
chipscope_ila_128 chipscope_ila_i0
|
||||
(
|
||||
.CONTROL(CONTROL0), // INOUT BUS [35:0]
|
||||
.CLK(siso_clk), // IN
|
||||
.TRIG0(
|
||||
{
|
||||
tx_i_del_debug[11:0],
|
||||
tx_q_del_debug[11:0],
|
||||
tx_i_debug[11:0],
|
||||
tx_q_debug[11:0],
|
||||
tx_i0_debug[11:0],
|
||||
tx_q0_debug[11:0],
|
||||
find_radio_clk_phase_debug,
|
||||
find_radio_clk_phase_del_debug,
|
||||
tx_strobe_debug,
|
||||
tx_strobe_del_debug
|
||||
}
|
||||
)
|
||||
|
||||
);
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,185 @@
|
||||
set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVCMOS33} [get_ports PPS_IN_EXT]
|
||||
set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS33} [get_ports PPS_IN_INT]
|
||||
|
||||
set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVDS} [get_ports codec_main_clk_p]
|
||||
set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVDS} [get_ports codec_main_clk_n]
|
||||
|
||||
set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS33} [get_ports pll_ce]
|
||||
set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS33} [get_ports pll_mosi]
|
||||
set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS33} [get_ports pll_sclk]
|
||||
set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS33} [get_ports ref_sel]
|
||||
set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS33} [get_ports pll_lock]
|
||||
|
||||
# set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33} [get_ports gps_rxd]
|
||||
# set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33} [get_ports gps_txd]
|
||||
|
||||
# #### FX3 Lines ##############################################################
|
||||
# GPIF Data lines
|
||||
set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[0]}]
|
||||
set_property -dict {PACKAGE_PIN AA3 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[1]}]
|
||||
set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[2]}]
|
||||
set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[3]}]
|
||||
set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[4]}]
|
||||
set_property -dict {PACKAGE_PIN U1 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[5]}]
|
||||
set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[6]}]
|
||||
set_property -dict {PACKAGE_PIN W4 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[7]}]
|
||||
set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[8]}]
|
||||
set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[9]}]
|
||||
set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[10]}]
|
||||
set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[11]}]
|
||||
set_property -dict {PACKAGE_PIN AA5 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[12]}]
|
||||
set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[13]}]
|
||||
set_property -dict {PACKAGE_PIN AC1 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[14]}]
|
||||
set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[15]}]
|
||||
set_property -dict {PACKAGE_PIN AE6 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[16]}]
|
||||
set_property -dict {PACKAGE_PIN AD5 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[17]}]
|
||||
set_property -dict {PACKAGE_PIN AD6 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[18]}]
|
||||
set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[19]}]
|
||||
set_property -dict {PACKAGE_PIN AE5 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[20]}]
|
||||
set_property -dict {PACKAGE_PIN AF3 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[21]}]
|
||||
set_property -dict {PACKAGE_PIN AE3 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[22]}]
|
||||
set_property -dict {PACKAGE_PIN AF2 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[23]}]
|
||||
set_property -dict {PACKAGE_PIN W3 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[24]}]
|
||||
set_property -dict {PACKAGE_PIN AF4 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[25]}]
|
||||
set_property -dict {PACKAGE_PIN AD4 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[26]}]
|
||||
set_property -dict {PACKAGE_PIN AF5 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[27]}]
|
||||
set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[28]}]
|
||||
set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[29]}]
|
||||
set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[30]}]
|
||||
set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[31]}]
|
||||
|
||||
set_property -dict {PACKAGE_PIN AD1 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports IFCLK]
|
||||
set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS18} [get_ports FX3_EXTINT]
|
||||
|
||||
# FX3 CTRL
|
||||
set_property -dict {PACKAGE_PIN AA4 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL0]
|
||||
set_property -dict {PACKAGE_PIN AE2 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL1]
|
||||
set_property -dict {PACKAGE_PIN AE1 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL2]
|
||||
set_property -dict {PACKAGE_PIN AC2 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL3]
|
||||
set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL4]
|
||||
set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL5]
|
||||
set_property -dict {PACKAGE_PIN AD3 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL6]
|
||||
set_property -dict {PACKAGE_PIN Y5 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL7]
|
||||
set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL8]
|
||||
set_property -dict {PACKAGE_PIN AB1 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL9]
|
||||
set_property -dict {PACKAGE_PIN AC4 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL11]
|
||||
set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL12]
|
||||
|
||||
#debug uart
|
||||
set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVCMOS18} [get_ports FPGA_RXD0]
|
||||
set_property -dict {PACKAGE_PIN AE11 IOSTANDARD LVCMOS18} [get_ports FPGA_TXD0]
|
||||
#GPIO
|
||||
|
||||
set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {fp_gpio[0]}]
|
||||
set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {fp_gpio[1]}]
|
||||
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {fp_gpio[2]}]
|
||||
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {fp_gpio[3]}]
|
||||
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {fp_gpio[4]}]
|
||||
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {fp_gpio[5]}]
|
||||
set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {fp_gpio[6]}]
|
||||
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {fp_gpio[7]}]
|
||||
|
||||
# LED
|
||||
set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS33} [get_ports LED_TXRX1_RX]
|
||||
set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS33} [get_ports LED_TXRX1_TX]
|
||||
set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS33} [get_ports LED_RX1]
|
||||
set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS33} [get_ports LED_RX2]
|
||||
set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS33} [get_ports LED_TXRX2_RX]
|
||||
set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports LED_TXRX2_TX]
|
||||
|
||||
set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports LED_STATUS]
|
||||
set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVCMOS33} [get_ports LED_CLK_G]
|
||||
set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS33} [get_ports LED_CLK_R]
|
||||
|
||||
# CAT
|
||||
set_property -dict {PACKAGE_PIN F23 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports codec_reset]
|
||||
set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports codec_en_agc]
|
||||
set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports codec_enable]
|
||||
set_property -dict {PACKAGE_PIN G24 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports codec_txrx]
|
||||
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports codec_sync]
|
||||
set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS18 SLEW SLOW PULLTYPE PULLUP } [get_ports cat_ce]
|
||||
set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports cat_sclk]
|
||||
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports cat_mosi]
|
||||
set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports cat_miso]
|
||||
set_property -dict {PACKAGE_PIN F24 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports cat_clkout_fpga]
|
||||
|
||||
# Control Lines
|
||||
set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS18} [get_ports {codec_ctrl_out[0]}]
|
||||
set_property -dict {PACKAGE_PIN C26 IOSTANDARD LVCMOS18} [get_ports {codec_ctrl_out[1]}]
|
||||
set_property -dict {PACKAGE_PIN C24 IOSTANDARD LVCMOS18} [get_ports {codec_ctrl_out[2]}]
|
||||
set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS18} [get_ports {codec_ctrl_out[3]}]
|
||||
set_property -dict {PACKAGE_PIN C23 IOSTANDARD LVCMOS18} [get_ports {codec_ctrl_out[4]}]
|
||||
set_property -dict {PACKAGE_PIN D24 IOSTANDARD LVCMOS18} [get_ports {codec_ctrl_out[5]}]
|
||||
set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVCMOS18} [get_ports {codec_ctrl_out[6]}]
|
||||
set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS18} [get_ports {codec_ctrl_out[7]}]
|
||||
|
||||
set_property -dict {PACKAGE_PIN A24 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {codec_ctrl_in[0]}]
|
||||
set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {codec_ctrl_in[1]}]
|
||||
set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {codec_ctrl_in[2]}]
|
||||
set_property -dict {PACKAGE_PIN A23 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {codec_ctrl_in[3]}]
|
||||
|
||||
# Tx Bus P0
|
||||
set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[0]}]
|
||||
set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[1]}]
|
||||
set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[2]}]
|
||||
set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[3]}]
|
||||
set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[4]}]
|
||||
set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[5]}]
|
||||
set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[6]}]
|
||||
set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[7]}]
|
||||
set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[8]}]
|
||||
set_property -dict {PACKAGE_PIN Y15 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[9]}]
|
||||
set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[10]}]
|
||||
set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[11]}]
|
||||
|
||||
# RX Bus P1
|
||||
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[0]}]
|
||||
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[1]}]
|
||||
set_property -dict {PACKAGE_PIN AE20 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[2]}]
|
||||
set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[3]}]
|
||||
set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[4]}]
|
||||
set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[5]}]
|
||||
set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[6]}]
|
||||
set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[7]}]
|
||||
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[8]}]
|
||||
set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[9]}]
|
||||
set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[10]}]
|
||||
set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[11]}]
|
||||
|
||||
# Frame syncs
|
||||
set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS18} [get_ports codec_data_clk_p]
|
||||
set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS18} [get_ports rx_frame_p]
|
||||
set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS18} [get_ports tx_frame_p]
|
||||
set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS18} [get_ports codec_fb_clk_p]
|
||||
|
||||
## RF Hardware Control
|
||||
set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33} [get_ports SFDX1_RX]
|
||||
set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS33} [get_ports SFDX1_TX]
|
||||
set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS33} [get_ports SFDX2_RX]
|
||||
set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS33} [get_ports SFDX2_TX]
|
||||
set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33} [get_ports SRX1_RX]
|
||||
set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports SRX1_TX]
|
||||
set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS33} [get_ports SRX2_RX]
|
||||
set_property -dict {PACKAGE_PIN G10 IOSTANDARD LVCMOS33} [get_ports SRX2_TX]
|
||||
set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports tx_bandsel_a]
|
||||
set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVCMOS33} [get_ports tx_bandsel_b]
|
||||
set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_a]
|
||||
set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_b]
|
||||
set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_c]
|
||||
|
||||
set_property -dict {PACKAGE_PIN D13 IOSTANDARD LVCMOS33} [get_ports tx_enable1]
|
||||
set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS33} [get_ports tx_enable2]
|
||||
|
||||
|
||||
# IFCLK is 100 MHz GPIF clock
|
||||
create_clock -period 10.000 -name IFCLK [get_ports IFCLK]
|
||||
create_clock -period 16.276 -name codec_data_clk_p [get_ports codec_data_clk_p]
|
||||
|
||||
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins gen_clks/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks codec_data_clk_p]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins gen_clks/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins b200_io_i0/BUFR_inst/O]]
|
||||
set_false_path -from [get_clocks codec_data_clk_p] -to [get_clocks -of_objects [get_pins gen_clks/inst/mmcm_adv_inst/CLKOUT1]]
|
||||
set_false_path -from [get_clocks -of_objects [get_pins b200_io_i0/BUFR_inst/O]] -to [get_clocks -of_objects [get_pins gen_clks/inst/mmcm_adv_inst/CLKOUT1]]
|
||||
|
||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,43 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2025/07/03 01:29:39
|
||||
// Design Name:
|
||||
// Module Name: edge_detect
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
// 边沿检测子模块
|
||||
module edge_detect (
|
||||
input wire clk,
|
||||
input wire rst_n,
|
||||
input wire din,
|
||||
output wire dout
|
||||
);
|
||||
reg din_d1, din_d2;
|
||||
always @(posedge clk or negedge rst_n) begin
|
||||
if (!rst_n) begin
|
||||
din_d1 <= 1'b0;
|
||||
din_d2 <= 1'b0;
|
||||
end else begin
|
||||
din_d1 <= din;
|
||||
din_d2 <= din_d1;
|
||||
end
|
||||
end
|
||||
assign dout = din_d1 & ~din_d2; // 上升沿
|
||||
endmodule
|
||||
|
||||
|
||||
@@ -0,0 +1,72 @@
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// pps_switch.v
|
||||
module pps_switch (
|
||||
input wire clk, // 系统时钟（≥10 MHz 推荐）
|
||||
input wire rst_n, // 低电平有效异步复位
|
||||
input wire gps_pps, // GPS_PPS 输入
|
||||
input wire ext_pps, // EXT_PPS 输入
|
||||
output reg pps_out // 最终输出的PPS脉冲
|
||||
);
|
||||
|
||||
// 跟踪当前激活的PPS源
|
||||
reg active_pps_source; // 0=GPS, 1=EXT
|
||||
|
||||
// 边沿检测：上升沿产生一个时钟周期的高脉冲
|
||||
wire gps_posedge;
|
||||
wire ext_posedge;
|
||||
|
||||
edge_detect u_gps_edge (
|
||||
.clk(clk),
|
||||
.rst_n(rst_n),
|
||||
.din(gps_pps),
|
||||
.dout(gps_posedge)
|
||||
);
|
||||
|
||||
edge_detect u_ext_edge (
|
||||
.clk(clk),
|
||||
.rst_n(rst_n),
|
||||
.din(ext_pps),
|
||||
.dout(ext_posedge)
|
||||
);
|
||||
|
||||
// 状态机：0=等待GPS，1=等待EXT
|
||||
reg [1:0] state;
|
||||
localparam S_GPS = 2'b00;
|
||||
localparam S_EXT = 2'b01;
|
||||
|
||||
always @(posedge clk or negedge rst_n) begin
|
||||
if (!rst_n) begin
|
||||
state <= S_GPS;
|
||||
active_pps_source <= 1'b0; // 默认GPS
|
||||
end
|
||||
else begin
|
||||
case (state)
|
||||
S_GPS: begin
|
||||
if (gps_posedge) begin
|
||||
state <= S_GPS; // 保持GPS优先
|
||||
active_pps_source <= 1'b0; // 激活GPS
|
||||
end else if (ext_posedge) begin
|
||||
state <= S_GPS; // 仍保持GPS优先，但允许EXT临时补位
|
||||
active_pps_source <= 1'b1; // 激活EXT
|
||||
end
|
||||
end
|
||||
default: begin // 简化处理，实际应用中可扩展状态机
|
||||
if (ext_posedge) begin
|
||||
state <= S_GPS; // 回到GPS等待
|
||||
active_pps_source <= 1'b1; // 激活EXT
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// 输出逻辑
|
||||
always @(posedge clk or negedge rst_n) begin
|
||||
if (!rst_n)
|
||||
pps_out <= 1'b0;
|
||||
else
|
||||
pps_out <= active_pps_source ? ext_pps : gps_pps;
|
||||
end
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user