diff --git a/top/b200/Define.vh b/top/b200/Define.vh new file mode 100644 index 0000000..d8680f8 --- /dev/null +++ b/top/b200/Define.vh @@ -0,0 +1 @@ +`define TARGET_B210 \ No newline at end of file diff --git a/top/b200/b200.v b/top/b200/b200.v index 811842f..c89e63c 100644 --- a/top/b200/b200.v +++ b/top/b200/b200.v @@ -16,10 +16,10 @@ module b200 ( output cat_mosi, output cat_sclk, - input fx3_ce, - output fx3_miso, - input fx3_mosi, - input fx3_sclk, + // input fx3_ce, + // output fx3_miso, + // input fx3_mosi, + // input fx3_sclk, output pll_ce, output pll_mosi, @@ -58,8 +58,8 @@ module b200 ( input codec_main_clk_n, // Debug Bus - output [31:0] debug, - output [1:0] debug_clk, + // output [31:0] debug, + // output [1:0] debug_clk, // GPIF, FX3 Slave FIFO output IFCLK, // pclk @@ -79,10 +79,10 @@ module b200 ( input GPIF_CTL9, // global_reset // GPS - input gps_lock, - output gps_rxd, - input gps_txd, // FPGA has pullup for unpopulated GPS - input gps_txd_nmea, // FPGA has pullup for unpopulated GPS + // input gps_lock, + // output gps_rxd, + // input gps_txd, // FPGA has pullup for unpopulated GPS + // input gps_txd_nmea, // FPGA has pullup for unpopulated GPS // LEDS output LED_RX1, @@ -102,8 +102,8 @@ module b200 ( // Misc Hardware Control output ref_sel, input pll_lock, - input FPGA_CFG_CS, // Driven by FX3 gpio. - input AUX_PWR_ON, // Driven by FX3 gpio. + // input FPGA_CFG_CS, // Driven by FX3 gpio. + // input AUX_PWR_ON, // Driven by FX3 gpio. // PPS input PPS_IN_EXT, @@ -124,9 +124,14 @@ module b200 ( output tx_enable2, output rx_bandsel_a, output rx_bandsel_b, - output rx_bandsel_c + output rx_bandsel_c, + + output LED_STATUS, + output LED_CLK_G, + output LED_CLK_R ); + wire reset_global = GPIF_CTL9; /////////////////////////////////////////////////////////////////////// @@ -136,9 +141,13 @@ module b200 ( wire locked; b200_clk_gen gen_clks ( - .CLK_IN1_40_P(codec_main_clk_p), .CLK_IN1_40_N(codec_main_clk_n), - .CLK_OUT1_40_int(), .CLK_OUT2_100_gpif(gpif_clk), .CLK_OUT3_100_bus(), - .RESET(reset_global), .LOCKED(locked) + .clk_in1_p(codec_main_clk_p), + .clk_in1_n(codec_main_clk_n), + .CLK_OUT1_40_int(), + .CLK_OUT2_100_gpif(gpif_clk), + .CLK_OUT3_100_bus(), + .reset(reset_global), + .locked(locked) ); // Bus Clock and GPIF Clock both same 100MHz clock. @@ -165,8 +174,27 @@ module b200 ( wire [1:0] debug_clk_int; //S6CLK2PIN S6CLK2PIN_dbg0 (.I(debug_clk_int[0]), .O(debug_clk[0])); //S6CLK2PIN S6CLK2PIN_dbg1 (.I(debug_clk_int[1]), .O(debug_clk[1])); - assign debug_clk[1:0] = 2'b0; - S6CLK2PIN S6CLK2PIN_gpif (.I(gpif_clk), .O(IFCLK)); + // assign debug_clk[1:0] = 2'b0; + // S6CLK2PIN S6CLK2PIN_gpif (.I(gpif_clk), .O(IFCLK)); + + /////////////////////////////////////////////////////////////////////// + // drive output clocks + /////////////////////////////////////////////////////////////////////// + ODDR #( + .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE" + .INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1 + .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" + ) + ODDR_U + ( + .Q(IFCLK), // 1-bit DDR output data + .C(gpif_clk), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D1(1'b1), // 1-bit data input (associated with C0) + .D2(1'b0), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0) // 1-bit set input + ); /////////////////////////////////////////////////////////////////////// // Create sync reset signals @@ -176,6 +204,19 @@ module b200 ( reset_sync bus_sync(.clk(bus_clk), .reset_in(!clocks_ready), .reset_out(bus_rst)); reset_sync radio_sync(.clk(radio_clk), .reset_in(!clocks_ready), .reset_out(radio_rst)); + + /////////////////////////////////////////////////////////////////////// + // PPS Switch 1.GPS_PPS 2.EXT_PPS + /////////////////////////////////////////////////////////////////////// + wire pps_ext_int; + pps_switch u_pps_switch ( + .clk (gpif_clk), + .rst_n (!gpif_rst), + .gps_pps (PPS_IN_INT), + .ext_pps (PPS_IN_EXT), + .pps_out (pps_ext_int) + ); + /////////////////////////////////////////////////////////////////////// // I/O /////////////////////////////////////////////////////////////////////// @@ -185,11 +226,12 @@ module b200 ( b200_io b200_io_i0 ( - .reset(reset), + .areset(reset_global), .mimo(mimo), // Baseband sample interface .radio_clk(radio_clk), + // .radio_rst(radio_rst), .rx_i0(rx_data0[31:20]), .rx_q0(rx_data0[15:4]), @@ -234,7 +276,7 @@ module b200 ( //The following signals are routed to the FX3 and were used by an obsolete //bit-banging SPI engine. // fx3_ce, fx3_sclk, fx3_mosi - assign fx3_miso = 1'bZ; //Safe state because we cannot guarantee the + // assign fx3_miso = 1'bZ; //Safe state because we cannot guarantee the //direction of this pin in the FX3 /////////////////////////////////////////////////////////////////////// @@ -294,10 +336,10 @@ module b200 ( .tx0(tx_data0), .tx1(tx_data1), .fe0_gpio_out(radio0_gpio), .fe1_gpio_out(radio1_gpio), .fp_gpio_in(fp_gpio_in), .fp_gpio_out(fp_gpio_out), .fp_gpio_ddr(fp_gpio_ddr), - - .pps_int(PPS_IN_INT), .pps_ext(PPS_IN_EXT), - - .rxd(gps_txd), .txd(gps_rxd), + + .pps_int(pps_ext_int), .pps_ext(pps_ext_int), + // .rxd(gps_txd), .txd(gps_rxd), + .pps(LED_CLK_R), .sclk(sclk), .sen(sen), .mosi(mosi), .miso(miso), .rb_misc({31'b0, pll_lock}), .misc_outs(misc_outs), @@ -360,6 +402,11 @@ module b200 ( /////////////////////////////////////////////////////////////////////// // Debug port /////////////////////////////////////////////////////////////////////// - assign debug = 0; + // assign debug = 0; + assign LED_STATUS = 'd1; + assign LED_CLK_G = 'd0; + + + endmodule // B200 diff --git a/top/b200/b200_core.v b/top/b200/b200_core.v index f03c5ea..fcc668d 100644 --- a/top/b200/b200_core.v +++ b/top/b200/b200_core.v @@ -21,7 +21,6 @@ module b200_core parameter EXTRA_BUFF_SIZE = 0, parameter RADIO_FIFO_SIZE = 11, parameter SAMPLE_FIFO_SIZE = 11 - ) ( //////////////////////////////////////////////////////////////////// @@ -73,7 +72,9 @@ module b200_core //////////////////////////////////////////////////////////////////// // debug signals //////////////////////////////////////////////////////////////////// - output [63:0] debug + output [63:0] debug, + + output pps ); localparam SR_CORE_SPI = 8'd8; localparam SR_CORE_MISC = 8'd16; @@ -111,7 +112,7 @@ module b200_core // PPS mux wire [1:0] pps_select; - wire pps = (pps_select == 2'b00)? gpsdo_pps_del[1] : + assign pps = (pps_select == 2'b00)? gpsdo_pps_del[1] : (pps_select == 2'b01)? ext_pps_del[1] : (pps_select == 2'b10)? int_pps_del[1] : 1'b0; @@ -307,7 +308,7 @@ module b200_core .NEW_HB_DECIM(1), .SOURCE_FLOW_CONTROL(0), .USER_SETTINGS(0), - .DEVICE("SPARTAN6") + .DEVICE("7SERIES") ) radio_0 ( .radio_clk(radio_clk), .radio_rst(radio_rst), .rx(rx0), .tx(tx0), .pps(pps), .time_sync(time_sync_r), @@ -339,7 +340,7 @@ module b200_core .NEW_HB_DECIM(1), .SOURCE_FLOW_CONTROL(0), .USER_SETTINGS(0), - .DEVICE("SPARTAN6") + .DEVICE("7SERIES") ) radio_1 ( .radio_clk(radio_clk), .radio_rst(radio_rst), .rx(rx1), .tx(tx1), .pps(pps), .time_sync(time_sync_r), diff --git a/top/b200/b200_io.v b/top/b200/b200_io.v index 1c6ea2d..da7c09e 100644 --- a/top/b200/b200_io.v +++ b/top/b200/b200_io.v @@ -1,554 +1,161 @@ // -// Copyright 2013 Ettus Research LLC -// Copyright 2017 Ettus Research, a National Instruments Company +// Copyright 2015 Ettus Research, A National Instruments Company +// SPDX-License-Identifier: LGPL-3.0 // -// SPDX-License-Identifier: LGPL-3.0-or-later +// Description: E31X IO for CMOS interface // -// -//------------------------------------------------------------------ -// -// In SISO mode, we output a clock thats 1x the frequency of the Catalina -// source-synchronous bus clock to be used as the radio_clk. -// In MIMO mode, we output a clock thats 1/2 the frequency of the Catalina -// source-synchronous bus clock to be used as the radio_clk. -// -//------------------------------------------------------------------ -module b200_io - ( - input reset, - input mimo, +module b200_io ( + input areset, + input mimo, + // Baseband sample interface + output radio_clk, + output radio_rst, + output reg [11:0] rx_i0, + output reg [11:0] rx_q0, + output reg [11:0] rx_i1, + output reg [11:0] rx_q1, + output reg rx_stb, + input [11:0] tx_i0, + input [11:0] tx_q0, + input [11:0] tx_i1, + input [11:0] tx_q1, + output reg tx_stb, + // AD9361 interface + input rx_clk, + input rx_frame, + input [11:0] rx_data, + output tx_clk, + output tx_frame, + output [11:0] tx_data +); - // Baseband sample interface - output radio_clk, - output [11:0] rx_i0, - output [11:0] rx_q0, - output [11:0] rx_i1, - output [11:0] rx_q1, - input [11:0] tx_i0, - input [11:0] tx_q0, - input [11:0] tx_i1, - input [11:0] tx_q1, + // Synchronize asynchronous reset and MIMO + synchronizer #(.STAGES(3), .INITIAL_VAL(1'b1)) sychronizer_radio_rst ( + .clk(radio_clk), .rst(areset), .in(1'b0), .out(radio_rst)); - // Catalina interface - input rx_clk, - input rx_frame, - input [11:0] rx_data, - output tx_clk, - output tx_frame, - output [11:0] tx_data - ); + wire mimo_sync; + synchronizer synchronizer_mimo (.clk(radio_clk), .rst(radio_rst), .in(mimo), .out(mimo_sync)); + + /**************************************************************************** + ** RX Capture Interface + ****************************************************************************/ + wire rx_clk_bufr; // Capture clock + wire rx_clk_mimo_bufr; + + BUFG bufr_rx_clk (.I(rx_clk), .O(rx_clk_bufr)); + + BUFR #( + .BUFR_DIVIDE("2"), // Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8" + .SIM_DEVICE("7SERIES") // Must be set to "7SERIES" + ) + BUFR_inst ( + .O(rx_clk_mimo_bufr), + .CE(1'b1), + .CLR(areset), + .I(rx_clk) + ); + + BUFGMUX #( + ) + BUFGMUX_inst ( + .O(radio_clk), + .I0(rx_clk_bufr), + .I1(rx_clk_mimo_bufr), + .S(mimo_sync) + ); - genvar z; + wire [11:0] rx_i, rx_q; + genvar n; + generate + for (n = 0; n < 12; n = n + 1) begin + IDDR #(.DDR_CLK_EDGE("SAME_EDGE")) iddr ( + .C(rx_clk_bufr), .CE(1'b1), .R(1'b0), .S(1'b0), + .D(rx_data[n]), .Q1(rx_q[n]), .Q2(rx_i[n])); + end + endgenerate - //------------------------------------------------------------------ - // - // Synchronize MIMO signal from bus_clk to siso_clk. - // - //------------------------------------------------------------------ - reg mimo_sync, mimo_sync2; + wire rx_frame_rising, rx_frame_falling; + IDDR #(.DDR_CLK_EDGE("SAME_EDGE")) iddr_frame ( + .C(rx_clk_bufr), .CE(1'b1), .R(1'b0), .S(1'b0), + .D(rx_frame), .Q1(rx_frame_rising), .Q2(rx_frame_falling)); - always @(posedge siso_clk) begin - mimo_sync <= mimo_sync2; - mimo_sync2 <= mimo; - end + always @(posedge rx_clk_bufr or posedge radio_rst) begin + if (radio_rst) begin + rx_stb <= 1'b0; + end else begin + if (mimo_sync) begin + if (rx_frame_rising) begin + rx_i0 <= rx_i; + rx_q0 <= rx_q; + end else begin + rx_i1 <= rx_i; + rx_q1 <= rx_q; + end + rx_stb <= ~rx_frame_rising; + end else begin + rx_i0 <= rx_i; + rx_q0 <= rx_q; + rx_i1 <= rx_i; + rx_q1 <= rx_q; + rx_stb <= 1'b1; + end + end + end + /**************************************************************************** + ** TX Output Interface + ****************************************************************************/ + reg [11:0] tx_i, tx_q; + reg tx_frame_int = 1'b1; + generate + for (n = 0; n < 12; n = n + 1) begin + ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr ( + .C(rx_clk_bufr), .CE(1'b1), .R(1'b0), .S(1'b0), + .D1(tx_i[n]), .D2(tx_q[n]), .Q(tx_data[n])); + end + endgenerate - //------------------------------------------------------------------ - // Clock Buffering. - // BUFIO2 drives all IDDR2 and ODDR2 cells directly in bank3. - // Need two pairs of BUFIO2 one pair each for Top Left and Bottom Left half banks. - //------------------------------------------------------------------ - wire rx_clk_buf; - wire mimo_clk_unbuf; - wire siso_clk_unbuf; - wire siso2_clk_unbuf; + ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr_frame ( + .C(rx_clk_bufr), .CE(1'b1), .R(1'b0), .S(1'b0), + // In SISO mode, TX frame is asserted only on the falling edge + .D1(tx_frame_int), .D2(tx_frame_int & mimo_sync), .Q(tx_frame)); - IBUFG clk_ibufg (.O(rx_clk_buf), .I(rx_clk)); + ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr_clk ( + .C(rx_clk_bufr), .CE(1'b1), .R(1'b0), .S(1'b0), + .D1(1'b1), .D2(1'b0), .Q(tx_clk)); - //------------------------------------------------------------------ - // - // Buffers for LEFT TOP half bank pins - // BUFIO2_X0Y22 - // - //------------------------------------------------------------------ - BUFIO2 #( - .DIVIDE(4), - .DIVIDE_BYPASS("FALSE"), - .I_INVERT("FALSE"), - .USE_DOUBLER("TRUE")) - clk_bufio_lt - ( - .IOCLK(io_clk_lt), - .DIVCLK(mimo_clk_unbuf), // Non-inverted source of 1/2x interface clock for radio_clk - .SERDESSTROBE(), - .I(rx_clk_buf) - ); + reg [11:0] tx_i1_hold, tx_q1_hold; + always @(posedge rx_clk_bufr or posedge radio_rst) begin + if (radio_rst) begin + tx_stb <= 1'b0; + tx_frame_int <= 1'b1; + end else begin + if (mimo_sync) begin + tx_stb <= ~tx_stb; + tx_frame_int <= tx_stb; + if (tx_stb) begin + tx_i <= tx_i0; + tx_q <= tx_q0; + tx_i1_hold <= tx_i1; + tx_q1_hold <= tx_q1; + end else begin + tx_i <= tx_i1_hold; + tx_q <= tx_q1_hold; + end + end else begin + tx_stb <= 1'b1; + tx_frame_int <= 1'b1; + if ({tx_i0,tx_q0} != 24'd0) begin + tx_i <= tx_i0; + tx_q <= tx_q0; + end else begin + tx_i <= tx_i1; + tx_q <= tx_q1; + end + end + end + end - // BUFIO2_X0Y23 - BUFIO2 #( - .DIVIDE(1), - .DIVIDE_BYPASS("FALSE"), - .I_INVERT("TRUE"), - .USE_DOUBLER("FALSE")) - clk_bufio_lt_b - ( - .IOCLK(io_clk_lt_b), - .DIVCLK(siso_clk2_unbuf), // Inverted source of 1x interface clock for radio_clk - .SERDESSTROBE(), - .I(rx_clk_buf) - ); - - //------------------------------------------------------------------ - // - // Buffers for LEFT BOTTOM half bank pins - // BUFIO2_X1Y14 - // - //------------------------------------------------------------------ - BUFIO2 #( - .DIVIDE(1), - .DIVIDE_BYPASS("FALSE"), - .I_INVERT("FALSE"), - .USE_DOUBLER("FALSE")) - clk_bufio_lb - ( - .IOCLK(io_clk_lb), - .DIVCLK(siso_clk_unbuf), // Non-inverted source of 1x interface clock for local IO use - .SERDESSTROBE(), - .I(rx_clk_buf) - ); - - // BUFIO2_X1Y15 - BUFIO2 #( - .DIVIDE(1), - .DIVIDE_BYPASS("FALSE"), - .I_INVERT("TRUE"), - .USE_DOUBLER("FALSE")) - clk_bufio_lb_b - ( - .IOCLK(io_clk_lb_b), - .DIVCLK(), - .SERDESSTROBE(), - .I(rx_clk_buf) - ); - - //------------------------------------------------------------------ - // Always-on SISO clk needed to load/unload DDR2 I/O Regs - //------------------------------------------------------------------ - BUFG siso_clk_bufg ( - .I(siso_clk_unbuf), - .O(siso_clk) - ); - - //------------------------------------------------------------------ - // 2-1 mux combined with BUFG to drive global radio_clk. - // Note: Not addressed setup/hold constraints of S input ...unsure if anything "bad" can happen here. - //------------------------------------------------------------------ - BUFGMUX #( - .CLK_SEL_TYPE("SYNC")) - radio_clk_bufg ( - .I0(siso_clk2_unbuf), - .I1(mimo_clk_unbuf), - .S(mimo_sync), - .O(radio_clk) - ); - - //------------------------------------------------------------------ - // RX Frame Signal - In bank 3 LB - //------------------------------------------------------------------ - wire rx_frame_0, rx_frame_1; - - IDDR2 #( - .DDR_ALIGNMENT("C0")) - iddr2_frame ( - .Q0(rx_frame_1), - .Q1(rx_frame_0), - .C0(io_clk_lb), - .C1(io_clk_lb_b), - .CE(1'b1), - .D(rx_frame), - .R(1'b0), - .S(1'b0)); - - reg rx_frame_d1, rx_frame_d2; - always @(posedge siso_clk) - if(~mimo_sync) - { rx_frame_d2, rx_frame_d1 } <= { rx_frame_1, 1'b0 }; - else - { rx_frame_d2, rx_frame_d1 } <= { rx_frame_d1, rx_frame_1 }; - - //------------------------------------------------------------------ - // RX Data Bus - In bank3 both LT and LB - //------------------------------------------------------------------ - wire [11:0] rx_i,rx_q; - - // Bit0 LB - IDDR2 #( - .DDR_ALIGNMENT("C0")) - iddr2_i0 ( - .Q0(rx_q[0]), - .Q1(rx_i[0]), - .C0(io_clk_lb), - .C1(io_clk_lb_b), - .CE(1'b1), - .D(rx_data[0]), - .R(1'b0), - .S(1'b0)); - - // Bit1 LB - IDDR2 #( - .DDR_ALIGNMENT("C0")) - iddr2_i1 ( - .Q0(rx_q[1]), - .Q1(rx_i[1]), - .C0(io_clk_lb), - .C1(io_clk_lb_b), - .CE(1'b1), - .D(rx_data[1]), - .R(1'b0), - .S(1'b0)); - - // Bit2 LB - IDDR2 #( - .DDR_ALIGNMENT("C0")) - iddr2_i2 ( - .Q0(rx_q[2]), - .Q1(rx_i[2]), - .C0(io_clk_lb), - .C1(io_clk_lb_b), - .CE(1'b1), - .D(rx_data[2]), - .R(1'b0), - .S(1'b0)); - - // Bit3 LT - IDDR2 #( - .DDR_ALIGNMENT("C0")) - iddr2_i3 ( - .Q0(rx_q[3]), - .Q1(rx_i[3]), - .C0(io_clk_lt), - .C1(io_clk_lt_b), - .CE(1'b1), - .D(rx_data[3]), - .R(1'b0), - .S(1'b0)); - - // Bit4 LB - IDDR2 #( - .DDR_ALIGNMENT("C0")) - iddr2_i4 ( - .Q0(rx_q[4]), - .Q1(rx_i[4]), - .C0(io_clk_lb), - .C1(io_clk_lb_b), - .CE(1'b1), - .D(rx_data[4]), - .R(1'b0), - .S(1'b0)); - - // Bit5 LT - IDDR2 #( - .DDR_ALIGNMENT("C0")) - iddr2_i5 ( - .Q0(rx_q[5]), - .Q1(rx_i[5]), - .C0(io_clk_lt), - .C1(io_clk_lt_b), - .CE(1'b1), - .D(rx_data[5]), - .R(1'b0), - .S(1'b0)); - - // Bit6 LB - IDDR2 #( - .DDR_ALIGNMENT("C0")) - iddr2_i6 ( - .Q0(rx_q[6]), - .Q1(rx_i[6]), - .C0(io_clk_lb), - .C1(io_clk_lb_b), - .CE(1'b1), - .D(rx_data[6]), - .R(1'b0), - .S(1'b0)); - - // Bit7 LT - IDDR2 #( - .DDR_ALIGNMENT("C0")) - iddr2_i7 ( - .Q0(rx_q[7]), - .Q1(rx_i[7]), - .C0(io_clk_lt), - .C1(io_clk_lt_b), - .CE(1'b1), - .D(rx_data[7]), - .R(1'b0), - .S(1'b0)); - - // Bit8 LB - IDDR2 #( - .DDR_ALIGNMENT("C0")) - iddr2_i8 ( - .Q0(rx_q[8]), - .Q1(rx_i[8]), - .C0(io_clk_lb), - .C1(io_clk_lb_b), - .CE(1'b1), - .D(rx_data[8]), - .R(1'b0), - .S(1'b0)); - - // Bit9 LT - IDDR2 #( - .DDR_ALIGNMENT("C0")) - iddr2_i9 ( - .Q0(rx_q[9]), - .Q1(rx_i[9]), - .C0(io_clk_lt), - .C1(io_clk_lt_b), - .CE(1'b1), - .D(rx_data[9]), - .R(1'b0), - .S(1'b0)); - - // Bit10 LB - IDDR2 #( - .DDR_ALIGNMENT("C0")) - iddr2_i10 ( - .Q0(rx_q[10]), - .Q1(rx_i[10]), - .C0(io_clk_lb), - .C1(io_clk_lb_b), - .CE(1'b1), - .D(rx_data[10]), - .R(1'b0), - .S(1'b0)); - - // Bit11 LB - IDDR2 #( - .DDR_ALIGNMENT("C0")) - iddr2_i11 ( - .Q0(rx_q[11]), - .Q1(rx_i[11]), - .C0(io_clk_lb), - .C1(io_clk_lb_b), - .CE(1'b1), - .D(rx_data[11]), - .R(1'b0), - .S(1'b0)); - - //------------------------------------------------------------------ - // - // De-mux I & Q, Ch A & B onto fullrate clock. - // - // In all modes we grab data from the IDDR2 using negedge of siso_clk. - // IDDR2 updates all Q pins on posedge of io_clk. siso_clk does not have aligned phase - // with siso_clk...siso_clk is always a little more delayed than io_clk. - // This small delay is always much smaller than half a clk cycle. Thus by sampling the Q outputs - // with negedge siso_clk we avoid any risk of a race condition (hold violation on receiveing register). - // - // In SISO mode data is replicated onto both CH0 and CH1 for max flexibility in using the DDC's. - // - //------------------------------------------------------------------ - reg [11:0] rx_i_del, rx_q_del; - reg [11:0] rx_i0_siso_pos; - reg [11:0] rx_q0_siso_pos; - reg [11:0] rx_i1_siso_pos; - reg [11:0] rx_q1_siso_pos; - reg [11:0] rx_i0_siso_neg; - reg [11:0] rx_q0_siso_neg; - reg [11:0] rx_i1_siso_neg; - reg [11:0] rx_q1_siso_neg; - reg [11:0] rx_i0_siso; - reg [11:0] rx_q0_siso; - reg [11:0] rx_i1_siso; - reg [11:0] rx_q1_siso; - - - always @(negedge siso_clk) - if(mimo_sync) - // rx_frame_0 was sampled by same falling io_clk edge as rx_i[x] - // rx_frame_0 == 0 causes I & Q to be allocated to CH0 - if(rx_frame_0) begin - rx_i_del[11:0] <= rx_i[11:0]; - rx_q_del[11:0] <= rx_q[11:0]; - end - else begin - // Deal with the fact that Ch A and Ch B are labelled in silkscreen opposite to their documentation in AD9361. - rx_i0_siso[11:0] <= rx_i[11:0]; - rx_q0_siso[11:0] <= rx_q[11:0]; - rx_i1_siso[11:0] <= rx_i_del[11:0]; - rx_q1_siso[11:0] <= rx_q_del[11:0]; - end - else begin - rx_i0_siso[11:0] <= rx_i[11:0]; - rx_q0_siso[11:0] <= rx_q[11:0]; - rx_i1_siso[11:0] <= rx_i[11:0]; - rx_q1_siso[11:0] <= rx_q[11:0]; - end // else: !if(rx_frame_0) - - //------------------------------------------------------------------ - // - // Now prepare data for crossing into radio_clk domain which can be for SISO mode (inverted) siso_clk or for MIMO mode siso_clk/2. - // In MIMO mode tx_strobe is used to maintain a known phase relationship betwwen siso_clk and radio_clk. - // (Note: Negedge or posedge is used conditionally so that we have massive margin against a fast-path race condition - // betwwen siso_clk and radio_clk). This kind of arrangement could still lead to confusion in timing analysis - // even if it works in the real world depending on how well the STA tool can do automatic case analysis. - // - //------------------------------------------------------------------ - // This code lock only relevent in MIMO mode. - always @(negedge siso_clk) - if (tx_strobe) - begin - rx_i0_siso_neg[11:0] <= rx_i0_siso[11:0]; - rx_q0_siso_neg[11:0] <= rx_q0_siso[11:0]; - rx_i1_siso_neg[11:0] <= rx_i1_siso[11:0]; - rx_q1_siso_neg[11:0] <= rx_q1_siso[11:0]; - end - // This code block only relevent in SISO mode. - always @(posedge siso_clk) - begin - rx_i0_siso_pos[11:0] <= rx_i0_siso[11:0]; - rx_q0_siso_pos[11:0] <= rx_q0_siso[11:0]; - rx_i1_siso_pos[11:0] <= rx_i1_siso[11:0]; - rx_q1_siso_pos[11:0] <= rx_q1_siso[11:0]; - end - - assign rx_i0 = (mimo_sync) ? rx_i0_siso_neg : rx_i0_siso_pos; - assign rx_q0 = (mimo_sync) ? rx_q0_siso_neg : rx_q0_siso_pos; - assign rx_i1 = (mimo_sync) ? rx_i1_siso_neg : rx_i1_siso_pos; - assign rx_q1 = (mimo_sync) ? rx_q1_siso_neg : rx_q1_siso_pos; - - - //------------------------------------------------------------------ - // TX Data Bus - In bank3 LB - //------------------------------------------------------------------ - reg [11:0] tx_i,tx_q; - reg tx_strobe_del; - - generate - for(z = 0; z < 12; z = z + 1) - begin : gen_pins - ODDR2 #( - .DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC")) - oddr2 ( - .Q(tx_data[z]), .C0(io_clk_lb), .C1(io_clk_lb_b), - .CE(1'b1), .D0(tx_i[z]), .D1(tx_q[z]), .R(1'b0), .S(1'b0)); - end - endgenerate - - //------------------------------------------------------------------ - // TX Frame Signal - In bank 3 LB - //------------------------------------------------------------------ - ODDR2 #( - .DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC")) - oddr2_frame ( - .Q(tx_frame), .C0(io_clk_lb), .C1(io_clk_lb_b), - .CE(1'b1), .D0(tx_strobe_del), .D1(mimo_sync & tx_strobe_del), .R(1'b0), .S(1'b0)); - - //------------------------------------------------------------------ - // TX Clock Signal - In bank 3 LB - //------------------------------------------------------------------ - ODDR2 #( - .DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC")) - oddr2_clk ( - .Q(tx_clk), .C0(io_clk_lb), .C1(io_clk_lb_b), - .CE(1'b1), .D0(1'b1), .D1(1'b0), .R(1'b0), .S(1'b0)); - - //------------------------------------------------------------------ - // - // Mux I & Q, Ch A & B onto fullrate clockTX bus to AD9361 - // - //------------------------------------------------------------------ - wire tx_strobe; - reg [11:0] tx_i_del, tx_q_del; - - reg find_radio_clk_phase = 1'b0; - reg find_radio_clk_phase_del; - - - always @(posedge radio_clk) - find_radio_clk_phase <= ~find_radio_clk_phase; - - always @(negedge radio_clk) - find_radio_clk_phase_del <= find_radio_clk_phase; - - assign tx_strobe = mimo_sync ? (find_radio_clk_phase_del ^ find_radio_clk_phase) : 1'b1; - - always @(posedge siso_clk) - tx_strobe_del <= tx_strobe; - - // This strange piece of logic allows either USRP DUC to drive the AD9361 in SISO mode. - // This is principly used in the CODEC loopback test. - wire [11:0] tx_im = (mimo_sync || tx_i0 != 12'h0) ? tx_i0 : tx_i1; - wire [11:0] tx_qm = (mimo_sync || tx_q0 != 12'h0) ? tx_q0 : tx_q1; - - - // Deal with the fact that Ch A and Ch B are labelled in silkscreen opposite to their documentation in AD9361. - // (Except on B200 based on AD9364 where only the true Ch A is stuffed) - always @(posedge siso_clk) - if(tx_strobe) - begin - {tx_i,tx_q} <= mimo_sync ? {tx_i1,tx_q1} : {tx_im,tx_qm}; - {tx_i_del,tx_q_del} <= {tx_i0,tx_q0}; - end - else - {tx_i,tx_q} <= {tx_i_del,tx_q_del}; - // - // Debug - // -/* -----\/----- EXCLUDED -----\/----- - wire [35:0] CONTROL0; - reg [11:0] tx_i_del_debug, tx_q_del_debug; - reg [11:0] tx_i_debug,tx_q_debug; - reg [11:0] tx_i0_debug,tx_q0_debug; - reg find_radio_clk_phase_debug; - reg find_radio_clk_phase_del_debug; - reg tx_strobe_debug; - reg tx_strobe_del_debug; - - - always @(posedge siso_clk) begin - tx_i_del_debug <= tx_i_del; - tx_q_del_debug <= tx_q_del; - tx_i_debug <= tx_i; - tx_q_debug <= tx_q; - tx_i0_debug <=tx_i0; - tx_q0_debug <= tx_q0; - find_radio_clk_phase_debug <= find_radio_clk_phase; - find_radio_clk_phase_del_debug <= find_radio_clk_phase_del; - tx_strobe_debug <= tx_strobe; - tx_strobe_del_debug <= tx_strobe_del; - end - - - - chipscope_icon chipscope_icon_i0 - ( - .CONTROL0(CONTROL0) // INOUT BUS [35:0] - ); - - chipscope_ila_128 chipscope_ila_i0 - ( - .CONTROL(CONTROL0), // INOUT BUS [35:0] - .CLK(siso_clk), // IN - .TRIG0( - { - tx_i_del_debug[11:0], - tx_q_del_debug[11:0], - tx_i_debug[11:0], - tx_q_debug[11:0], - tx_i0_debug[11:0], - tx_q0_debug[11:0], - find_radio_clk_phase_debug, - find_radio_clk_phase_del_debug, - tx_strobe_debug, - tx_strobe_del_debug - } - ) - - ); - -----/\----- EXCLUDED -----/\----- */ endmodule diff --git a/top/b200/b210.xdc b/top/b200/b210.xdc new file mode 100644 index 0000000..2f54486 --- /dev/null +++ b/top/b200/b210.xdc @@ -0,0 +1,185 @@ +set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVCMOS33} [get_ports PPS_IN_EXT] +set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS33} [get_ports PPS_IN_INT] + +set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVDS} [get_ports codec_main_clk_p] +set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVDS} [get_ports codec_main_clk_n] + +set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS33} [get_ports pll_ce] +set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS33} [get_ports pll_mosi] +set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS33} [get_ports pll_sclk] +set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS33} [get_ports ref_sel] +set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS33} [get_ports pll_lock] + +# set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33} [get_ports gps_rxd] +# set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33} [get_ports gps_txd] + +# #### FX3 Lines ############################################################## +# GPIF Data lines +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[0]}] +set_property -dict {PACKAGE_PIN AA3 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[1]}] +set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[2]}] +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[3]}] +set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[4]}] +set_property -dict {PACKAGE_PIN U1 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[5]}] +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[6]}] +set_property -dict {PACKAGE_PIN W4 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[7]}] +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[8]}] +set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[9]}] +set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[10]}] +set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[11]}] +set_property -dict {PACKAGE_PIN AA5 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[12]}] +set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[13]}] +set_property -dict {PACKAGE_PIN AC1 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[14]}] +set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[15]}] +set_property -dict {PACKAGE_PIN AE6 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[16]}] +set_property -dict {PACKAGE_PIN AD5 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[17]}] +set_property -dict {PACKAGE_PIN AD6 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[18]}] +set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[19]}] +set_property -dict {PACKAGE_PIN AE5 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[20]}] +set_property -dict {PACKAGE_PIN AF3 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[21]}] +set_property -dict {PACKAGE_PIN AE3 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[22]}] +set_property -dict {PACKAGE_PIN AF2 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[23]}] +set_property -dict {PACKAGE_PIN W3 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[24]}] +set_property -dict {PACKAGE_PIN AF4 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[25]}] +set_property -dict {PACKAGE_PIN AD4 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[26]}] +set_property -dict {PACKAGE_PIN AF5 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[27]}] +set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[28]}] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[29]}] +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[30]}] +set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[31]}] + +set_property -dict {PACKAGE_PIN AD1 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports IFCLK] +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS18} [get_ports FX3_EXTINT] + +# FX3 CTRL +set_property -dict {PACKAGE_PIN AA4 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL0] +set_property -dict {PACKAGE_PIN AE2 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL1] +set_property -dict {PACKAGE_PIN AE1 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL2] +set_property -dict {PACKAGE_PIN AC2 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL3] +set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL4] +set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL5] +set_property -dict {PACKAGE_PIN AD3 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL6] +set_property -dict {PACKAGE_PIN Y5 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL7] +set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL8] +set_property -dict {PACKAGE_PIN AB1 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL9] +set_property -dict {PACKAGE_PIN AC4 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL11] +set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL12] + +#debug uart +set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVCMOS18} [get_ports FPGA_RXD0] +set_property -dict {PACKAGE_PIN AE11 IOSTANDARD LVCMOS18} [get_ports FPGA_TXD0] +#GPIO + +set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {fp_gpio[0]}] +set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {fp_gpio[1]}] +set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {fp_gpio[2]}] +set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {fp_gpio[3]}] +set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {fp_gpio[4]}] +set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {fp_gpio[5]}] +set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {fp_gpio[6]}] +set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {fp_gpio[7]}] + +# LED +set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS33} [get_ports LED_TXRX1_RX] +set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS33} [get_ports LED_TXRX1_TX] +set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS33} [get_ports LED_RX1] +set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS33} [get_ports LED_RX2] +set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS33} [get_ports LED_TXRX2_RX] +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports LED_TXRX2_TX] + +set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports LED_STATUS] +set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVCMOS33} [get_ports LED_CLK_G] +set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS33} [get_ports LED_CLK_R] + +# CAT +set_property -dict {PACKAGE_PIN F23 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports codec_reset] +set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports codec_en_agc] +set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports codec_enable] +set_property -dict {PACKAGE_PIN G24 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports codec_txrx] +set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports codec_sync] +set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS18 SLEW SLOW PULLTYPE PULLUP } [get_ports cat_ce] +set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports cat_sclk] +set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports cat_mosi] +set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports cat_miso] +set_property -dict {PACKAGE_PIN F24 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports cat_clkout_fpga] + +# Control Lines +set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS18} [get_ports {codec_ctrl_out[0]}] +set_property -dict {PACKAGE_PIN C26 IOSTANDARD LVCMOS18} [get_ports {codec_ctrl_out[1]}] +set_property -dict {PACKAGE_PIN C24 IOSTANDARD LVCMOS18} [get_ports {codec_ctrl_out[2]}] +set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS18} [get_ports {codec_ctrl_out[3]}] +set_property -dict {PACKAGE_PIN C23 IOSTANDARD LVCMOS18} [get_ports {codec_ctrl_out[4]}] +set_property -dict {PACKAGE_PIN D24 IOSTANDARD LVCMOS18} [get_ports {codec_ctrl_out[5]}] +set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVCMOS18} [get_ports {codec_ctrl_out[6]}] +set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS18} [get_ports {codec_ctrl_out[7]}] + +set_property -dict {PACKAGE_PIN A24 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {codec_ctrl_in[0]}] +set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {codec_ctrl_in[1]}] +set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {codec_ctrl_in[2]}] +set_property -dict {PACKAGE_PIN A23 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {codec_ctrl_in[3]}] + +# Tx Bus P0 +set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[0]}] +set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[1]}] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[2]}] +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[3]}] +set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[4]}] +set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[5]}] +set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[6]}] +set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[7]}] +set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[8]}] +set_property -dict {PACKAGE_PIN Y15 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[9]}] +set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[10]}] +set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[11]}] + +# RX Bus P1 +set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[0]}] +set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[1]}] +set_property -dict {PACKAGE_PIN AE20 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[2]}] +set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[3]}] +set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[4]}] +set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[5]}] +set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[6]}] +set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[7]}] +set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[8]}] +set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[9]}] +set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[10]}] +set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[11]}] + +# Frame syncs +set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS18} [get_ports codec_data_clk_p] +set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS18} [get_ports rx_frame_p] +set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS18} [get_ports tx_frame_p] +set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS18} [get_ports codec_fb_clk_p] + +## RF Hardware Control +set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33} [get_ports SFDX1_RX] +set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS33} [get_ports SFDX1_TX] +set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS33} [get_ports SFDX2_RX] +set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS33} [get_ports SFDX2_TX] +set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33} [get_ports SRX1_RX] +set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports SRX1_TX] +set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS33} [get_ports SRX2_RX] +set_property -dict {PACKAGE_PIN G10 IOSTANDARD LVCMOS33} [get_ports SRX2_TX] +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports tx_bandsel_a] +set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVCMOS33} [get_ports tx_bandsel_b] +set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_a] +set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_b] +set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_c] + +set_property -dict {PACKAGE_PIN D13 IOSTANDARD LVCMOS33} [get_ports tx_enable1] +set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS33} [get_ports tx_enable2] + + +# IFCLK is 100 MHz GPIF clock +create_clock -period 10.000 -name IFCLK [get_ports IFCLK] +create_clock -period 16.276 -name codec_data_clk_p [get_ports codec_data_clk_p] + + + +set_false_path -from [get_clocks -of_objects [get_pins gen_clks/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks codec_data_clk_p] +set_false_path -from [get_clocks -of_objects [get_pins gen_clks/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins b200_io_i0/BUFR_inst/O]] +set_false_path -from [get_clocks codec_data_clk_p] -to [get_clocks -of_objects [get_pins gen_clks/inst/mmcm_adv_inst/CLKOUT1]] +set_false_path -from [get_clocks -of_objects [get_pins b200_io_i0/BUFR_inst/O]] -to [get_clocks -of_objects [get_pins gen_clks/inst/mmcm_adv_inst/CLKOUT1]] + +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] \ No newline at end of file diff --git a/top/b200/coregen_dsp/hbdec1.edif b/top/b200/coregen_dsp/hbdec1.edif new file mode 100644 index 0000000..3d2a17b --- /dev/null +++ b/top/b200/coregen_dsp/hbdec1.edif @@ -0,0 +1,69922 @@ +(edif hbdec1 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2018 8 29 14 59 34) + (program "Xilinx ngc2edif" (version "P_INT.20171106")) + (author "Xilinx. Inc ") + (comment "This EDIF netlist is to be used within supported synthesis tools") + (comment "for determining resource/timing estimates of the design component") + (comment "represented by this netlist.") + (comment "Command line: hbdec1.ngc hbdec1.edif "))) + (external UNISIMS + (edifLevel 0) + (technology (numberDefinition)) + (cell VCC + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port P + (direction OUTPUT) + ) + ) + ) + ) + (cell GND + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port G + (direction OUTPUT) + ) + ) + ) + ) + (cell FDRE + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port R + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell MUXCY_D + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT) + ) + (port DI + (direction INPUT) + ) + (port S + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + (port LO + (direction OUTPUT) + ) + ) + ) + ) + (cell XORCY + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT) + ) + (port LI + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell FD + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell DSP48E1 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port PATTERNBDETECT + (direction OUTPUT) + ) + (port RSTC + (direction INPUT) + ) + (port CEB1 + (direction INPUT) + ) + (port CEAD + (direction INPUT) + ) + (port MULTSIGNOUT + (direction OUTPUT) + ) + (port CEC + (direction INPUT) + ) + (port RSTM + (direction INPUT) + ) + (port MULTSIGNIN + (direction INPUT) + ) + (port CEB2 + (direction INPUT) + ) + (port RSTCTRL + (direction INPUT) + ) + (port CEP + (direction INPUT) + ) + (port CARRYCASCOUT + (direction OUTPUT) + ) + (port RSTA + (direction INPUT) + ) + (port CECARRYIN + (direction INPUT) + ) + (port UNDERFLOW + (direction OUTPUT) + ) + (port PATTERNDETECT + (direction OUTPUT) + ) + (port RSTALUMODE + (direction INPUT) + ) + (port RSTALLCARRYIN + (direction INPUT) + ) + (port CED + (direction INPUT) + ) + (port RSTD + (direction INPUT) + ) + (port CEALUMODE + (direction INPUT) + ) + (port CEA2 + (direction INPUT) + ) + (port CLK + (direction INPUT) + ) + (port CEA1 + (direction INPUT) + ) + (port RSTB + (direction INPUT) + ) + (port OVERFLOW + (direction OUTPUT) + ) + (port CECTRL + (direction INPUT) + ) + (port CEM + (direction INPUT) + ) + (port CARRYIN + (direction INPUT) + ) + (port CARRYCASCIN + (direction INPUT) + ) + (port RSTINMODE + (direction INPUT) + ) + (port CEINMODE + (direction INPUT) + ) + (port RSTP + (direction INPUT) + ) + (port (rename ACOUT_29_ "ACOUT<29>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename ACOUT_28_ "ACOUT<28>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename ACOUT_27_ "ACOUT<27>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename ACOUT_26_ "ACOUT<26>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename ACOUT_25_ "ACOUT<25>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename ACOUT_24_ "ACOUT<24>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 5) (owner "Xilinx")) + ) + (port (rename ACOUT_23_ "ACOUT<23>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 6) (owner "Xilinx")) + ) + (port (rename ACOUT_22_ "ACOUT<22>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 7) (owner "Xilinx")) + ) + (port (rename ACOUT_21_ "ACOUT<21>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 8) (owner "Xilinx")) + ) + (port (rename ACOUT_20_ "ACOUT<20>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 9) (owner "Xilinx")) + ) + (port (rename ACOUT_19_ "ACOUT<19>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 10) (owner "Xilinx")) + ) + (port (rename ACOUT_18_ "ACOUT<18>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 11) (owner "Xilinx")) + ) + (port (rename ACOUT_17_ "ACOUT<17>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 12) (owner "Xilinx")) + ) + (port (rename ACOUT_16_ "ACOUT<16>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 13) (owner "Xilinx")) + ) + (port (rename ACOUT_15_ "ACOUT<15>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 14) (owner "Xilinx")) + ) + (port (rename ACOUT_14_ "ACOUT<14>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 15) (owner "Xilinx")) + ) + (port (rename ACOUT_13_ "ACOUT<13>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 16) (owner "Xilinx")) + ) + (port (rename ACOUT_12_ "ACOUT<12>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 17) (owner "Xilinx")) + ) + (port (rename ACOUT_11_ "ACOUT<11>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 18) (owner "Xilinx")) + ) + (port (rename ACOUT_10_ "ACOUT<10>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 19) (owner "Xilinx")) + ) + (port (rename ACOUT_9_ "ACOUT<9>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 20) (owner "Xilinx")) + ) + (port (rename ACOUT_8_ "ACOUT<8>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 21) (owner "Xilinx")) + ) + (port (rename ACOUT_7_ "ACOUT<7>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 22) (owner "Xilinx")) + ) + (port (rename ACOUT_6_ "ACOUT<6>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 23) (owner "Xilinx")) + ) + (port (rename ACOUT_5_ "ACOUT<5>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 24) (owner "Xilinx")) + ) + (port (rename ACOUT_4_ "ACOUT<4>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 25) (owner "Xilinx")) + ) + (port (rename ACOUT_3_ "ACOUT<3>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 26) (owner "Xilinx")) + ) + (port (rename ACOUT_2_ "ACOUT<2>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 27) (owner "Xilinx")) + ) + (port (rename ACOUT_1_ "ACOUT<1>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 28) (owner "Xilinx")) + ) + (port (rename ACOUT_0_ "ACOUT<0>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 29) (owner "Xilinx")) + ) + (port (rename OPMODE_6_ "OPMODE<6>") + (direction INPUT) + (property PIN_BUSNAME (string "OPMODE<6:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename OPMODE_5_ "OPMODE<5>") + (direction INPUT) + (property PIN_BUSNAME (string "OPMODE<6:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename OPMODE_4_ "OPMODE<4>") + (direction INPUT) + (property PIN_BUSNAME (string "OPMODE<6:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename OPMODE_3_ "OPMODE<3>") + (direction INPUT) + (property PIN_BUSNAME (string "OPMODE<6:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename OPMODE_2_ "OPMODE<2>") + (direction INPUT) + (property PIN_BUSNAME (string "OPMODE<6:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename OPMODE_1_ "OPMODE<1>") + (direction INPUT) + (property PIN_BUSNAME (string "OPMODE<6:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 5) (owner "Xilinx")) + ) + (port (rename OPMODE_0_ "OPMODE<0>") + (direction INPUT) + (property PIN_BUSNAME (string "OPMODE<6:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 6) (owner "Xilinx")) + ) + (port (rename PCIN_47_ "PCIN<47>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename PCIN_46_ "PCIN<46>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename PCIN_45_ "PCIN<45>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename PCIN_44_ "PCIN<44>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename PCIN_43_ "PCIN<43>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename PCIN_42_ "PCIN<42>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 5) (owner "Xilinx")) + ) + (port (rename PCIN_41_ "PCIN<41>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 6) (owner "Xilinx")) + ) + (port (rename PCIN_40_ "PCIN<40>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 7) (owner "Xilinx")) + ) + (port (rename PCIN_39_ "PCIN<39>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 8) (owner "Xilinx")) + ) + (port (rename PCIN_38_ "PCIN<38>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 9) (owner "Xilinx")) + ) + (port (rename PCIN_37_ "PCIN<37>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 10) (owner "Xilinx")) + ) + (port (rename PCIN_36_ "PCIN<36>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 11) (owner "Xilinx")) + ) + (port (rename PCIN_35_ "PCIN<35>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 12) (owner "Xilinx")) + ) + (port (rename PCIN_34_ "PCIN<34>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 13) (owner "Xilinx")) + ) + (port (rename PCIN_33_ "PCIN<33>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 14) (owner "Xilinx")) + ) + (port (rename PCIN_32_ "PCIN<32>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 15) (owner "Xilinx")) + ) + (port (rename PCIN_31_ "PCIN<31>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 16) (owner "Xilinx")) + ) + (port (rename PCIN_30_ "PCIN<30>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 17) (owner "Xilinx")) + ) + (port (rename PCIN_29_ "PCIN<29>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 18) (owner "Xilinx")) + ) + (port (rename PCIN_28_ "PCIN<28>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 19) (owner "Xilinx")) + ) + (port (rename PCIN_27_ "PCIN<27>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 20) (owner "Xilinx")) + ) + (port (rename PCIN_26_ "PCIN<26>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 21) (owner "Xilinx")) + ) + (port (rename PCIN_25_ "PCIN<25>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 22) (owner "Xilinx")) + ) + (port (rename PCIN_24_ "PCIN<24>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 23) (owner "Xilinx")) + ) + (port (rename PCIN_23_ "PCIN<23>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 24) (owner "Xilinx")) + ) + (port (rename PCIN_22_ "PCIN<22>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 25) (owner "Xilinx")) + ) + (port (rename PCIN_21_ "PCIN<21>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 26) (owner "Xilinx")) + ) + (port (rename PCIN_20_ "PCIN<20>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 27) (owner "Xilinx")) + ) + (port (rename PCIN_19_ "PCIN<19>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 28) (owner "Xilinx")) + ) + (port (rename PCIN_18_ "PCIN<18>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 29) (owner "Xilinx")) + ) + (port (rename PCIN_17_ "PCIN<17>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 30) (owner "Xilinx")) + ) + (port (rename PCIN_16_ "PCIN<16>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 31) (owner "Xilinx")) + ) + (port (rename PCIN_15_ "PCIN<15>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 32) (owner "Xilinx")) + ) + (port (rename PCIN_14_ "PCIN<14>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 33) (owner "Xilinx")) + ) + (port (rename PCIN_13_ "PCIN<13>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 34) (owner "Xilinx")) + ) + (port (rename PCIN_12_ "PCIN<12>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 35) (owner "Xilinx")) + ) + (port (rename PCIN_11_ "PCIN<11>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 36) (owner "Xilinx")) + ) + (port (rename PCIN_10_ "PCIN<10>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 37) (owner "Xilinx")) + ) + (port (rename PCIN_9_ "PCIN<9>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 38) (owner "Xilinx")) + ) + (port (rename PCIN_8_ "PCIN<8>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 39) (owner "Xilinx")) + ) + (port (rename PCIN_7_ "PCIN<7>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 40) (owner "Xilinx")) + ) + (port (rename PCIN_6_ "PCIN<6>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 41) (owner "Xilinx")) + ) + (port (rename PCIN_5_ "PCIN<5>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 42) (owner "Xilinx")) + ) + (port (rename PCIN_4_ "PCIN<4>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 43) (owner "Xilinx")) + ) + (port (rename PCIN_3_ "PCIN<3>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 44) (owner "Xilinx")) + ) + (port (rename PCIN_2_ "PCIN<2>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 45) (owner "Xilinx")) + ) + (port (rename PCIN_1_ "PCIN<1>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 46) (owner "Xilinx")) + ) + (port (rename PCIN_0_ "PCIN<0>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 47) (owner "Xilinx")) + ) + (port (rename ALUMODE_3_ "ALUMODE<3>") + (direction INPUT) + (property PIN_BUSNAME (string "ALUMODE<3:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename ALUMODE_2_ "ALUMODE<2>") + (direction INPUT) + (property PIN_BUSNAME (string "ALUMODE<3:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename ALUMODE_1_ "ALUMODE<1>") + (direction INPUT) + (property PIN_BUSNAME (string "ALUMODE<3:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename ALUMODE_0_ "ALUMODE<0>") + (direction INPUT) + (property PIN_BUSNAME (string "ALUMODE<3:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename C_47_ "C<47>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename C_46_ "C<46>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename C_45_ "C<45>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename C_44_ "C<44>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename C_43_ "C<43>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename C_42_ "C<42>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 5) (owner "Xilinx")) + ) + (port (rename C_41_ "C<41>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 6) (owner "Xilinx")) + ) + (port (rename C_40_ "C<40>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 7) (owner "Xilinx")) + ) + (port (rename C_39_ "C<39>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 8) (owner "Xilinx")) + ) + (port (rename C_38_ "C<38>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 9) (owner "Xilinx")) + ) + (port (rename C_37_ "C<37>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 10) (owner "Xilinx")) + ) + (port (rename C_36_ "C<36>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 11) (owner "Xilinx")) + ) + (port (rename C_35_ "C<35>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 12) (owner "Xilinx")) + ) + (port (rename C_34_ "C<34>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 13) (owner "Xilinx")) + ) + (port (rename C_33_ "C<33>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 14) (owner "Xilinx")) + ) + (port (rename C_32_ "C<32>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 15) (owner "Xilinx")) + ) + (port (rename C_31_ "C<31>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 16) (owner "Xilinx")) + ) + (port (rename C_30_ "C<30>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 17) (owner "Xilinx")) + ) + (port (rename C_29_ "C<29>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 18) (owner "Xilinx")) + ) + (port (rename C_28_ "C<28>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 19) (owner "Xilinx")) + ) + (port (rename C_27_ "C<27>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 20) (owner "Xilinx")) + ) + (port (rename C_26_ "C<26>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 21) (owner "Xilinx")) + ) + (port (rename C_25_ "C<25>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 22) (owner "Xilinx")) + ) + (port (rename C_24_ "C<24>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 23) (owner "Xilinx")) + ) + (port (rename C_23_ "C<23>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 24) (owner "Xilinx")) + ) + (port (rename C_22_ "C<22>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 25) (owner "Xilinx")) + ) + (port (rename C_21_ "C<21>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 26) (owner "Xilinx")) + ) + (port (rename C_20_ "C<20>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 27) (owner "Xilinx")) + ) + (port (rename C_19_ "C<19>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 28) (owner "Xilinx")) + ) + (port (rename C_18_ "C<18>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 29) (owner "Xilinx")) + ) + (port (rename C_17_ "C<17>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 30) (owner "Xilinx")) + ) + (port (rename C_16_ "C<16>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 31) (owner "Xilinx")) + ) + (port (rename C_15_ "C<15>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 32) (owner "Xilinx")) + ) + (port (rename C_14_ "C<14>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 33) (owner "Xilinx")) + ) + (port (rename C_13_ "C<13>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 34) (owner "Xilinx")) + ) + (port (rename C_12_ "C<12>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 35) (owner "Xilinx")) + ) + (port (rename C_11_ "C<11>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 36) (owner "Xilinx")) + ) + (port (rename C_10_ "C<10>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 37) (owner "Xilinx")) + ) + (port (rename C_9_ "C<9>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 38) (owner "Xilinx")) + ) + (port (rename C_8_ "C<8>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 39) (owner "Xilinx")) + ) + (port (rename C_7_ "C<7>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 40) (owner "Xilinx")) + ) + (port (rename C_6_ "C<6>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 41) (owner "Xilinx")) + ) + (port (rename C_5_ "C<5>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 42) (owner "Xilinx")) + ) + (port (rename C_4_ "C<4>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 43) (owner "Xilinx")) + ) + (port (rename C_3_ "C<3>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 44) (owner "Xilinx")) + ) + (port (rename C_2_ "C<2>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 45) (owner "Xilinx")) + ) + (port (rename C_1_ "C<1>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 46) (owner "Xilinx")) + ) + (port (rename C_0_ "C<0>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 47) (owner "Xilinx")) + ) + (port (rename CARRYOUT_3_ "CARRYOUT<3>") + (direction OUTPUT) + (property PIN_BUSNAME (string "CARRYOUT<3:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename CARRYOUT_2_ "CARRYOUT<2>") + (direction OUTPUT) + (property PIN_BUSNAME (string "CARRYOUT<3:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename CARRYOUT_1_ "CARRYOUT<1>") + (direction OUTPUT) + (property PIN_BUSNAME (string "CARRYOUT<3:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename CARRYOUT_0_ "CARRYOUT<0>") + (direction OUTPUT) + (property PIN_BUSNAME (string "CARRYOUT<3:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename INMODE_4_ "INMODE<4>") + (direction INPUT) + (property PIN_BUSNAME (string "INMODE<4:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename INMODE_3_ "INMODE<3>") + (direction INPUT) + (property PIN_BUSNAME (string "INMODE<4:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename INMODE_2_ "INMODE<2>") + (direction INPUT) + (property PIN_BUSNAME (string "INMODE<4:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename INMODE_1_ "INMODE<1>") + (direction INPUT) + (property PIN_BUSNAME (string "INMODE<4:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename INMODE_0_ "INMODE<0>") + (direction INPUT) + (property PIN_BUSNAME (string "INMODE<4:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename BCIN_17_ "BCIN<17>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename BCIN_16_ "BCIN<16>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename BCIN_15_ "BCIN<15>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename BCIN_14_ "BCIN<14>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename BCIN_13_ "BCIN<13>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename BCIN_12_ "BCIN<12>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 5) (owner "Xilinx")) + ) + (port (rename BCIN_11_ "BCIN<11>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 6) (owner "Xilinx")) + ) + (port (rename BCIN_10_ "BCIN<10>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 7) (owner "Xilinx")) + ) + (port (rename BCIN_9_ "BCIN<9>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 8) (owner "Xilinx")) + ) + (port (rename BCIN_8_ "BCIN<8>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 9) (owner "Xilinx")) + ) + (port (rename BCIN_7_ "BCIN<7>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 10) (owner "Xilinx")) + ) + (port (rename BCIN_6_ "BCIN<6>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 11) (owner "Xilinx")) + ) + (port (rename BCIN_5_ "BCIN<5>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 12) (owner "Xilinx")) + ) + (port (rename BCIN_4_ "BCIN<4>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 13) (owner "Xilinx")) + ) + (port (rename BCIN_3_ "BCIN<3>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 14) (owner "Xilinx")) + ) + (port (rename BCIN_2_ "BCIN<2>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 15) (owner "Xilinx")) + ) + (port (rename BCIN_1_ "BCIN<1>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 16) (owner "Xilinx")) + ) + (port (rename BCIN_0_ "BCIN<0>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 17) (owner "Xilinx")) + ) + (port (rename B_17_ "B<17>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename B_16_ "B<16>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename B_15_ "B<15>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename B_14_ "B<14>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename B_13_ "B<13>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename B_12_ "B<12>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 5) (owner "Xilinx")) + ) + (port (rename B_11_ "B<11>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 6) (owner "Xilinx")) + ) + (port (rename B_10_ "B<10>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 7) (owner "Xilinx")) + ) + (port (rename B_9_ "B<9>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 8) (owner "Xilinx")) + ) + (port (rename B_8_ "B<8>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 9) (owner "Xilinx")) + ) + (port (rename B_7_ "B<7>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 10) (owner "Xilinx")) + ) + (port (rename B_6_ "B<6>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 11) (owner "Xilinx")) + ) + (port (rename B_5_ "B<5>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 12) (owner "Xilinx")) + ) + (port (rename B_4_ "B<4>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 13) (owner "Xilinx")) + ) + (port (rename B_3_ "B<3>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 14) (owner "Xilinx")) + ) + (port (rename B_2_ "B<2>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 15) (owner "Xilinx")) + ) + (port (rename B_1_ "B<1>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 16) (owner "Xilinx")) + ) + (port (rename B_0_ "B<0>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 17) (owner "Xilinx")) + ) + (port (rename BCOUT_17_ "BCOUT<17>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename BCOUT_16_ "BCOUT<16>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename BCOUT_15_ "BCOUT<15>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename BCOUT_14_ "BCOUT<14>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename BCOUT_13_ "BCOUT<13>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename BCOUT_12_ "BCOUT<12>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 5) (owner "Xilinx")) + ) + (port (rename BCOUT_11_ "BCOUT<11>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 6) (owner "Xilinx")) + ) + (port (rename BCOUT_10_ "BCOUT<10>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 7) (owner "Xilinx")) + ) + (port (rename BCOUT_9_ "BCOUT<9>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 8) (owner "Xilinx")) + ) + (port (rename BCOUT_8_ "BCOUT<8>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 9) (owner "Xilinx")) + ) + (port (rename BCOUT_7_ "BCOUT<7>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 10) (owner "Xilinx")) + ) + (port (rename BCOUT_6_ "BCOUT<6>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 11) (owner "Xilinx")) + ) + (port (rename BCOUT_5_ "BCOUT<5>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 12) (owner "Xilinx")) + ) + (port (rename BCOUT_4_ "BCOUT<4>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 13) (owner "Xilinx")) + ) + (port (rename BCOUT_3_ "BCOUT<3>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 14) (owner "Xilinx")) + ) + (port (rename BCOUT_2_ "BCOUT<2>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 15) (owner "Xilinx")) + ) + (port (rename BCOUT_1_ "BCOUT<1>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 16) (owner "Xilinx")) + ) + (port (rename BCOUT_0_ "BCOUT<0>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 17) (owner "Xilinx")) + ) + (port (rename D_24_ "D<24>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename D_23_ "D<23>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename D_22_ "D<22>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename D_21_ "D<21>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename D_20_ "D<20>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename D_19_ "D<19>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 5) (owner "Xilinx")) + ) + (port (rename D_18_ "D<18>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 6) (owner "Xilinx")) + ) + (port (rename D_17_ "D<17>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 7) (owner "Xilinx")) + ) + (port (rename D_16_ "D<16>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 8) (owner "Xilinx")) + ) + (port (rename D_15_ "D<15>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 9) (owner "Xilinx")) + ) + (port (rename D_14_ "D<14>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 10) (owner "Xilinx")) + ) + (port (rename D_13_ "D<13>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 11) (owner "Xilinx")) + ) + (port (rename D_12_ "D<12>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 12) (owner "Xilinx")) + ) + (port (rename D_11_ "D<11>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 13) (owner "Xilinx")) + ) + (port (rename D_10_ "D<10>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 14) (owner "Xilinx")) + ) + (port (rename D_9_ "D<9>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 15) (owner "Xilinx")) + ) + (port (rename D_8_ "D<8>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 16) (owner "Xilinx")) + ) + (port (rename D_7_ "D<7>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 17) (owner "Xilinx")) + ) + (port (rename D_6_ "D<6>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 18) (owner "Xilinx")) + ) + (port (rename D_5_ "D<5>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 19) (owner "Xilinx")) + ) + (port (rename D_4_ "D<4>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 20) (owner "Xilinx")) + ) + (port (rename D_3_ "D<3>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 21) (owner "Xilinx")) + ) + (port (rename D_2_ "D<2>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 22) (owner "Xilinx")) + ) + (port (rename D_1_ "D<1>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 23) (owner "Xilinx")) + ) + (port (rename D_0_ "D<0>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 24) (owner "Xilinx")) + ) + (port (rename P_47_ "P<47>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename P_46_ "P<46>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename P_45_ "P<45>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename P_44_ "P<44>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename P_43_ "P<43>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename P_42_ "P<42>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 5) (owner "Xilinx")) + ) + (port (rename P_41_ "P<41>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 6) (owner "Xilinx")) + ) + (port (rename P_40_ "P<40>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 7) (owner "Xilinx")) + ) + (port (rename P_39_ "P<39>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 8) (owner "Xilinx")) + ) + (port (rename P_38_ "P<38>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 9) (owner "Xilinx")) + ) + (port (rename P_37_ "P<37>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 10) (owner "Xilinx")) + ) + (port (rename P_36_ "P<36>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 11) (owner "Xilinx")) + ) + (port (rename P_35_ "P<35>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 12) (owner "Xilinx")) + ) + (port (rename P_34_ "P<34>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 13) (owner "Xilinx")) + ) + (port (rename P_33_ "P<33>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 14) (owner "Xilinx")) + ) + (port (rename P_32_ "P<32>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 15) (owner "Xilinx")) + ) + (port (rename P_31_ "P<31>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 16) (owner "Xilinx")) + ) + (port (rename P_30_ "P<30>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 17) (owner "Xilinx")) + ) + (port (rename P_29_ "P<29>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 18) (owner "Xilinx")) + ) + (port (rename P_28_ "P<28>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 19) (owner "Xilinx")) + ) + (port (rename P_27_ "P<27>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 20) (owner "Xilinx")) + ) + (port (rename P_26_ "P<26>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 21) (owner "Xilinx")) + ) + (port (rename P_25_ "P<25>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 22) (owner "Xilinx")) + ) + (port (rename P_24_ "P<24>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 23) (owner "Xilinx")) + ) + (port (rename P_23_ "P<23>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 24) (owner "Xilinx")) + ) + (port (rename P_22_ "P<22>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 25) (owner "Xilinx")) + ) + (port (rename P_21_ "P<21>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 26) (owner "Xilinx")) + ) + (port (rename P_20_ "P<20>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 27) (owner "Xilinx")) + ) + (port (rename P_19_ "P<19>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 28) (owner "Xilinx")) + ) + (port (rename P_18_ "P<18>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 29) (owner "Xilinx")) + ) + (port (rename P_17_ "P<17>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 30) (owner "Xilinx")) + ) + (port (rename P_16_ "P<16>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 31) (owner "Xilinx")) + ) + (port (rename P_15_ "P<15>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 32) (owner "Xilinx")) + ) + (port (rename P_14_ "P<14>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 33) (owner "Xilinx")) + ) + (port (rename P_13_ "P<13>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 34) (owner "Xilinx")) + ) + (port (rename P_12_ "P<12>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 35) (owner "Xilinx")) + ) + (port (rename P_11_ "P<11>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 36) (owner "Xilinx")) + ) + (port (rename P_10_ "P<10>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 37) (owner "Xilinx")) + ) + (port (rename P_9_ "P<9>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 38) (owner "Xilinx")) + ) + (port (rename P_8_ "P<8>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 39) (owner "Xilinx")) + ) + (port (rename P_7_ "P<7>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 40) (owner "Xilinx")) + ) + (port (rename P_6_ "P<6>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 41) (owner "Xilinx")) + ) + (port (rename P_5_ "P<5>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 42) (owner "Xilinx")) + ) + (port (rename P_4_ "P<4>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 43) (owner "Xilinx")) + ) + (port (rename P_3_ "P<3>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 44) (owner "Xilinx")) + ) + (port (rename P_2_ "P<2>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 45) (owner "Xilinx")) + ) + (port (rename P_1_ "P<1>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 46) (owner "Xilinx")) + ) + (port (rename P_0_ "P<0>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 47) (owner "Xilinx")) + ) + (port (rename A_29_ "A<29>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename A_28_ "A<28>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename A_27_ "A<27>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename A_26_ "A<26>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename A_25_ "A<25>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename A_24_ "A<24>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 5) (owner "Xilinx")) + ) + (port (rename A_23_ "A<23>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 6) (owner "Xilinx")) + ) + (port (rename A_22_ "A<22>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 7) (owner "Xilinx")) + ) + (port (rename A_21_ "A<21>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 8) (owner "Xilinx")) + ) + (port (rename A_20_ "A<20>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 9) (owner "Xilinx")) + ) + (port (rename A_19_ "A<19>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 10) (owner "Xilinx")) + ) + (port (rename A_18_ "A<18>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 11) (owner "Xilinx")) + ) + (port (rename A_17_ "A<17>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 12) (owner "Xilinx")) + ) + (port (rename A_16_ "A<16>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 13) (owner "Xilinx")) + ) + (port (rename A_15_ "A<15>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 14) (owner "Xilinx")) + ) + (port (rename A_14_ "A<14>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 15) (owner "Xilinx")) + ) + (port (rename A_13_ "A<13>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 16) (owner "Xilinx")) + ) + (port (rename A_12_ "A<12>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 17) (owner "Xilinx")) + ) + (port (rename A_11_ "A<11>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 18) (owner "Xilinx")) + ) + (port (rename A_10_ "A<10>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 19) (owner "Xilinx")) + ) + (port (rename A_9_ "A<9>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 20) (owner "Xilinx")) + ) + (port (rename A_8_ "A<8>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 21) (owner "Xilinx")) + ) + (port (rename A_7_ "A<7>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 22) (owner "Xilinx")) + ) + (port (rename A_6_ "A<6>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 23) (owner "Xilinx")) + ) + (port (rename A_5_ "A<5>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 24) (owner "Xilinx")) + ) + (port (rename A_4_ "A<4>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 25) (owner "Xilinx")) + ) + (port (rename A_3_ "A<3>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 26) (owner "Xilinx")) + ) + (port (rename A_2_ "A<2>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 27) (owner "Xilinx")) + ) + (port (rename A_1_ "A<1>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 28) (owner "Xilinx")) + ) + (port (rename A_0_ "A<0>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 29) (owner "Xilinx")) + ) + (port (rename PCOUT_47_ "PCOUT<47>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename PCOUT_46_ "PCOUT<46>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename PCOUT_45_ "PCOUT<45>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename PCOUT_44_ "PCOUT<44>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename PCOUT_43_ "PCOUT<43>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename PCOUT_42_ "PCOUT<42>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 5) (owner "Xilinx")) + ) + (port (rename PCOUT_41_ "PCOUT<41>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 6) (owner "Xilinx")) + ) + (port (rename PCOUT_40_ "PCOUT<40>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 7) (owner "Xilinx")) + ) + (port (rename PCOUT_39_ "PCOUT<39>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 8) (owner "Xilinx")) + ) + (port (rename PCOUT_38_ "PCOUT<38>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 9) (owner "Xilinx")) + ) + (port (rename PCOUT_37_ "PCOUT<37>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 10) (owner "Xilinx")) + ) + (port (rename PCOUT_36_ "PCOUT<36>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 11) (owner "Xilinx")) + ) + (port (rename PCOUT_35_ "PCOUT<35>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 12) (owner "Xilinx")) + ) + (port (rename PCOUT_34_ "PCOUT<34>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 13) (owner "Xilinx")) + ) + (port (rename PCOUT_33_ "PCOUT<33>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 14) (owner "Xilinx")) + ) + (port (rename PCOUT_32_ "PCOUT<32>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 15) (owner "Xilinx")) + ) + (port (rename PCOUT_31_ "PCOUT<31>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 16) (owner "Xilinx")) + ) + (port (rename PCOUT_30_ "PCOUT<30>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 17) (owner "Xilinx")) + ) + (port (rename PCOUT_29_ "PCOUT<29>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 18) (owner "Xilinx")) + ) + (port (rename PCOUT_28_ "PCOUT<28>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 19) (owner "Xilinx")) + ) + (port (rename PCOUT_27_ "PCOUT<27>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 20) (owner "Xilinx")) + ) + (port (rename PCOUT_26_ "PCOUT<26>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 21) (owner "Xilinx")) + ) + (port (rename PCOUT_25_ "PCOUT<25>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 22) (owner "Xilinx")) + ) + (port (rename PCOUT_24_ "PCOUT<24>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 23) (owner "Xilinx")) + ) + (port (rename PCOUT_23_ "PCOUT<23>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 24) (owner "Xilinx")) + ) + (port (rename PCOUT_22_ "PCOUT<22>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 25) (owner "Xilinx")) + ) + (port (rename PCOUT_21_ "PCOUT<21>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 26) (owner "Xilinx")) + ) + (port (rename PCOUT_20_ "PCOUT<20>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 27) (owner "Xilinx")) + ) + (port (rename PCOUT_19_ "PCOUT<19>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 28) (owner "Xilinx")) + ) + (port (rename PCOUT_18_ "PCOUT<18>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 29) (owner "Xilinx")) + ) + (port (rename PCOUT_17_ "PCOUT<17>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 30) (owner "Xilinx")) + ) + (port (rename PCOUT_16_ "PCOUT<16>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 31) (owner "Xilinx")) + ) + (port (rename PCOUT_15_ "PCOUT<15>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 32) (owner "Xilinx")) + ) + (port (rename PCOUT_14_ "PCOUT<14>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 33) (owner "Xilinx")) + ) + (port (rename PCOUT_13_ "PCOUT<13>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 34) (owner "Xilinx")) + ) + (port (rename PCOUT_12_ "PCOUT<12>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 35) (owner "Xilinx")) + ) + (port (rename PCOUT_11_ "PCOUT<11>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 36) (owner "Xilinx")) + ) + (port (rename PCOUT_10_ "PCOUT<10>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 37) (owner "Xilinx")) + ) + (port (rename PCOUT_9_ "PCOUT<9>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 38) (owner "Xilinx")) + ) + (port (rename PCOUT_8_ "PCOUT<8>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 39) (owner "Xilinx")) + ) + (port (rename PCOUT_7_ "PCOUT<7>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 40) (owner "Xilinx")) + ) + (port (rename PCOUT_6_ "PCOUT<6>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 41) (owner "Xilinx")) + ) + (port (rename PCOUT_5_ "PCOUT<5>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 42) (owner "Xilinx")) + ) + (port (rename PCOUT_4_ "PCOUT<4>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 43) (owner "Xilinx")) + ) + (port (rename PCOUT_3_ "PCOUT<3>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 44) (owner "Xilinx")) + ) + (port (rename PCOUT_2_ "PCOUT<2>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 45) (owner "Xilinx")) + ) + (port (rename PCOUT_1_ "PCOUT<1>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 46) (owner "Xilinx")) + ) + (port (rename PCOUT_0_ "PCOUT<0>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 47) (owner "Xilinx")) + ) + (port (rename ACIN_29_ "ACIN<29>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename ACIN_28_ "ACIN<28>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename ACIN_27_ "ACIN<27>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename ACIN_26_ "ACIN<26>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename ACIN_25_ "ACIN<25>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename ACIN_24_ "ACIN<24>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 5) (owner "Xilinx")) + ) + (port (rename ACIN_23_ "ACIN<23>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 6) (owner "Xilinx")) + ) + (port (rename ACIN_22_ "ACIN<22>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 7) (owner "Xilinx")) + ) + (port (rename ACIN_21_ "ACIN<21>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 8) (owner "Xilinx")) + ) + (port (rename ACIN_20_ "ACIN<20>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 9) (owner "Xilinx")) + ) + (port (rename ACIN_19_ "ACIN<19>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 10) (owner "Xilinx")) + ) + (port (rename ACIN_18_ "ACIN<18>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 11) (owner "Xilinx")) + ) + (port (rename ACIN_17_ "ACIN<17>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 12) (owner "Xilinx")) + ) + (port (rename ACIN_16_ "ACIN<16>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 13) (owner "Xilinx")) + ) + (port (rename ACIN_15_ "ACIN<15>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 14) (owner "Xilinx")) + ) + (port (rename ACIN_14_ "ACIN<14>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 15) (owner "Xilinx")) + ) + (port (rename ACIN_13_ "ACIN<13>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 16) (owner "Xilinx")) + ) + (port (rename ACIN_12_ "ACIN<12>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 17) (owner "Xilinx")) + ) + (port (rename ACIN_11_ "ACIN<11>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 18) (owner "Xilinx")) + ) + (port (rename ACIN_10_ "ACIN<10>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 19) (owner "Xilinx")) + ) + (port (rename ACIN_9_ "ACIN<9>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 20) (owner "Xilinx")) + ) + (port (rename ACIN_8_ "ACIN<8>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 21) (owner "Xilinx")) + ) + (port (rename ACIN_7_ "ACIN<7>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 22) (owner "Xilinx")) + ) + (port (rename ACIN_6_ "ACIN<6>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 23) (owner "Xilinx")) + ) + (port (rename ACIN_5_ "ACIN<5>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 24) (owner "Xilinx")) + ) + (port (rename ACIN_4_ "ACIN<4>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 25) (owner "Xilinx")) + ) + (port (rename ACIN_3_ "ACIN<3>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 26) (owner "Xilinx")) + ) + (port (rename ACIN_2_ "ACIN<2>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 27) (owner "Xilinx")) + ) + (port (rename ACIN_1_ "ACIN<1>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 28) (owner "Xilinx")) + ) + (port (rename ACIN_0_ "ACIN<0>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 29) (owner "Xilinx")) + ) + (port (rename CARRYINSEL_2_ "CARRYINSEL<2>") + (direction INPUT) + (property PIN_BUSNAME (string "CARRYINSEL<2:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename CARRYINSEL_1_ "CARRYINSEL<1>") + (direction INPUT) + (property PIN_BUSNAME (string "CARRYINSEL<2:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename CARRYINSEL_0_ "CARRYINSEL<0>") + (direction INPUT) + (property PIN_BUSNAME (string "CARRYINSEL<2:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + ) + ) + ) + (cell FDSE + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port S + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell FDE + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port CE 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(cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell MUXCY + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT) + ) + (port DI + (direction INPUT) + ) + (port S + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell MUXCY_L + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT) + ) + (port DI + (direction INPUT) + ) + (port S + (direction INPUT) + ) + (port LO + (direction OUTPUT) + ) + ) + ) + ) + (cell SRLC16E + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port A0 + (direction INPUT) + ) + (port A1 + (direction INPUT) + ) + (port A2 + (direction INPUT) + ) + (port A3 + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + (port CLK + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port Q + 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"Xilinx")) + (property PREG (integer 1) (owner "Xilinx")) + (property SEL_MASK (string "MASK") (owner "Xilinx")) + (property SEL_PATTERN (string "PATTERN") (owner "Xilinx")) + (property USE_DPORT (string "FALSE") (owner "Xilinx")) + (property USE_MULT (string "MULTIPLY") (owner "Xilinx")) + (property USE_PATTERN_DETECT (string "NO_PATDET") (owner "Xilinx")) + (property USE_SIMD (string "ONE48") (owner "Xilinx")) + ) + (instance blk00000016 + (viewRef view_1 (cellRef DSP48E1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "3:INPUT:CARRYINSEL<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:CARRYOUT<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:INPUT:ALUMODE<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "7:INPUT:OPMODE<6:0>") (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:INMODE<4:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:OUTPUT:ACOUT<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:BCOUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:PCOUT<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:PCIN<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:BCIN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:ACIN<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:C<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:B<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "25:INPUT:D<24:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:P<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:A<29:0>") (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property ACASCREG (integer 2) (owner "Xilinx")) + (property ADREG (integer 0) (owner "Xilinx")) + (property ALUMODEREG (integer 1) (owner "Xilinx")) + (property AREG (integer 2) (owner "Xilinx")) + (property AUTORESET_PATDET (string "NO_RESET") (owner "Xilinx")) + (property A_INPUT (string "DIRECT") (owner "Xilinx")) + (property BCASCREG (integer 2) (owner "Xilinx")) + (property BREG (integer 2) (owner "Xilinx")) + (property B_INPUT (string "DIRECT") (owner "Xilinx")) + (property CARRYINREG (integer 1) (owner "Xilinx")) + (property CARRYINSELREG (integer 1) (owner "Xilinx")) + (property CREG (integer 1) (owner "Xilinx")) + (property DREG (integer 0) (owner "Xilinx")) + (property INMODEREG (integer 0) (owner "Xilinx")) + (property MASK (string "FFFFFFFFFFFE") (owner "Xilinx")) + (property MREG (integer 1) (owner "Xilinx")) + (property OPMODEREG (integer 1) (owner "Xilinx")) + (property PATTERN (string "000000000000") (owner "Xilinx")) + (property PREG (integer 1) (owner "Xilinx")) + (property SEL_MASK (string "MASK") (owner "Xilinx")) + (property SEL_PATTERN (string "PATTERN") (owner "Xilinx")) + (property USE_DPORT (string "FALSE") (owner "Xilinx")) + (property USE_MULT (string "MULTIPLY") (owner "Xilinx")) + (property USE_PATTERN_DETECT (string "NO_PATDET") (owner "Xilinx")) + (property USE_SIMD (string "ONE48") (owner "Xilinx")) + ) + (instance blk00000017 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk00000018 + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance blk00000019 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000001a + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000001b + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000001c + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000001d + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000001e + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000001f + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000020 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000021 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000022 + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance blk00000023 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance blk00000024 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000025 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance blk00000026 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000027 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000028 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000029 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000002a + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000002b + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance blk0000002c + (viewRef view_1 (cellRef dpr_ram_1_blk0000002c (libraryRef hbdec1_lib))) + (property BUS_INFO (string "3:INPUT:ADDRA<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:DA_IN<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "3:INPUT:ADDRB<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:DA_OUT<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:DB_OUT<47:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 2) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "dpr_ram_1_blk0000002c") (owner "Xilinx")) + ) + (instance blk0000008f + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance blk00000090 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000091 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk00000092 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk00000093 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk00000094 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk00000095 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk00000096 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk00000097 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk00000098 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk00000099 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk0000009a + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk0000009b + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk0000009c + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000009d + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000009e + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000009f + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000a0 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000a1 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000a2 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000a3 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000a4 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000a5 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000a6 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000a7 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000a8 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000a9 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000aa + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000ab + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000ac + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000ad + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000ae + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000af + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000b0 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000b1 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000b2 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000b3 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000b4 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000b5 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000b6 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000b7 + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000b8 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000b9 + (viewRef view_1 (cellRef MUXCY_L (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000ba + (viewRef view_1 (cellRef MUXCY_L (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000bb + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000bc + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000bd + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000be + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000bf + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance blk000000c0 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000c1 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000c2 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000c3 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000c4 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000c5 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000c6 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000c7 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000c8 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000c9 + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance blk000000ca + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000cb + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000cc + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000cd + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000ce + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000cf + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000d0 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000d1 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000d2 + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance blk000000d3 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000d4 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000d5 + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000d6 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000d7 + (viewRef view_1 (cellRef MUXCY_L (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000d8 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000d9 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000da + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000db + (viewRef view_1 (cellRef MUXCY_L (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000dc + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000dd + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000de + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000df + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000e0 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000e1 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance blk000000e2 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000e3 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000e4 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000e5 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000e6 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000e7 + (viewRef view_1 (cellRef DSP48E1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "3:INPUT:CARRYINSEL<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:CARRYOUT<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:INPUT:ALUMODE<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "7:INPUT:OPMODE<6:0>") (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:INMODE<4:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:OUTPUT:ACOUT<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:BCOUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:PCOUT<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:PCIN<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:BCIN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:ACIN<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:C<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:B<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "25:INPUT:D<24:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:P<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:A<29:0>") (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property ACASCREG (integer 1) (owner "Xilinx")) + (property ADREG (integer 1) (owner "Xilinx")) + (property ALUMODEREG (integer 0) (owner "Xilinx")) + (property AREG (integer 1) (owner "Xilinx")) + (property AUTORESET_PATDET (string "NO_RESET") (owner "Xilinx")) + (property A_INPUT (string "DIRECT") (owner "Xilinx")) + (property BCASCREG (integer 1) (owner "Xilinx")) + (property BREG (integer 1) (owner "Xilinx")) + (property B_INPUT (string "DIRECT") (owner "Xilinx")) + (property CARRYINREG (integer 1) (owner "Xilinx")) + (property CARRYINSELREG (integer 1) (owner "Xilinx")) + (property CREG (integer 1) (owner "Xilinx")) + (property DREG (integer 1) (owner "Xilinx")) + (property INMODEREG (integer 1) (owner "Xilinx")) + (property MASK (string "FFFFFFFFFFFE") (owner "Xilinx")) + (property MREG (integer 1) (owner "Xilinx")) + (property OPMODEREG (integer 0) (owner "Xilinx")) + (property PATTERN (string "000000000000") (owner "Xilinx")) + (property PREG (integer 1) (owner "Xilinx")) + (property SEL_MASK (string "MASK") (owner "Xilinx")) + (property SEL_PATTERN (string "PATTERN") (owner "Xilinx")) + (property USE_DPORT (string "TRUE") (owner "Xilinx")) + (property USE_MULT (string "MULTIPLY") (owner "Xilinx")) + (property USE_PATTERN_DETECT (string "NO_PATDET") (owner "Xilinx")) + (property USE_SIMD (string "ONE48") (owner "Xilinx")) + ) + (instance blk000000e8 + (viewRef view_1 (cellRef DSP48E1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "3:INPUT:CARRYINSEL<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:CARRYOUT<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:INPUT:ALUMODE<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "7:INPUT:OPMODE<6:0>") (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:INMODE<4:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:OUTPUT:ACOUT<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:BCOUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:PCOUT<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:PCIN<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:BCIN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:ACIN<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:C<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:B<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "25:INPUT:D<24:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:P<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:A<29:0>") (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property ACASCREG (integer 1) (owner "Xilinx")) + (property ADREG (integer 1) (owner "Xilinx")) + (property ALUMODEREG (integer 0) (owner "Xilinx")) + (property AREG (integer 1) (owner "Xilinx")) + (property AUTORESET_PATDET (string "NO_RESET") (owner "Xilinx")) + (property A_INPUT (string "DIRECT") (owner "Xilinx")) + (property BCASCREG (integer 1) (owner "Xilinx")) + (property BREG (integer 1) (owner "Xilinx")) + (property B_INPUT (string "DIRECT") (owner "Xilinx")) + (property CARRYINREG (integer 1) (owner "Xilinx")) + (property CARRYINSELREG (integer 1) (owner "Xilinx")) + (property CREG (integer 1) (owner "Xilinx")) + (property DREG (integer 1) (owner "Xilinx")) + (property INMODEREG (integer 1) (owner "Xilinx")) + (property MASK (string "FFFFFFFFFFFE") (owner "Xilinx")) + (property MREG (integer 1) (owner "Xilinx")) + (property OPMODEREG (integer 0) (owner "Xilinx")) + (property PATTERN (string "000000000000") (owner "Xilinx")) + (property PREG (integer 1) (owner "Xilinx")) + (property SEL_MASK (string "MASK") (owner "Xilinx")) + (property SEL_PATTERN (string "PATTERN") (owner "Xilinx")) + (property USE_DPORT (string "TRUE") (owner "Xilinx")) + (property USE_MULT (string "MULTIPLY") (owner "Xilinx")) + (property USE_PATTERN_DETECT (string "NO_PATDET") (owner "Xilinx")) + (property USE_SIMD (string "ONE48") (owner "Xilinx")) + ) + (instance blk000000e9 + (viewRef view_1 (cellRef DSP48E1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "3:INPUT:CARRYINSEL<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:CARRYOUT<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:INPUT:ALUMODE<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "7:INPUT:OPMODE<6:0>") (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:INMODE<4:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:OUTPUT:ACOUT<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:BCOUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:PCOUT<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:PCIN<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:BCIN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:ACIN<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:C<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:B<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "25:INPUT:D<24:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:P<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:A<29:0>") (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property ACASCREG (integer 1) (owner "Xilinx")) + (property ADREG (integer 1) (owner "Xilinx")) + (property ALUMODEREG (integer 0) (owner "Xilinx")) + (property AREG (integer 1) (owner "Xilinx")) + (property AUTORESET_PATDET (string "NO_RESET") (owner "Xilinx")) + (property A_INPUT (string "DIRECT") (owner "Xilinx")) + (property BCASCREG (integer 1) (owner "Xilinx")) + (property BREG (integer 1) (owner "Xilinx")) + (property B_INPUT (string "DIRECT") (owner "Xilinx")) + (property CARRYINREG (integer 1) (owner "Xilinx")) + (property CARRYINSELREG (integer 1) (owner "Xilinx")) + (property CREG (integer 1) (owner "Xilinx")) + (property DREG (integer 1) (owner "Xilinx")) + (property INMODEREG (integer 1) (owner "Xilinx")) + (property MASK (string "FFFFFFFFFFFE") (owner "Xilinx")) + (property MREG (integer 1) (owner "Xilinx")) + (property OPMODEREG (integer 0) (owner "Xilinx")) + (property PATTERN (string "000000000000") (owner "Xilinx")) + (property PREG (integer 1) (owner "Xilinx")) + (property SEL_MASK (string "MASK") (owner "Xilinx")) + (property SEL_PATTERN (string "PATTERN") (owner "Xilinx")) + (property USE_DPORT (string "TRUE") (owner "Xilinx")) + (property USE_MULT (string "MULTIPLY") (owner "Xilinx")) + (property USE_PATTERN_DETECT (string "NO_PATDET") (owner "Xilinx")) + (property USE_SIMD (string "ONE48") (owner "Xilinx")) + ) + (instance blk000000ea + (viewRef view_1 (cellRef DSP48E1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "3:INPUT:CARRYINSEL<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:CARRYOUT<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:INPUT:ALUMODE<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "7:INPUT:OPMODE<6:0>") (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:INMODE<4:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:OUTPUT:ACOUT<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:BCOUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:PCOUT<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:PCIN<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:BCIN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:ACIN<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:C<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:B<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "25:INPUT:D<24:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:P<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:A<29:0>") (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property ACASCREG (integer 1) (owner "Xilinx")) + (property ADREG (integer 1) (owner "Xilinx")) + (property ALUMODEREG (integer 0) (owner "Xilinx")) + (property AREG (integer 1) (owner "Xilinx")) + (property AUTORESET_PATDET (string "NO_RESET") (owner "Xilinx")) + (property A_INPUT (string "DIRECT") (owner "Xilinx")) + (property BCASCREG (integer 1) (owner "Xilinx")) + (property BREG (integer 1) (owner "Xilinx")) + (property B_INPUT (string "DIRECT") (owner "Xilinx")) + (property CARRYINREG (integer 1) (owner "Xilinx")) + (property CARRYINSELREG (integer 1) (owner "Xilinx")) + (property CREG (integer 1) (owner "Xilinx")) + (property DREG (integer 1) (owner "Xilinx")) + (property INMODEREG (integer 1) (owner "Xilinx")) + (property MASK (string "FFFFFFFFFFFE") (owner "Xilinx")) + (property MREG (integer 1) (owner "Xilinx")) + (property OPMODEREG (integer 0) (owner "Xilinx")) + (property PATTERN (string "000000000000") (owner "Xilinx")) + (property PREG (integer 1) (owner "Xilinx")) + (property SEL_MASK (string "MASK") (owner "Xilinx")) + (property SEL_PATTERN (string "PATTERN") (owner "Xilinx")) + (property USE_DPORT (string "TRUE") (owner "Xilinx")) + (property USE_MULT (string "MULTIPLY") (owner "Xilinx")) + (property USE_PATTERN_DETECT (string "NO_PATDET") (owner "Xilinx")) + (property USE_SIMD (string "ONE48") (owner "Xilinx")) + ) + (instance blk000000eb + (viewRef view_1 (cellRef DSP48E1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "3:INPUT:CARRYINSEL<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:CARRYOUT<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:INPUT:ALUMODE<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "7:INPUT:OPMODE<6:0>") (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:INMODE<4:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:OUTPUT:ACOUT<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:BCOUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:PCOUT<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:PCIN<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:BCIN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:ACIN<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:C<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:B<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "25:INPUT:D<24:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:P<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:A<29:0>") (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property ACASCREG (integer 1) (owner "Xilinx")) + (property ADREG (integer 1) (owner "Xilinx")) + (property ALUMODEREG (integer 0) (owner "Xilinx")) + (property AREG (integer 1) (owner "Xilinx")) + (property AUTORESET_PATDET (string "NO_RESET") (owner "Xilinx")) + (property A_INPUT (string "DIRECT") (owner "Xilinx")) + (property BCASCREG (integer 1) (owner "Xilinx")) + (property BREG (integer 1) (owner "Xilinx")) + (property B_INPUT (string "DIRECT") (owner "Xilinx")) + (property CARRYINREG (integer 1) (owner "Xilinx")) + (property CARRYINSELREG (integer 1) (owner "Xilinx")) + (property CREG (integer 1) (owner "Xilinx")) + (property DREG (integer 1) (owner "Xilinx")) + (property INMODEREG (integer 1) (owner "Xilinx")) + (property MASK (string "FFFFFFFFFFFE") (owner "Xilinx")) + (property MREG (integer 1) (owner "Xilinx")) + (property OPMODEREG (integer 0) (owner "Xilinx")) + (property PATTERN (string "000000000000") (owner "Xilinx")) + (property PREG (integer 1) (owner "Xilinx")) + (property SEL_MASK (string "MASK") (owner "Xilinx")) + (property SEL_PATTERN (string "PATTERN") (owner "Xilinx")) + (property USE_DPORT (string "TRUE") (owner "Xilinx")) + (property USE_MULT (string "MULTIPLY") (owner "Xilinx")) + (property USE_PATTERN_DETECT (string "NO_PATDET") (owner "Xilinx")) + (property USE_SIMD (string "ONE48") (owner "Xilinx")) + ) + (instance blk000000ec + (viewRef view_1 (cellRef DSP48E1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "3:INPUT:CARRYINSEL<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:CARRYOUT<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:INPUT:ALUMODE<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "7:INPUT:OPMODE<6:0>") (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:INMODE<4:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:OUTPUT:ACOUT<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:BCOUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:PCOUT<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:PCIN<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:BCIN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:ACIN<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:C<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:B<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "25:INPUT:D<24:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:P<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:A<29:0>") (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property ACASCREG (integer 1) (owner "Xilinx")) + (property ADREG (integer 1) (owner "Xilinx")) + (property ALUMODEREG (integer 0) (owner "Xilinx")) + (property AREG (integer 1) (owner "Xilinx")) + (property AUTORESET_PATDET (string "NO_RESET") (owner "Xilinx")) + (property A_INPUT (string "DIRECT") (owner "Xilinx")) + (property BCASCREG (integer 1) (owner "Xilinx")) + (property BREG (integer 1) (owner "Xilinx")) + (property B_INPUT (string "DIRECT") (owner "Xilinx")) + (property CARRYINREG (integer 1) (owner "Xilinx")) + (property CARRYINSELREG (integer 1) (owner "Xilinx")) + (property CREG (integer 1) (owner "Xilinx")) + (property DREG (integer 1) (owner "Xilinx")) + (property INMODEREG (integer 1) (owner "Xilinx")) + (property MASK (string "FFFFFFFFFFFE") (owner "Xilinx")) + (property MREG (integer 1) (owner "Xilinx")) + (property OPMODEREG (integer 0) (owner "Xilinx")) + (property PATTERN (string "000000000000") (owner "Xilinx")) + (property PREG (integer 1) (owner "Xilinx")) + (property SEL_MASK (string "MASK") (owner "Xilinx")) + (property SEL_PATTERN (string "PATTERN") (owner "Xilinx")) + (property USE_DPORT (string "TRUE") (owner "Xilinx")) + (property USE_MULT (string "MULTIPLY") (owner "Xilinx")) + (property USE_PATTERN_DETECT (string "NO_PATDET") (owner "Xilinx")) + (property USE_SIMD (string "ONE48") (owner "Xilinx")) + ) + (instance blk000000ed + (viewRef view_1 (cellRef DSP48E1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "3:INPUT:CARRYINSEL<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:CARRYOUT<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:INPUT:ALUMODE<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "7:INPUT:OPMODE<6:0>") (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:INMODE<4:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:OUTPUT:ACOUT<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:BCOUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:PCOUT<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:PCIN<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:BCIN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:ACIN<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:C<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:B<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "25:INPUT:D<24:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:P<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:A<29:0>") (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property ACASCREG (integer 1) (owner "Xilinx")) + (property ADREG (integer 1) (owner "Xilinx")) + (property ALUMODEREG (integer 0) (owner "Xilinx")) + (property AREG (integer 1) (owner "Xilinx")) + (property AUTORESET_PATDET (string "NO_RESET") (owner "Xilinx")) + (property A_INPUT (string "DIRECT") (owner "Xilinx")) + (property BCASCREG (integer 1) (owner "Xilinx")) + (property BREG (integer 1) (owner "Xilinx")) + (property B_INPUT (string "DIRECT") (owner "Xilinx")) + (property CARRYINREG (integer 1) (owner "Xilinx")) + (property CARRYINSELREG (integer 1) (owner "Xilinx")) + (property CREG (integer 1) (owner "Xilinx")) + (property DREG (integer 1) (owner "Xilinx")) + (property INMODEREG (integer 1) (owner "Xilinx")) + (property MASK (string "FFFFFFFFFFFE") (owner "Xilinx")) + (property MREG (integer 1) (owner "Xilinx")) + (property OPMODEREG (integer 0) (owner "Xilinx")) + (property PATTERN (string "000000000000") (owner "Xilinx")) + (property PREG (integer 1) (owner "Xilinx")) + (property SEL_MASK (string "MASK") (owner "Xilinx")) + (property SEL_PATTERN (string "PATTERN") (owner "Xilinx")) + (property USE_DPORT (string "TRUE") (owner "Xilinx")) + (property USE_MULT (string "MULTIPLY") (owner "Xilinx")) + (property USE_PATTERN_DETECT (string "NO_PATDET") (owner "Xilinx")) + (property USE_SIMD (string "ONE48") (owner "Xilinx")) + ) + (instance blk000000ee + (viewRef view_1 (cellRef DSP48E1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "3:INPUT:CARRYINSEL<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:CARRYOUT<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:INPUT:ALUMODE<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "7:INPUT:OPMODE<6:0>") (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:INMODE<4:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:OUTPUT:ACOUT<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:BCOUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:PCOUT<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:PCIN<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:BCIN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:ACIN<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:C<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:B<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "25:INPUT:D<24:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:P<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:A<29:0>") (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property ACASCREG (integer 1) (owner "Xilinx")) + (property ADREG (integer 1) (owner "Xilinx")) + (property ALUMODEREG (integer 0) (owner "Xilinx")) + (property AREG (integer 1) (owner "Xilinx")) + (property AUTORESET_PATDET (string "NO_RESET") (owner "Xilinx")) + (property A_INPUT (string "DIRECT") (owner "Xilinx")) + (property BCASCREG (integer 1) (owner "Xilinx")) + (property BREG (integer 1) (owner "Xilinx")) + (property B_INPUT (string "DIRECT") (owner "Xilinx")) + (property CARRYINREG (integer 1) (owner "Xilinx")) + (property CARRYINSELREG (integer 1) (owner "Xilinx")) + (property CREG (integer 1) (owner "Xilinx")) + (property DREG (integer 1) (owner "Xilinx")) + (property INMODEREG (integer 1) (owner "Xilinx")) + (property MASK (string "FFFFFFFFFFFE") (owner "Xilinx")) + (property MREG (integer 1) (owner "Xilinx")) + (property OPMODEREG (integer 0) (owner "Xilinx")) + (property PATTERN (string "000000000000") (owner "Xilinx")) + (property PREG (integer 1) (owner "Xilinx")) + (property SEL_MASK (string "MASK") (owner "Xilinx")) + (property SEL_PATTERN (string "PATTERN") (owner "Xilinx")) + (property USE_DPORT (string "TRUE") (owner "Xilinx")) + (property USE_MULT (string "MULTIPLY") (owner "Xilinx")) + (property USE_PATTERN_DETECT (string "NO_PATDET") (owner "Xilinx")) + (property USE_SIMD (string "ONE48") (owner "Xilinx")) + ) + (instance blk000000ef + (viewRef view_1 (cellRef DSP48E1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "3:INPUT:CARRYINSEL<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:CARRYOUT<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:INPUT:ALUMODE<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "7:INPUT:OPMODE<6:0>") (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:INMODE<4:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:OUTPUT:ACOUT<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:BCOUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:PCOUT<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:PCIN<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:BCIN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:ACIN<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:C<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:B<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "25:INPUT:D<24:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:P<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:A<29:0>") (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property ACASCREG (integer 1) (owner "Xilinx")) + (property ADREG (integer 1) (owner "Xilinx")) + (property ALUMODEREG (integer 0) (owner "Xilinx")) + (property AREG (integer 1) (owner "Xilinx")) + (property AUTORESET_PATDET (string "NO_RESET") (owner "Xilinx")) + (property A_INPUT (string "DIRECT") (owner "Xilinx")) + (property BCASCREG (integer 1) (owner "Xilinx")) + (property BREG (integer 1) (owner "Xilinx")) + (property B_INPUT (string "DIRECT") (owner "Xilinx")) + (property CARRYINREG (integer 1) (owner "Xilinx")) + (property CARRYINSELREG (integer 1) (owner "Xilinx")) + (property CREG (integer 1) (owner "Xilinx")) + (property DREG (integer 1) (owner "Xilinx")) + (property INMODEREG (integer 1) (owner "Xilinx")) + (property MASK (string "FFFFFFFFFFFE") (owner "Xilinx")) + (property MREG (integer 1) (owner "Xilinx")) + (property OPMODEREG (integer 0) (owner "Xilinx")) + (property PATTERN (string "000000000000") (owner "Xilinx")) + (property PREG (integer 1) (owner "Xilinx")) + (property SEL_MASK (string "MASK") (owner "Xilinx")) + (property SEL_PATTERN (string "PATTERN") (owner "Xilinx")) + (property USE_DPORT (string "TRUE") (owner "Xilinx")) + (property USE_MULT (string "MULTIPLY") (owner "Xilinx")) + (property USE_PATTERN_DETECT (string "NO_PATDET") (owner "Xilinx")) + (property USE_SIMD (string "ONE48") (owner "Xilinx")) + ) + (instance blk000000f0 + (viewRef view_1 (cellRef DSP48E1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "3:INPUT:CARRYINSEL<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:CARRYOUT<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:INPUT:ALUMODE<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "7:INPUT:OPMODE<6:0>") (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:INMODE<4:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:OUTPUT:ACOUT<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:BCOUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:PCOUT<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:PCIN<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:BCIN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:ACIN<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:C<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:B<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "25:INPUT:D<24:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:P<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:A<29:0>") (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property ACASCREG (integer 1) (owner "Xilinx")) + (property ADREG (integer 1) (owner "Xilinx")) + (property ALUMODEREG (integer 0) (owner "Xilinx")) + (property AREG (integer 1) (owner "Xilinx")) + (property AUTORESET_PATDET (string "NO_RESET") (owner "Xilinx")) + (property A_INPUT (string "DIRECT") (owner "Xilinx")) + (property BCASCREG (integer 1) (owner "Xilinx")) + (property BREG (integer 1) (owner "Xilinx")) + (property B_INPUT (string "DIRECT") (owner "Xilinx")) + (property CARRYINREG (integer 1) (owner "Xilinx")) + (property CARRYINSELREG (integer 1) (owner "Xilinx")) + (property CREG (integer 1) (owner "Xilinx")) + (property DREG (integer 1) (owner "Xilinx")) + (property INMODEREG (integer 1) (owner "Xilinx")) + (property MASK (string "FFFFFFFFFFFE") (owner "Xilinx")) + (property MREG (integer 1) (owner "Xilinx")) + (property OPMODEREG (integer 0) (owner "Xilinx")) + (property PATTERN (string "000000000000") (owner "Xilinx")) + (property PREG (integer 1) (owner "Xilinx")) + (property SEL_MASK (string "MASK") (owner "Xilinx")) + (property SEL_PATTERN (string "PATTERN") (owner "Xilinx")) + (property USE_DPORT (string "TRUE") (owner "Xilinx")) + (property USE_MULT (string "MULTIPLY") (owner "Xilinx")) + (property USE_PATTERN_DETECT (string "NO_PATDET") (owner "Xilinx")) + (property USE_SIMD (string "ONE48") (owner "Xilinx")) + ) + (instance blk000000f1 + (viewRef view_1 (cellRef DSP48E1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "3:INPUT:CARRYINSEL<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:CARRYOUT<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:INPUT:ALUMODE<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "7:INPUT:OPMODE<6:0>") (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:INMODE<4:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:OUTPUT:ACOUT<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:BCOUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:PCOUT<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:PCIN<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:BCIN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:ACIN<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:C<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:B<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "25:INPUT:D<24:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:P<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:A<29:0>") (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property ACASCREG (integer 1) (owner "Xilinx")) + (property ADREG (integer 1) (owner "Xilinx")) + (property ALUMODEREG (integer 0) (owner "Xilinx")) + (property AREG (integer 1) (owner "Xilinx")) + (property AUTORESET_PATDET (string "NO_RESET") (owner "Xilinx")) + (property A_INPUT (string "DIRECT") (owner "Xilinx")) + (property BCASCREG (integer 1) (owner "Xilinx")) + (property BREG (integer 1) (owner "Xilinx")) + (property B_INPUT (string "DIRECT") (owner "Xilinx")) + (property CARRYINREG (integer 1) (owner "Xilinx")) + (property CARRYINSELREG (integer 1) (owner "Xilinx")) + (property CREG (integer 1) (owner "Xilinx")) + (property DREG (integer 1) (owner "Xilinx")) + (property INMODEREG (integer 1) (owner "Xilinx")) + (property MASK (string "FFFFFFFFFFFE") (owner "Xilinx")) + (property MREG (integer 1) (owner "Xilinx")) + (property OPMODEREG (integer 0) (owner "Xilinx")) + (property PATTERN (string "000000000000") (owner "Xilinx")) + (property PREG (integer 1) (owner "Xilinx")) + (property SEL_MASK (string "MASK") (owner "Xilinx")) + (property SEL_PATTERN (string "PATTERN") (owner "Xilinx")) + (property USE_DPORT (string "TRUE") (owner "Xilinx")) + (property USE_MULT (string "MULTIPLY") (owner "Xilinx")) + (property USE_PATTERN_DETECT (string "NO_PATDET") (owner "Xilinx")) + (property USE_SIMD (string "ONE48") (owner "Xilinx")) + ) + (instance blk000000f2 + (viewRef view_1 (cellRef DSP48E1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "3:INPUT:CARRYINSEL<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:CARRYOUT<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:INPUT:ALUMODE<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "7:INPUT:OPMODE<6:0>") (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:INMODE<4:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:OUTPUT:ACOUT<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:BCOUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:PCOUT<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:PCIN<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:BCIN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:ACIN<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:C<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:B<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "25:INPUT:D<24:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:P<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:A<29:0>") (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property ACASCREG (integer 1) (owner "Xilinx")) + (property ADREG (integer 1) (owner "Xilinx")) + (property ALUMODEREG (integer 0) (owner "Xilinx")) + (property AREG (integer 1) (owner "Xilinx")) + (property AUTORESET_PATDET (string "NO_RESET") (owner "Xilinx")) + (property A_INPUT (string "DIRECT") (owner "Xilinx")) + (property BCASCREG (integer 1) (owner "Xilinx")) + (property BREG (integer 1) (owner "Xilinx")) + (property B_INPUT (string "DIRECT") (owner "Xilinx")) + (property CARRYINREG (integer 1) (owner "Xilinx")) + (property CARRYINSELREG (integer 1) (owner "Xilinx")) + (property CREG (integer 1) (owner "Xilinx")) + (property DREG (integer 1) (owner "Xilinx")) + (property INMODEREG (integer 1) (owner "Xilinx")) + (property MASK (string "FFFFFFFFFFFE") (owner "Xilinx")) + (property MREG (integer 1) (owner "Xilinx")) + (property OPMODEREG (integer 0) (owner "Xilinx")) + (property PATTERN (string "000000000000") (owner "Xilinx")) + (property PREG (integer 1) (owner "Xilinx")) + (property SEL_MASK (string "MASK") (owner "Xilinx")) + (property SEL_PATTERN (string "PATTERN") (owner "Xilinx")) + (property USE_DPORT (string "TRUE") (owner "Xilinx")) + (property USE_MULT (string "MULTIPLY") (owner "Xilinx")) + (property USE_PATTERN_DETECT (string "NO_PATDET") (owner "Xilinx")) + (property USE_SIMD (string "ONE48") (owner "Xilinx")) + ) + (instance blk000000f3 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000f4 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000f5 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000f6 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000f7 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000f8 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000f9 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000fa + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000fb + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000fc + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000fd + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000fe + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000ff + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000100 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000101 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000102 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000103 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000104 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000105 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000106 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000107 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000108 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000109 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000010a + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000010b + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000010c + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000010d + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000010e + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000010f + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000110 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000111 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000112 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000113 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000114 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000115 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000116 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000117 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000118 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000119 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000011a + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000011b + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000011c + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000011d + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000011e + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000011f + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000120 + (viewRef view_1 (cellRef sp_ram_blk00000120 (libraryRef hbdec1_lib))) + (property BUS_INFO (string "1:INPUT:ADDR<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 3) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_blk00000120") (owner "Xilinx")) + ) + (instance blk00000153 + (viewRef view_1 (cellRef sp_ram_NO1_blk00000153 (libraryRef hbdec1_lib))) + (property BUS_INFO (string "1:INPUT:ADDR<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 1) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 4) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO1_blk00000153") (owner "Xilinx")) + ) + (instance blk00000186 + (viewRef view_1 (cellRef sp_ram_NO2_blk00000186 (libraryRef hbdec1_lib))) + (property BUS_INFO (string "1:INPUT:ADDR<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 2) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 5) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO2_blk00000186") (owner "Xilinx")) + ) + (instance blk000001b9 + (viewRef view_1 (cellRef sp_ram_NO3_blk000001b9 (libraryRef hbdec1_lib))) + (property BUS_INFO (string "1:INPUT:ADDR<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 3) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 6) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO3_blk000001b9") (owner "Xilinx")) + ) + (instance blk000001ec + (viewRef view_1 (cellRef sp_ram_NO4_blk000001ec (libraryRef hbdec1_lib))) + (property BUS_INFO (string "1:INPUT:ADDR<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 4) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 7) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO4_blk000001ec") (owner "Xilinx")) + ) + (instance blk0000021f + (viewRef view_1 (cellRef sp_ram_NO5_blk0000021f (libraryRef hbdec1_lib))) + (property BUS_INFO (string "1:INPUT:ADDR<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 5) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 8) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO5_blk0000021f") (owner "Xilinx")) + ) + (instance blk00000252 + (viewRef view_1 (cellRef sp_ram_NO6_blk00000252 (libraryRef hbdec1_lib))) + (property BUS_INFO (string "1:INPUT:ADDR<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 6) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 9) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO6_blk00000252") (owner "Xilinx")) + ) + (instance blk00000285 + (viewRef view_1 (cellRef sp_ram_NO7_blk00000285 (libraryRef hbdec1_lib))) + (property BUS_INFO (string "1:INPUT:ADDR<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 7) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 10) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO7_blk00000285") (owner "Xilinx")) + ) + (instance blk000002b8 + (viewRef view_1 (cellRef sp_ram_NO8_blk000002b8 (libraryRef hbdec1_lib))) + (property BUS_INFO (string "1:INPUT:ADDR<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 8) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 11) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO8_blk000002b8") (owner "Xilinx")) + ) + (instance blk000002eb + (viewRef view_1 (cellRef sp_ram_NO9_blk000002eb (libraryRef hbdec1_lib))) + (property BUS_INFO (string "1:INPUT:ADDR<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 9) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 12) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO9_blk000002eb") (owner "Xilinx")) + ) + (instance blk0000031e + (viewRef view_1 (cellRef sp_ram_NO10_blk0000031e (libraryRef hbdec1_lib))) + (property BUS_INFO (string "1:INPUT:ADDR<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 10) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 13) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO10_blk0000031e") (owner "Xilinx")) + ) + (instance blk00000351 + (viewRef view_1 (cellRef sp_ram_NO11_blk00000351 (libraryRef hbdec1_lib))) + (property BUS_INFO (string "1:INPUT:ADDR<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 11) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 14) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO11_blk00000351") (owner "Xilinx")) + ) + (instance blk00000384 + (viewRef view_1 (cellRef sp_ram_NO12_blk00000384 (libraryRef hbdec1_lib))) + (property BUS_INFO (string "1:INPUT:ADDR<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 12) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 15) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO12_blk00000384") (owner "Xilinx")) + ) + (instance blk000003b7 + (viewRef view_1 (cellRef sp_ram_NO13_blk000003b7 (libraryRef hbdec1_lib))) + (property BUS_INFO (string "1:INPUT:ADDR<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 13) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 16) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO13_blk000003b7") (owner "Xilinx")) + ) + (instance blk000003ea + (viewRef view_1 (cellRef sp_ram_NO14_blk000003ea (libraryRef hbdec1_lib))) + (property BUS_INFO (string "1:INPUT:ADDR<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 14) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 17) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO14_blk000003ea") (owner "Xilinx")) + ) + (instance blk0000041d + (viewRef view_1 (cellRef sp_ram_NO15_blk0000041d (libraryRef hbdec1_lib))) + (property BUS_INFO (string "1:INPUT:ADDR<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 15) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 18) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO15_blk0000041d") (owner "Xilinx")) + ) + (instance blk00000450 + (viewRef view_1 (cellRef sp_ram_NO16_blk00000450 (libraryRef hbdec1_lib))) + (property BUS_INFO (string "1:INPUT:ADDR<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 16) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 19) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO16_blk00000450") (owner "Xilinx")) + ) + (instance blk00000483 + (viewRef view_1 (cellRef sp_ram_NO17_blk00000483 (libraryRef hbdec1_lib))) + (property BUS_INFO (string "1:INPUT:ADDR<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 17) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 20) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO17_blk00000483") (owner "Xilinx")) + ) + (instance blk000004b6 + (viewRef view_1 (cellRef sp_ram_NO18_blk000004b6 (libraryRef hbdec1_lib))) + (property BUS_INFO (string "1:INPUT:ADDR<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 18) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 21) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO18_blk000004b6") (owner "Xilinx")) + ) + (instance blk000004e9 + (viewRef view_1 (cellRef sp_ram_NO19_blk000004e9 (libraryRef hbdec1_lib))) + (property BUS_INFO (string "1:INPUT:ADDR<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 19) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 22) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO19_blk000004e9") (owner "Xilinx")) + ) + (instance blk0000051c + (viewRef view_1 (cellRef sp_ram_NO20_blk0000051c (libraryRef hbdec1_lib))) + (property BUS_INFO (string "1:INPUT:ADDR<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 20) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 23) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO20_blk0000051c") (owner "Xilinx")) + ) + (instance blk0000054f + (viewRef view_1 (cellRef sp_ram_NO21_blk0000054f (libraryRef hbdec1_lib))) + (property BUS_INFO (string "1:INPUT:ADDR<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 21) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 24) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO21_blk0000054f") (owner "Xilinx")) + ) + (instance blk00000582 + (viewRef view_1 (cellRef sp_ram_NO22_blk00000582 (libraryRef hbdec1_lib))) + (property BUS_INFO (string "1:INPUT:ADDR<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 22) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 25) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO22_blk00000582") (owner "Xilinx")) + ) + (instance blk000005b5 + (viewRef view_1 (cellRef sp_ram_NO23_blk000005b5 (libraryRef hbdec1_lib))) + (property BUS_INFO (string "1:INPUT:ADDR<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 23) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 26) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO23_blk000005b5") (owner "Xilinx")) + ) + (instance blk000005e8 + (viewRef view_1 (cellRef dpr_ram_2_blk000005e8 (libraryRef hbdec1_lib))) + (property BUS_INFO (string "2:INPUT:ADDRA<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:DA_IN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "2:INPUT:ADDRB<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:DA_OUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:DB_OUT<17:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 27) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "dpr_ram_2_blk000005e8") (owner "Xilinx")) + ) + (instance blk00000621 + (viewRef view_1 (cellRef dpr_ram_3_blk00000621 (libraryRef hbdec1_lib))) + (property BUS_INFO (string "2:INPUT:ADDRA<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:DA_IN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "2:INPUT:ADDRB<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:DA_OUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:DB_OUT<17:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 28) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "dpr_ram_3_blk00000621") (owner "Xilinx")) + ) + (instance blk0000065a + (viewRef view_1 (cellRef dpr_ram_4_blk0000065a (libraryRef hbdec1_lib))) + (property BUS_INFO (string "2:INPUT:ADDRA<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:DA_IN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "2:INPUT:ADDRB<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:DA_OUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:DB_OUT<17:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 29) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "dpr_ram_4_blk0000065a") (owner "Xilinx")) + ) + (instance blk00000693 + (viewRef view_1 (cellRef dpr_ram_5_blk00000693 (libraryRef hbdec1_lib))) + (property BUS_INFO (string "2:INPUT:ADDRA<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:DA_IN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "2:INPUT:ADDRB<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:DA_OUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:DB_OUT<17:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 30) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "dpr_ram_5_blk00000693") (owner "Xilinx")) + ) + (instance blk000006cc + (viewRef view_1 (cellRef dpr_ram_6_blk000006cc (libraryRef hbdec1_lib))) + (property BUS_INFO (string "2:INPUT:ADDRA<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:DA_IN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "2:INPUT:ADDRB<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:DA_OUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:DB_OUT<17:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 31) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "dpr_ram_6_blk000006cc") (owner "Xilinx")) + ) + (instance blk00000705 + (viewRef view_1 (cellRef dpr_ram_7_blk00000705 (libraryRef hbdec1_lib))) + (property BUS_INFO (string "2:INPUT:ADDRA<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:DA_IN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "2:INPUT:ADDRB<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:DA_OUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:DB_OUT<17:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 32) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "dpr_ram_7_blk00000705") (owner "Xilinx")) + ) + (instance blk0000072c + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000072d + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000072e + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000072f + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000730 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000731 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000732 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000733 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000734 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000735 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000736 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000737 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000738 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000739 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000073a + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000073b + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000073c + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000073d + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000073e + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000073f + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000740 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000741 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000742 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000743 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000744 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000745 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000746 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000747 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000748 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000749 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000074a + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000074b + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000074c + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000074d + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000074e + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000074f + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000750 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000751 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000752 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000753 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000754 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000755 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000756 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000757 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000758 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000759 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000075a + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000075b + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000075c + (viewRef view_1 (cellRef dpr_ram_8_blk0000075c (libraryRef hbdec1_lib))) + (property BUS_INFO (string "1:INPUT:ADDRA<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:DA_IN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "1:INPUT:ADDRB<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:DA_OUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:DB_OUT<17:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 33) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "dpr_ram_8_blk0000075c") (owner "Xilinx")) + ) + (instance blk00000783 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk00000784 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk00000785 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk00000786 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk00000787 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk00000788 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk00000789 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk0000078a + (viewRef view_1 (cellRef MUXCY_L (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk0000078b + (viewRef view_1 (cellRef MUXCY_L (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk0000078c + (viewRef view_1 (cellRef MUXCY_L (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk0000078d + (viewRef view_1 (cellRef MUXCY_L (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk0000078e + (viewRef view_1 (cellRef MUXCY_L (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk0000078f + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000790 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000791 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000792 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000793 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000794 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000795 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000796 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000797 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000798 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000799 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000079a + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000079b + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000079c + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000079d + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000079e + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000079f + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007a0 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007a1 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007a2 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007a3 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007a4 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007a5 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007a6 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007a7 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007a8 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007a9 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007aa + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007ab + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007ac + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007ad + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007ae + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007af + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007b0 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007b1 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007b2 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007b3 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007b4 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007b5 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007b6 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007b7 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007b8 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007b9 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007ba + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007bb + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007bc + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007bd + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007be + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007bf + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007c0 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007c1 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007c2 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007c3 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007c4 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007c5 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007c6 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007c7 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007c8 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007c9 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007ca + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007cb + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007cc + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007cd + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007ce + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007cf + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007d0 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007d1 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007d2 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007d3 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007d4 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007d5 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007d6 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007d7 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007d8 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007d9 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007da + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007db + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007dc + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007dd + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007de + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007df + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007e0 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007e1 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007e2 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007e3 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007e4 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007e5 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007e6 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007e7 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007e8 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007e9 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007ea + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007eb + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000007ec + (viewRef view_1 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(viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk00000857 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk00000858 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk00000859 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk0000085a + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk0000085b + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk0000085c + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk0000085d + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk0000085e + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk0000085f + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk00000860 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk00000861 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk00000862 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk00000863 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk00000864 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk00000865 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk00000866 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk00000867 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk00000868 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk00000869 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk0000086a + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk0000086b + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk0000086c + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk0000086d + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk0000086e + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk0000086f + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk00000870 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk00000871 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk00000872 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk00000873 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk00000874 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk00000875 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk00000876 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk00000877 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk00000878 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk00000879 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk0000087a + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk0000087b + (viewRef view_1 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"5140") (owner "Xilinx")) + ) + (instance blk00000886 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk00000887 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk00000888 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk00000889 + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk0000088a + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk0000088b + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk0000088c + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk0000088d + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "5140") (owner "Xilinx")) + ) + (instance blk0000088e + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "04") (owner "Xilinx")) + ) + (instance blk0000088f + (viewRef view_1 (cellRef LUT3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "DE") (owner "Xilinx")) + ) + (instance blk00000890 + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance blk00000891 + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance blk00000892 + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance blk00000893 + (viewRef view_1 (cellRef LUT2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "E") (owner "Xilinx")) + ) + (instance blk00000894 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000895 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000896 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000897 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000898 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000899 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000089a + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance blk0000089b + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000089c + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000089d + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000089e + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance blk0000089f + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance blk000008a0 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000008a1 + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance blk000008a2 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000008a3 + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance blk000008a4 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000008a5 + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance blk000008a6 + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance blk000008a7 + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance blk000008a8 + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance blk000008a9 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance 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+ (instance blk0000091e + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk0000091f + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000920 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000921 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000922 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000923 + (viewRef view_1 (cellRef FDE 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(viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000944 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000945 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000946 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000947 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000948 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000949 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000094a + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk0000094b + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000094c + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk0000094d + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property 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(string "0000") (owner "Xilinx")) + ) + (instance blk000009a3 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000009a4 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000009a5 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000009a6 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000009a7 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000009a8 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000009a9 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000009aa + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000009ab + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000009ac + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000009ad + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000009ae + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000009af + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000009b0 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000009b1 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000009b2 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + 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(boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000009e3 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000009e4 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000009e5 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000009e6 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000009e7 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string 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(viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000009ee + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000009ef + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000009f0 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000009f1 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000009f2 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000009f3 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000009f4 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000009f5 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000009f6 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000009f7 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000009f8 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000009f9 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000009fa + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000009fb + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000009fc + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000009fd + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000009fe + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000009ff + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a00 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a01 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a02 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a03 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a04 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a05 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a06 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a07 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a08 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a09 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a0a + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a0b + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a0c + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a0d + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a0e + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a0f + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a10 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a11 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a12 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a13 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a14 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a15 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a16 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a17 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a18 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a19 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a1a + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a1b + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a1c + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a1d + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a1e + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a1f + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a20 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a21 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a22 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a23 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a24 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a25 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a26 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a27 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a28 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a29 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a2a + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a2b + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a2c + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a2d + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a2e + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a2f + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a30 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a31 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a32 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a33 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a34 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a35 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a36 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a37 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a38 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a39 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a3a + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a3b + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a3c + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a3d + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a3e + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a3f + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a40 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a41 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a42 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a43 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a44 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a45 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a46 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a47 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a48 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a49 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a4a + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a4b + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a4c + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a4d + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a4e + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a4f + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a50 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a51 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a52 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a53 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a54 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a55 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a56 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a57 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a58 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a59 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a5a + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a5b + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a5c + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a5d + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a5e + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a5f + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a60 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a61 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a62 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a63 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a64 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a65 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a66 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a67 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a68 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a69 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a6a + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a6b + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a6c + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a6d + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a6e + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a6f + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a70 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a71 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a72 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a73 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a74 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a75 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a76 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a77 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a78 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a79 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a7a + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a7b + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a7c + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a7d + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a7e + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a7f + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a80 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a81 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a82 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a83 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a84 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a85 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a86 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a87 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a88 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a89 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a8a + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a8b + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a8c + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a8d + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a8e + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a8f + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a90 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a91 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a92 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a93 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a94 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a95 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a96 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a97 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a98 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a99 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a9a + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a9b + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a9c + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a9d + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000a9e + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000a9f + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000aa0 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000aa1 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000aa2 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000aa3 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000aa4 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000aa5 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000aa6 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000aa7 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000aa8 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000aa9 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000aaa + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000aab + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000aac + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000aad + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000aae + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000aaf + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ab0 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000ab1 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ab2 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000ab3 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ab4 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000ab5 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ab6 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000ab7 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ab8 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000ab9 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000aba + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000abb + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000abc + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000abd + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000abe + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000abf + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ac0 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000ac1 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ac2 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000ac3 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ac4 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000ac5 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ac6 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000ac7 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ac8 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000ac9 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000aca + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000acb + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000acc + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000acd + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ace + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000acf + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ad0 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000ad1 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ad2 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000ad3 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ad4 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000ad5 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ad6 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000ad7 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ad8 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000ad9 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ada + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000adb + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000adc + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000add + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ade + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000adf + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ae0 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000ae1 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ae2 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000ae3 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ae4 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000ae5 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ae6 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000ae7 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ae8 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000ae9 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000aea + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000aeb + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000aec + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000aed + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000aee + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000aef + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000af0 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000af1 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000af2 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000af3 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000af4 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000af5 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000af6 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000af7 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000af8 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000af9 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000afa + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000afb + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000afc + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000afd + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000afe + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000aff + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b00 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b01 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b02 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b03 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b04 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b05 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b06 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b07 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b08 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b09 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b0a + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b0b + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b0c + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b0d + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b0e + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b0f + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b10 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b11 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b12 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b13 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b14 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b15 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b16 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b17 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b18 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b19 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b1a + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b1b + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b1c + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b1d + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b1e + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b1f + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b20 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b21 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b22 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b23 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b24 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b25 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b26 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b27 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b28 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b29 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b2a + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b2b + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b2c + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b2d + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b2e + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b2f + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b30 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b31 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b32 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b33 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b34 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b35 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b36 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b37 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b38 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b39 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b3a + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b3b + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b3c + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b3d + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b3e + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b3f + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b40 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b41 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b42 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b43 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b44 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b45 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b46 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b47 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b48 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b49 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b4a + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b4b + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b4c + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b4d + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b4e + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b4f + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b50 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b51 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b52 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b53 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b54 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b55 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b56 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b57 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b58 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b59 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b5a + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b5b + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b5c + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b5d + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b5e + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b5f + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b60 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b61 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b62 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b63 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b64 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b65 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b66 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b67 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b68 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b69 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b6a + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b6b + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b6c + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b6d + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b6e + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b6f + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b70 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b71 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b72 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b73 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b74 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b75 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b76 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b77 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b78 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b79 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b7a + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b7b + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b7c + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b7d + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b7e + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b7f + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b80 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b81 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b82 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b83 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b84 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b85 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b86 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b87 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b88 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b89 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b8a + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b8b + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b8c + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b8d + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b8e + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b8f + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b90 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b91 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b92 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b93 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b94 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000b95 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000b96 + (viewRef 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(string "0000") (owner "Xilinx")) + ) + (instance blk00000ba1 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ba2 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000ba3 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ba4 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000ba5 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ba6 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000ba7 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000ba8 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000ba9 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000baa + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000bab + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000bac + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000bad + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000bae + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000baf + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000bb0 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000bb1 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000bb2 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000bb3 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000bb4 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000bb5 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance 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BUS_INFO (string "24:INPUT:din_11<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:din_12<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:din_13<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:din_14<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:din_15<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:din_16<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "1:OUTPUT:chan_in<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "1:OUTPUT:chan_out<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "47:OUTPUT:dout<46:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:dout_i<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "47:OUTPUT:dout_q<46:0>") (owner "Xilinx")) + (property BUS_INFO (string "47:OUTPUT:dout_1<46:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:dout_i_1<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "47:OUTPUT:dout_q_1<46:0>") (owner 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"dout_2<1>") + (joined + (portRef (member dout_2 45)) + (portRef (member dout_2 45) (instanceRef blk00000003)) + ) + (property USER_ALIAS (string "N722") (owner "Xilinx")) + ) + (net (rename dout_2_renamed_4_0_ "dout_2<0>") + (joined + (portRef (member dout_2 46)) + (portRef (member dout_2 46) (instanceRef blk00000003)) + ) + (property USER_ALIAS (string "N723") (owner "Xilinx")) + ) + ) + ) + ) + ) + + (design hbdec1 + (cellRef hbdec1 + (libraryRef hbdec1_lib) + ) + (property PART (string "7k325tffg900-2") (owner "Xilinx")) + ) +) + diff --git a/top/b200/coregen_dsp/hbdec2.edif b/top/b200/coregen_dsp/hbdec2.edif new file mode 100644 index 0000000..031d238 --- /dev/null +++ b/top/b200/coregen_dsp/hbdec2.edif @@ -0,0 +1,43626 @@ +(edif hbdec2 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2018 8 29 14 59 39) + (program "Xilinx ngc2edif" (version "P_INT.20171106")) + (author "Xilinx. Inc ") + (comment "This EDIF netlist is to be used within supported synthesis tools") + (comment "for determining resource/timing estimates of the design component") + (comment "represented by this netlist.") + (comment "Command line: hbdec2.ngc hbdec2.edif "))) + (external UNISIMS + (edifLevel 0) + (technology (numberDefinition)) + (cell VCC + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port P + (direction OUTPUT) + ) + ) + ) + ) + (cell GND + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port G + (direction OUTPUT) + ) + ) + ) + ) + (cell MUXCY_D + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT) + ) + (port DI + (direction INPUT) + ) + (port S + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + (port LO + (direction OUTPUT) + ) + ) + ) + ) + (cell XORCY + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT) + ) + (port LI + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell FD + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell DSP48E1 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port PATTERNBDETECT + (direction OUTPUT) + ) + (port RSTC + (direction INPUT) + ) + (port CEB1 + (direction INPUT) + ) + (port CEAD + (direction INPUT) + ) + (port MULTSIGNOUT + (direction OUTPUT) + ) + (port CEC + (direction INPUT) + ) + (port RSTM + (direction INPUT) + ) + (port MULTSIGNIN + (direction INPUT) + ) + (port CEB2 + (direction INPUT) + ) + (port RSTCTRL + (direction INPUT) + ) + (port CEP + (direction INPUT) + ) + (port CARRYCASCOUT + (direction OUTPUT) + ) + (port RSTA + (direction INPUT) + ) + (port CECARRYIN + (direction INPUT) + ) + (port UNDERFLOW + (direction OUTPUT) + ) + (port PATTERNDETECT + (direction OUTPUT) + ) + (port RSTALUMODE + (direction INPUT) + ) + (port RSTALLCARRYIN + (direction INPUT) + ) + (port CED + (direction INPUT) + ) + (port RSTD + (direction INPUT) + ) + (port CEALUMODE + (direction INPUT) + ) + (port CEA2 + (direction INPUT) + ) + (port CLK + (direction INPUT) + ) + (port CEA1 + (direction INPUT) + ) + (port RSTB + (direction INPUT) + ) + (port OVERFLOW + (direction OUTPUT) + ) + (port CECTRL + (direction INPUT) + ) + (port CEM + (direction INPUT) + ) + (port CARRYIN + (direction INPUT) + ) + (port CARRYCASCIN + (direction INPUT) + ) + (port RSTINMODE + (direction INPUT) + ) + (port CEINMODE + (direction INPUT) + ) + (port RSTP + (direction INPUT) + ) + (port (rename ACOUT_29_ "ACOUT<29>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename ACOUT_28_ "ACOUT<28>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename ACOUT_27_ "ACOUT<27>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename ACOUT_26_ "ACOUT<26>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename ACOUT_25_ "ACOUT<25>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename ACOUT_24_ "ACOUT<24>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 5) (owner "Xilinx")) + ) + (port (rename ACOUT_23_ "ACOUT<23>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 6) (owner "Xilinx")) + ) + (port (rename ACOUT_22_ "ACOUT<22>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 7) (owner "Xilinx")) + ) + (port (rename ACOUT_21_ "ACOUT<21>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 8) (owner "Xilinx")) + ) + (port (rename ACOUT_20_ "ACOUT<20>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 9) (owner "Xilinx")) + ) + (port (rename ACOUT_19_ "ACOUT<19>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 10) (owner "Xilinx")) + ) + (port (rename ACOUT_18_ "ACOUT<18>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 11) (owner "Xilinx")) + ) + (port (rename ACOUT_17_ "ACOUT<17>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 12) (owner "Xilinx")) + ) + (port (rename ACOUT_16_ "ACOUT<16>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 13) (owner "Xilinx")) + ) + (port (rename ACOUT_15_ "ACOUT<15>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 14) (owner "Xilinx")) + ) + (port (rename ACOUT_14_ "ACOUT<14>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 15) (owner "Xilinx")) + ) + (port (rename ACOUT_13_ "ACOUT<13>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 16) (owner "Xilinx")) + ) + (port (rename ACOUT_12_ "ACOUT<12>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 17) (owner "Xilinx")) + ) + (port (rename ACOUT_11_ "ACOUT<11>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 18) (owner "Xilinx")) + ) + (port (rename ACOUT_10_ "ACOUT<10>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 19) (owner "Xilinx")) + ) + (port (rename ACOUT_9_ "ACOUT<9>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 20) (owner "Xilinx")) + ) + (port (rename ACOUT_8_ "ACOUT<8>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 21) (owner "Xilinx")) + ) + (port (rename ACOUT_7_ "ACOUT<7>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 22) (owner "Xilinx")) + ) + (port (rename ACOUT_6_ "ACOUT<6>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 23) (owner "Xilinx")) + ) + (port (rename ACOUT_5_ "ACOUT<5>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 24) (owner "Xilinx")) + ) + (port (rename ACOUT_4_ "ACOUT<4>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 25) (owner "Xilinx")) + ) + (port (rename ACOUT_3_ "ACOUT<3>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 26) (owner "Xilinx")) + ) + (port (rename ACOUT_2_ "ACOUT<2>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 27) (owner "Xilinx")) + ) + (port (rename ACOUT_1_ "ACOUT<1>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 28) (owner "Xilinx")) + ) + (port (rename ACOUT_0_ "ACOUT<0>") + (direction OUTPUT) + (property PIN_BUSNAME (string "ACOUT<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 29) (owner "Xilinx")) + ) + (port (rename OPMODE_6_ "OPMODE<6>") + (direction INPUT) + (property PIN_BUSNAME (string "OPMODE<6:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename OPMODE_5_ "OPMODE<5>") + (direction INPUT) + (property PIN_BUSNAME (string "OPMODE<6:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename OPMODE_4_ "OPMODE<4>") + (direction INPUT) + (property PIN_BUSNAME (string "OPMODE<6:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename OPMODE_3_ "OPMODE<3>") + (direction INPUT) + (property PIN_BUSNAME (string "OPMODE<6:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename OPMODE_2_ "OPMODE<2>") + (direction INPUT) + (property PIN_BUSNAME (string "OPMODE<6:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename OPMODE_1_ "OPMODE<1>") + (direction INPUT) + (property PIN_BUSNAME (string "OPMODE<6:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 5) (owner "Xilinx")) + ) + (port (rename OPMODE_0_ "OPMODE<0>") + (direction INPUT) + (property PIN_BUSNAME (string "OPMODE<6:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 6) (owner "Xilinx")) + ) + (port (rename PCIN_47_ "PCIN<47>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename PCIN_46_ "PCIN<46>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename PCIN_45_ "PCIN<45>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename PCIN_44_ "PCIN<44>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename PCIN_43_ "PCIN<43>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename PCIN_42_ "PCIN<42>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 5) (owner "Xilinx")) + ) + (port (rename PCIN_41_ "PCIN<41>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 6) (owner "Xilinx")) + ) + (port (rename PCIN_40_ "PCIN<40>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 7) (owner "Xilinx")) + ) + (port (rename PCIN_39_ "PCIN<39>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 8) (owner "Xilinx")) + ) + (port (rename PCIN_38_ "PCIN<38>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 9) (owner "Xilinx")) + ) + (port (rename PCIN_37_ "PCIN<37>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 10) (owner "Xilinx")) + ) + (port (rename PCIN_36_ "PCIN<36>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 11) (owner "Xilinx")) + ) + (port (rename PCIN_35_ "PCIN<35>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 12) (owner "Xilinx")) + ) + (port (rename PCIN_34_ "PCIN<34>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 13) (owner "Xilinx")) + ) + (port (rename PCIN_33_ "PCIN<33>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 14) (owner "Xilinx")) + ) + (port (rename PCIN_32_ "PCIN<32>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 15) (owner "Xilinx")) + ) + (port (rename PCIN_31_ "PCIN<31>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 16) (owner "Xilinx")) + ) + (port (rename PCIN_30_ "PCIN<30>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 17) (owner "Xilinx")) + ) + (port (rename PCIN_29_ "PCIN<29>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 18) (owner "Xilinx")) + ) + (port (rename PCIN_28_ "PCIN<28>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 19) (owner "Xilinx")) + ) + (port (rename PCIN_27_ "PCIN<27>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 20) (owner "Xilinx")) + ) + (port (rename PCIN_26_ "PCIN<26>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 21) (owner "Xilinx")) + ) + (port (rename PCIN_25_ "PCIN<25>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 22) (owner "Xilinx")) + ) + (port (rename PCIN_24_ "PCIN<24>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 23) (owner "Xilinx")) + ) + (port (rename PCIN_23_ "PCIN<23>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 24) (owner "Xilinx")) + ) + (port (rename PCIN_22_ "PCIN<22>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 25) (owner "Xilinx")) + ) + (port (rename PCIN_21_ "PCIN<21>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 26) (owner "Xilinx")) + ) + (port (rename PCIN_20_ "PCIN<20>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 27) (owner "Xilinx")) + ) + (port (rename PCIN_19_ "PCIN<19>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 28) (owner "Xilinx")) + ) + (port (rename PCIN_18_ "PCIN<18>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 29) (owner "Xilinx")) + ) + (port (rename PCIN_17_ "PCIN<17>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 30) (owner "Xilinx")) + ) + (port (rename PCIN_16_ "PCIN<16>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 31) (owner "Xilinx")) + ) + (port (rename PCIN_15_ "PCIN<15>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 32) (owner "Xilinx")) + ) + (port (rename PCIN_14_ "PCIN<14>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 33) (owner "Xilinx")) + ) + (port (rename PCIN_13_ "PCIN<13>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 34) (owner "Xilinx")) + ) + (port (rename PCIN_12_ "PCIN<12>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 35) (owner "Xilinx")) + ) + (port (rename PCIN_11_ "PCIN<11>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 36) (owner "Xilinx")) + ) + (port (rename PCIN_10_ "PCIN<10>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 37) (owner "Xilinx")) + ) + (port (rename PCIN_9_ "PCIN<9>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 38) (owner "Xilinx")) + ) + (port (rename PCIN_8_ "PCIN<8>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 39) (owner "Xilinx")) + ) + (port (rename PCIN_7_ "PCIN<7>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 40) (owner "Xilinx")) + ) + (port (rename PCIN_6_ "PCIN<6>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 41) (owner "Xilinx")) + ) + (port (rename PCIN_5_ "PCIN<5>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 42) (owner "Xilinx")) + ) + (port (rename PCIN_4_ "PCIN<4>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 43) (owner "Xilinx")) + ) + (port (rename PCIN_3_ "PCIN<3>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 44) (owner "Xilinx")) + ) + (port (rename PCIN_2_ "PCIN<2>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 45) (owner "Xilinx")) + ) + (port (rename PCIN_1_ "PCIN<1>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 46) (owner "Xilinx")) + ) + (port (rename PCIN_0_ "PCIN<0>") + (direction INPUT) + (property PIN_BUSNAME (string "PCIN<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 47) (owner "Xilinx")) + ) + (port (rename ALUMODE_3_ "ALUMODE<3>") + (direction INPUT) + (property PIN_BUSNAME (string "ALUMODE<3:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename ALUMODE_2_ "ALUMODE<2>") + (direction INPUT) + (property PIN_BUSNAME (string "ALUMODE<3:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename ALUMODE_1_ "ALUMODE<1>") + (direction INPUT) + (property PIN_BUSNAME (string "ALUMODE<3:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename ALUMODE_0_ "ALUMODE<0>") + (direction INPUT) + (property PIN_BUSNAME (string "ALUMODE<3:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename C_47_ "C<47>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename C_46_ "C<46>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename C_45_ "C<45>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename C_44_ "C<44>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename C_43_ "C<43>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename C_42_ "C<42>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 5) (owner "Xilinx")) + ) + (port (rename C_41_ "C<41>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 6) (owner "Xilinx")) + ) + (port (rename C_40_ "C<40>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 7) (owner "Xilinx")) + ) + (port (rename C_39_ "C<39>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 8) (owner "Xilinx")) + ) + (port (rename C_38_ "C<38>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 9) (owner "Xilinx")) + ) + (port (rename C_37_ "C<37>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 10) (owner "Xilinx")) + ) + (port (rename C_36_ "C<36>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 11) (owner "Xilinx")) + ) + (port (rename C_35_ "C<35>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 12) (owner "Xilinx")) + ) + (port (rename C_34_ "C<34>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 13) (owner "Xilinx")) + ) + (port (rename C_33_ "C<33>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 14) (owner "Xilinx")) + ) + (port (rename C_32_ "C<32>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 15) (owner "Xilinx")) + ) + (port (rename C_31_ "C<31>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 16) (owner "Xilinx")) + ) + (port (rename C_30_ "C<30>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 17) (owner "Xilinx")) + ) + (port (rename C_29_ "C<29>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 18) (owner "Xilinx")) + ) + (port (rename C_28_ "C<28>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 19) (owner "Xilinx")) + ) + (port (rename C_27_ "C<27>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 20) (owner "Xilinx")) + ) + (port (rename C_26_ "C<26>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 21) (owner "Xilinx")) + ) + (port (rename C_25_ "C<25>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 22) (owner "Xilinx")) + ) + (port (rename C_24_ "C<24>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 23) (owner "Xilinx")) + ) + (port (rename C_23_ "C<23>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 24) (owner "Xilinx")) + ) + (port (rename C_22_ "C<22>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 25) (owner "Xilinx")) + ) + (port (rename C_21_ "C<21>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 26) (owner "Xilinx")) + ) + (port (rename C_20_ "C<20>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 27) (owner "Xilinx")) + ) + (port (rename C_19_ "C<19>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 28) (owner "Xilinx")) + ) + (port (rename C_18_ "C<18>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 29) (owner "Xilinx")) + ) + (port (rename C_17_ "C<17>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 30) (owner "Xilinx")) + ) + (port (rename C_16_ "C<16>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 31) (owner "Xilinx")) + ) + (port (rename C_15_ "C<15>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 32) (owner "Xilinx")) + ) + (port (rename C_14_ "C<14>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 33) (owner "Xilinx")) + ) + (port (rename C_13_ "C<13>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 34) (owner "Xilinx")) + ) + (port (rename C_12_ "C<12>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 35) (owner "Xilinx")) + ) + (port (rename C_11_ "C<11>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 36) (owner "Xilinx")) + ) + (port (rename C_10_ "C<10>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 37) (owner "Xilinx")) + ) + (port (rename C_9_ "C<9>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 38) (owner "Xilinx")) + ) + (port (rename C_8_ "C<8>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 39) (owner "Xilinx")) + ) + (port (rename C_7_ "C<7>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 40) (owner "Xilinx")) + ) + (port (rename C_6_ "C<6>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 41) (owner "Xilinx")) + ) + (port (rename C_5_ "C<5>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 42) (owner "Xilinx")) + ) + (port (rename C_4_ "C<4>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 43) (owner "Xilinx")) + ) + (port (rename C_3_ "C<3>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 44) (owner "Xilinx")) + ) + (port (rename C_2_ "C<2>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 45) (owner "Xilinx")) + ) + (port (rename C_1_ "C<1>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 46) (owner "Xilinx")) + ) + (port (rename C_0_ "C<0>") + (direction INPUT) + (property PIN_BUSNAME (string "C<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 47) (owner "Xilinx")) + ) + (port (rename CARRYOUT_3_ "CARRYOUT<3>") + (direction OUTPUT) + (property PIN_BUSNAME (string "CARRYOUT<3:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename CARRYOUT_2_ "CARRYOUT<2>") + (direction OUTPUT) + (property PIN_BUSNAME (string "CARRYOUT<3:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename CARRYOUT_1_ "CARRYOUT<1>") + (direction OUTPUT) + (property PIN_BUSNAME (string "CARRYOUT<3:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename CARRYOUT_0_ "CARRYOUT<0>") + (direction OUTPUT) + (property PIN_BUSNAME (string "CARRYOUT<3:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename INMODE_4_ "INMODE<4>") + (direction INPUT) + (property PIN_BUSNAME (string "INMODE<4:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename INMODE_3_ "INMODE<3>") + (direction INPUT) + (property PIN_BUSNAME (string "INMODE<4:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename INMODE_2_ "INMODE<2>") + (direction INPUT) + (property PIN_BUSNAME (string "INMODE<4:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename INMODE_1_ "INMODE<1>") + (direction INPUT) + (property PIN_BUSNAME (string "INMODE<4:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename INMODE_0_ "INMODE<0>") + (direction INPUT) + (property PIN_BUSNAME (string "INMODE<4:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename BCIN_17_ "BCIN<17>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename BCIN_16_ "BCIN<16>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename BCIN_15_ "BCIN<15>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename BCIN_14_ "BCIN<14>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename BCIN_13_ "BCIN<13>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename BCIN_12_ "BCIN<12>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 5) (owner "Xilinx")) + ) + (port (rename BCIN_11_ "BCIN<11>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 6) (owner "Xilinx")) + ) + (port (rename BCIN_10_ "BCIN<10>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 7) (owner "Xilinx")) + ) + (port (rename BCIN_9_ "BCIN<9>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 8) (owner "Xilinx")) + ) + (port (rename BCIN_8_ "BCIN<8>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 9) (owner "Xilinx")) + ) + (port (rename BCIN_7_ "BCIN<7>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 10) (owner "Xilinx")) + ) + (port (rename BCIN_6_ "BCIN<6>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 11) (owner "Xilinx")) + ) + (port (rename BCIN_5_ "BCIN<5>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 12) (owner "Xilinx")) + ) + (port (rename BCIN_4_ "BCIN<4>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 13) (owner "Xilinx")) + ) + (port (rename BCIN_3_ "BCIN<3>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 14) (owner "Xilinx")) + ) + (port (rename BCIN_2_ "BCIN<2>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 15) (owner "Xilinx")) + ) + (port (rename BCIN_1_ "BCIN<1>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 16) (owner "Xilinx")) + ) + (port (rename BCIN_0_ "BCIN<0>") + (direction INPUT) + (property PIN_BUSNAME (string "BCIN<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 17) (owner "Xilinx")) + ) + (port (rename B_17_ "B<17>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename B_16_ "B<16>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename B_15_ "B<15>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename B_14_ "B<14>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename B_13_ "B<13>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename B_12_ "B<12>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 5) (owner "Xilinx")) + ) + (port (rename B_11_ "B<11>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 6) (owner "Xilinx")) + ) + (port (rename B_10_ "B<10>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 7) (owner "Xilinx")) + ) + (port (rename B_9_ "B<9>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 8) (owner "Xilinx")) + ) + (port (rename B_8_ "B<8>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 9) (owner "Xilinx")) + ) + (port (rename B_7_ "B<7>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 10) (owner "Xilinx")) + ) + (port (rename B_6_ "B<6>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 11) (owner "Xilinx")) + ) + (port (rename B_5_ "B<5>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 12) (owner "Xilinx")) + ) + (port (rename B_4_ "B<4>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 13) (owner "Xilinx")) + ) + (port (rename B_3_ "B<3>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 14) (owner "Xilinx")) + ) + (port (rename B_2_ "B<2>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 15) (owner "Xilinx")) + ) + (port (rename B_1_ "B<1>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 16) (owner "Xilinx")) + ) + (port (rename B_0_ "B<0>") + (direction INPUT) + (property PIN_BUSNAME (string "B<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 17) (owner "Xilinx")) + ) + (port (rename BCOUT_17_ "BCOUT<17>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename BCOUT_16_ "BCOUT<16>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename BCOUT_15_ "BCOUT<15>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename BCOUT_14_ "BCOUT<14>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename BCOUT_13_ "BCOUT<13>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename BCOUT_12_ "BCOUT<12>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 5) (owner "Xilinx")) + ) + (port (rename BCOUT_11_ "BCOUT<11>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 6) (owner "Xilinx")) + ) + (port (rename BCOUT_10_ "BCOUT<10>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 7) (owner "Xilinx")) + ) + (port (rename BCOUT_9_ "BCOUT<9>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 8) (owner "Xilinx")) + ) + (port (rename BCOUT_8_ "BCOUT<8>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 9) (owner "Xilinx")) + ) + (port (rename BCOUT_7_ "BCOUT<7>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 10) (owner "Xilinx")) + ) + (port (rename BCOUT_6_ "BCOUT<6>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 11) (owner "Xilinx")) + ) + (port (rename BCOUT_5_ "BCOUT<5>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 12) (owner "Xilinx")) + ) + (port (rename BCOUT_4_ "BCOUT<4>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 13) (owner "Xilinx")) + ) + (port (rename BCOUT_3_ "BCOUT<3>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 14) (owner "Xilinx")) + ) + (port (rename BCOUT_2_ "BCOUT<2>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 15) (owner "Xilinx")) + ) + (port (rename BCOUT_1_ "BCOUT<1>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 16) (owner "Xilinx")) + ) + (port (rename BCOUT_0_ "BCOUT<0>") + (direction OUTPUT) + (property PIN_BUSNAME (string "BCOUT<17:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 17) (owner "Xilinx")) + ) + (port (rename D_24_ "D<24>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename D_23_ "D<23>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename D_22_ "D<22>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename D_21_ "D<21>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename D_20_ "D<20>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename D_19_ "D<19>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 5) (owner "Xilinx")) + ) + (port (rename D_18_ "D<18>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 6) (owner "Xilinx")) + ) + (port (rename D_17_ "D<17>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 7) (owner "Xilinx")) + ) + (port (rename D_16_ "D<16>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 8) (owner "Xilinx")) + ) + (port (rename D_15_ "D<15>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 9) (owner "Xilinx")) + ) + (port (rename D_14_ "D<14>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 10) (owner "Xilinx")) + ) + (port (rename D_13_ "D<13>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 11) (owner "Xilinx")) + ) + (port (rename D_12_ "D<12>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 12) (owner "Xilinx")) + ) + (port (rename D_11_ "D<11>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 13) (owner "Xilinx")) + ) + (port (rename D_10_ "D<10>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 14) (owner "Xilinx")) + ) + (port (rename D_9_ "D<9>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 15) (owner "Xilinx")) + ) + (port (rename D_8_ "D<8>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 16) (owner "Xilinx")) + ) + (port (rename D_7_ "D<7>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 17) (owner "Xilinx")) + ) + (port (rename D_6_ "D<6>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 18) (owner "Xilinx")) + ) + (port (rename D_5_ "D<5>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 19) (owner "Xilinx")) + ) + (port (rename D_4_ "D<4>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 20) (owner "Xilinx")) + ) + (port (rename D_3_ "D<3>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 21) (owner "Xilinx")) + ) + (port (rename D_2_ "D<2>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 22) (owner "Xilinx")) + ) + (port (rename D_1_ "D<1>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 23) (owner "Xilinx")) + ) + (port (rename D_0_ "D<0>") + (direction INPUT) + (property PIN_BUSNAME (string "D<24:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 24) (owner "Xilinx")) + ) + (port (rename P_47_ "P<47>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename P_46_ "P<46>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename P_45_ "P<45>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename P_44_ "P<44>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename P_43_ "P<43>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename P_42_ "P<42>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 5) (owner "Xilinx")) + ) + (port (rename P_41_ "P<41>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 6) (owner "Xilinx")) + ) + (port (rename P_40_ "P<40>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 7) (owner "Xilinx")) + ) + (port (rename P_39_ "P<39>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 8) (owner "Xilinx")) + ) + (port (rename P_38_ "P<38>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 9) (owner "Xilinx")) + ) + (port (rename P_37_ "P<37>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 10) (owner "Xilinx")) + ) + (port (rename P_36_ "P<36>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 11) (owner "Xilinx")) + ) + (port (rename P_35_ "P<35>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 12) (owner "Xilinx")) + ) + (port (rename P_34_ "P<34>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 13) (owner "Xilinx")) + ) + (port (rename P_33_ "P<33>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 14) (owner "Xilinx")) + ) + (port (rename P_32_ "P<32>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 15) (owner "Xilinx")) + ) + (port (rename P_31_ "P<31>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 16) (owner "Xilinx")) + ) + (port (rename P_30_ "P<30>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 17) (owner "Xilinx")) + ) + (port (rename P_29_ "P<29>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 18) (owner "Xilinx")) + ) + (port (rename P_28_ "P<28>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 19) (owner "Xilinx")) + ) + (port (rename P_27_ "P<27>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 20) (owner "Xilinx")) + ) + (port (rename P_26_ "P<26>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 21) (owner "Xilinx")) + ) + (port (rename P_25_ "P<25>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 22) (owner "Xilinx")) + ) + (port (rename P_24_ "P<24>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 23) (owner "Xilinx")) + ) + (port (rename P_23_ "P<23>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 24) (owner "Xilinx")) + ) + (port (rename P_22_ "P<22>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 25) (owner "Xilinx")) + ) + (port (rename P_21_ "P<21>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 26) (owner "Xilinx")) + ) + (port (rename P_20_ "P<20>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 27) (owner "Xilinx")) + ) + (port (rename P_19_ "P<19>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 28) (owner "Xilinx")) + ) + (port (rename P_18_ "P<18>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 29) (owner "Xilinx")) + ) + (port (rename P_17_ "P<17>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 30) (owner "Xilinx")) + ) + (port (rename P_16_ "P<16>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 31) (owner "Xilinx")) + ) + (port (rename P_15_ "P<15>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 32) (owner "Xilinx")) + ) + (port (rename P_14_ "P<14>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 33) (owner "Xilinx")) + ) + (port (rename P_13_ "P<13>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 34) (owner "Xilinx")) + ) + (port (rename P_12_ "P<12>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 35) (owner "Xilinx")) + ) + (port (rename P_11_ "P<11>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 36) (owner "Xilinx")) + ) + (port (rename P_10_ "P<10>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 37) (owner "Xilinx")) + ) + (port (rename P_9_ "P<9>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 38) (owner "Xilinx")) + ) + (port (rename P_8_ "P<8>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 39) (owner "Xilinx")) + ) + (port (rename P_7_ "P<7>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 40) (owner "Xilinx")) + ) + (port (rename P_6_ "P<6>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 41) (owner "Xilinx")) + ) + (port (rename P_5_ "P<5>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 42) (owner "Xilinx")) + ) + (port (rename P_4_ "P<4>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 43) (owner "Xilinx")) + ) + (port (rename P_3_ "P<3>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 44) (owner "Xilinx")) + ) + (port (rename P_2_ "P<2>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 45) (owner "Xilinx")) + ) + (port (rename P_1_ "P<1>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 46) (owner "Xilinx")) + ) + (port (rename P_0_ "P<0>") + (direction OUTPUT) + (property PIN_BUSNAME (string "P<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 47) (owner "Xilinx")) + ) + (port (rename A_29_ "A<29>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename A_28_ "A<28>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename A_27_ "A<27>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename A_26_ "A<26>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename A_25_ "A<25>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename A_24_ "A<24>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 5) (owner "Xilinx")) + ) + (port (rename A_23_ "A<23>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 6) (owner "Xilinx")) + ) + (port (rename A_22_ "A<22>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 7) (owner "Xilinx")) + ) + (port (rename A_21_ "A<21>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 8) (owner "Xilinx")) + ) + (port (rename A_20_ "A<20>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 9) (owner "Xilinx")) + ) + (port (rename A_19_ "A<19>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 10) (owner "Xilinx")) + ) + (port (rename A_18_ "A<18>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 11) (owner "Xilinx")) + ) + (port (rename A_17_ "A<17>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 12) (owner "Xilinx")) + ) + (port (rename A_16_ "A<16>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 13) (owner "Xilinx")) + ) + (port (rename A_15_ "A<15>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 14) (owner "Xilinx")) + ) + (port (rename A_14_ "A<14>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 15) (owner "Xilinx")) + ) + (port (rename A_13_ "A<13>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 16) (owner "Xilinx")) + ) + (port (rename A_12_ "A<12>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 17) (owner "Xilinx")) + ) + (port (rename A_11_ "A<11>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 18) (owner "Xilinx")) + ) + (port (rename A_10_ "A<10>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 19) (owner "Xilinx")) + ) + (port (rename A_9_ "A<9>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 20) (owner "Xilinx")) + ) + (port (rename A_8_ "A<8>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 21) (owner "Xilinx")) + ) + (port (rename A_7_ "A<7>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 22) (owner "Xilinx")) + ) + (port (rename A_6_ "A<6>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 23) (owner "Xilinx")) + ) + (port (rename A_5_ "A<5>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 24) (owner "Xilinx")) + ) + (port (rename A_4_ "A<4>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 25) (owner "Xilinx")) + ) + (port (rename A_3_ "A<3>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 26) (owner "Xilinx")) + ) + (port (rename A_2_ "A<2>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 27) (owner "Xilinx")) + ) + (port (rename A_1_ "A<1>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 28) (owner "Xilinx")) + ) + (port (rename A_0_ "A<0>") + (direction INPUT) + (property PIN_BUSNAME (string "A<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 29) (owner "Xilinx")) + ) + (port (rename PCOUT_47_ "PCOUT<47>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename PCOUT_46_ "PCOUT<46>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename PCOUT_45_ "PCOUT<45>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename PCOUT_44_ "PCOUT<44>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename PCOUT_43_ "PCOUT<43>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename PCOUT_42_ "PCOUT<42>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 5) (owner "Xilinx")) + ) + (port (rename PCOUT_41_ "PCOUT<41>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 6) (owner "Xilinx")) + ) + (port (rename PCOUT_40_ "PCOUT<40>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 7) (owner "Xilinx")) + ) + (port (rename PCOUT_39_ "PCOUT<39>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 8) (owner "Xilinx")) + ) + (port (rename PCOUT_38_ "PCOUT<38>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 9) (owner "Xilinx")) + ) + (port (rename PCOUT_37_ "PCOUT<37>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 10) (owner "Xilinx")) + ) + (port (rename PCOUT_36_ "PCOUT<36>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 11) (owner "Xilinx")) + ) + (port (rename PCOUT_35_ "PCOUT<35>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 12) (owner "Xilinx")) + ) + (port (rename PCOUT_34_ "PCOUT<34>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 13) (owner "Xilinx")) + ) + (port (rename PCOUT_33_ "PCOUT<33>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 14) (owner "Xilinx")) + ) + (port (rename PCOUT_32_ "PCOUT<32>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 15) (owner "Xilinx")) + ) + (port (rename PCOUT_31_ "PCOUT<31>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 16) (owner "Xilinx")) + ) + (port (rename PCOUT_30_ "PCOUT<30>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 17) (owner "Xilinx")) + ) + (port (rename PCOUT_29_ "PCOUT<29>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 18) (owner "Xilinx")) + ) + (port (rename PCOUT_28_ "PCOUT<28>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 19) (owner "Xilinx")) + ) + (port (rename PCOUT_27_ "PCOUT<27>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 20) (owner "Xilinx")) + ) + (port (rename PCOUT_26_ "PCOUT<26>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 21) (owner "Xilinx")) + ) + (port (rename PCOUT_25_ "PCOUT<25>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 22) (owner "Xilinx")) + ) + (port (rename PCOUT_24_ "PCOUT<24>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 23) (owner "Xilinx")) + ) + (port (rename PCOUT_23_ "PCOUT<23>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 24) (owner "Xilinx")) + ) + (port (rename PCOUT_22_ "PCOUT<22>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 25) (owner "Xilinx")) + ) + (port (rename PCOUT_21_ "PCOUT<21>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 26) (owner "Xilinx")) + ) + (port (rename PCOUT_20_ "PCOUT<20>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 27) (owner "Xilinx")) + ) + (port (rename PCOUT_19_ "PCOUT<19>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 28) (owner "Xilinx")) + ) + (port (rename PCOUT_18_ "PCOUT<18>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 29) (owner "Xilinx")) + ) + (port (rename PCOUT_17_ "PCOUT<17>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 30) (owner "Xilinx")) + ) + (port (rename PCOUT_16_ "PCOUT<16>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 31) (owner "Xilinx")) + ) + (port (rename PCOUT_15_ "PCOUT<15>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 32) (owner "Xilinx")) + ) + (port (rename PCOUT_14_ "PCOUT<14>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 33) (owner "Xilinx")) + ) + (port (rename PCOUT_13_ "PCOUT<13>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 34) (owner "Xilinx")) + ) + (port (rename PCOUT_12_ "PCOUT<12>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 35) (owner "Xilinx")) + ) + (port (rename PCOUT_11_ "PCOUT<11>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 36) (owner "Xilinx")) + ) + (port (rename PCOUT_10_ "PCOUT<10>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 37) (owner "Xilinx")) + ) + (port (rename PCOUT_9_ "PCOUT<9>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 38) (owner "Xilinx")) + ) + (port (rename PCOUT_8_ "PCOUT<8>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 39) (owner "Xilinx")) + ) + (port (rename PCOUT_7_ "PCOUT<7>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 40) (owner "Xilinx")) + ) + (port (rename PCOUT_6_ "PCOUT<6>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 41) (owner "Xilinx")) + ) + (port (rename PCOUT_5_ "PCOUT<5>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 42) (owner "Xilinx")) + ) + (port (rename PCOUT_4_ "PCOUT<4>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 43) (owner "Xilinx")) + ) + (port (rename PCOUT_3_ "PCOUT<3>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 44) (owner "Xilinx")) + ) + (port (rename PCOUT_2_ "PCOUT<2>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 45) (owner "Xilinx")) + ) + (port (rename PCOUT_1_ "PCOUT<1>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 46) (owner "Xilinx")) + ) + (port (rename PCOUT_0_ "PCOUT<0>") + (direction OUTPUT) + (property PIN_BUSNAME (string "PCOUT<47:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 47) (owner "Xilinx")) + ) + (port (rename ACIN_29_ "ACIN<29>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename ACIN_28_ "ACIN<28>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename ACIN_27_ "ACIN<27>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + (port (rename ACIN_26_ "ACIN<26>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 3) (owner "Xilinx")) + ) + (port (rename ACIN_25_ "ACIN<25>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 4) (owner "Xilinx")) + ) + (port (rename ACIN_24_ "ACIN<24>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 5) (owner "Xilinx")) + ) + (port (rename ACIN_23_ "ACIN<23>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 6) (owner "Xilinx")) + ) + (port (rename ACIN_22_ "ACIN<22>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 7) (owner "Xilinx")) + ) + (port (rename ACIN_21_ "ACIN<21>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 8) (owner "Xilinx")) + ) + (port (rename ACIN_20_ "ACIN<20>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 9) (owner "Xilinx")) + ) + (port (rename ACIN_19_ "ACIN<19>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 10) (owner "Xilinx")) + ) + (port (rename ACIN_18_ "ACIN<18>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 11) (owner "Xilinx")) + ) + (port (rename ACIN_17_ "ACIN<17>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 12) (owner "Xilinx")) + ) + (port (rename ACIN_16_ "ACIN<16>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 13) (owner "Xilinx")) + ) + (port (rename ACIN_15_ "ACIN<15>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 14) (owner "Xilinx")) + ) + (port (rename ACIN_14_ "ACIN<14>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 15) (owner "Xilinx")) + ) + (port (rename ACIN_13_ "ACIN<13>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 16) (owner "Xilinx")) + ) + (port (rename ACIN_12_ "ACIN<12>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 17) (owner "Xilinx")) + ) + (port (rename ACIN_11_ "ACIN<11>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 18) (owner "Xilinx")) + ) + (port (rename ACIN_10_ "ACIN<10>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 19) (owner "Xilinx")) + ) + (port (rename ACIN_9_ "ACIN<9>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 20) (owner "Xilinx")) + ) + (port (rename ACIN_8_ "ACIN<8>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 21) (owner "Xilinx")) + ) + (port (rename ACIN_7_ "ACIN<7>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 22) (owner "Xilinx")) + ) + (port (rename ACIN_6_ "ACIN<6>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 23) (owner "Xilinx")) + ) + (port (rename ACIN_5_ "ACIN<5>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 24) (owner "Xilinx")) + ) + (port (rename ACIN_4_ "ACIN<4>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 25) (owner "Xilinx")) + ) + (port (rename ACIN_3_ "ACIN<3>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 26) (owner "Xilinx")) + ) + (port (rename ACIN_2_ "ACIN<2>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 27) (owner "Xilinx")) + ) + (port (rename ACIN_1_ "ACIN<1>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 28) (owner "Xilinx")) + ) + (port (rename ACIN_0_ "ACIN<0>") + (direction INPUT) + (property PIN_BUSNAME (string "ACIN<29:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 29) (owner "Xilinx")) + ) + (port (rename CARRYINSEL_2_ "CARRYINSEL<2>") + (direction INPUT) + (property PIN_BUSNAME (string "CARRYINSEL<2:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 0) (owner "Xilinx")) + ) + (port (rename CARRYINSEL_1_ "CARRYINSEL<1>") + (direction INPUT) + (property PIN_BUSNAME (string "CARRYINSEL<2:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 1) (owner "Xilinx")) + ) + (port (rename CARRYINSEL_0_ "CARRYINSEL<0>") + (direction INPUT) + (property PIN_BUSNAME (string "CARRYINSEL<2:0>") (owner "Xilinx")) + (property PIN_BUSIDX (integer 2) (owner "Xilinx")) + ) + ) + ) + ) + (cell MUXCY + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT) + ) + (port DI + (direction INPUT) + ) + (port S + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell FDSE + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port S + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell FDRE + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port R + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell FDE + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell FDR + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port C + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port R + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + ) + ) + ) + (cell RAM32X1D + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port A0 + (direction INPUT) + ) + (port A1 + (direction INPUT) + ) + (port A2 + (direction INPUT) + ) + (port A3 + (direction INPUT) + ) + (port A4 + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port DPRA0 + (direction INPUT) + ) + (port DPRA1 + (direction INPUT) + ) + (port DPRA2 + (direction INPUT) + ) + (port DPRA3 + (direction INPUT) + ) + (port DPRA4 + (direction INPUT) + ) + (port WCLK + (direction INPUT) + ) + (port WE + (direction INPUT) + ) + (port SPO + (direction OUTPUT) + ) + (port DPO + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT2 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell MUXCY_L + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT) + ) + (port DI + (direction INPUT) + ) + (port S + (direction INPUT) + ) + (port LO + (direction OUTPUT) + ) + ) + ) + ) + (cell SRLC16E + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port A0 + (direction INPUT) + ) + (port A1 + (direction INPUT) + ) + (port A2 + (direction INPUT) + ) + (port A3 + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + (port CLK + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port Q + (direction OUTPUT) + ) + (port Q15 + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT4 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT3 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT5 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port I4 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT1 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell INV + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + ) + + (library hbdec2_lib + (edifLevel 0) + (technology (numberDefinition)) + (cell (rename dpr_ram_5_blk000004a4 "dpr_ram_5") + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port WEA + (direction INPUT) + ) + (port CE + (direction INPUT) + ) + (port SCLR + (direction INPUT) + ) + (port CLK + (direction INPUT) + ) + (port (array (rename ADDRA "ADDRA<0:0>") 1) + (direction INPUT)) + (port (array (rename DA_IN "DA_IN<17:0>") 18) + (direction INPUT)) + (port (array (rename ADDRB "ADDRB<0:0>") 1) + (direction INPUT)) + (port (array (rename DA_OUT "DA_OUT<17:0>") 18) + (direction OUTPUT)) + (port (array (rename DB_OUT "DB_OUT<17:0>") 18) + (direction OUTPUT)) + ) + (contents + (instance blk000004a5 + (viewRef view_1 (cellRef GND (libraryRef UNISIMS))) + (property XSTLIB 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"Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000021 + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance blk00000022 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance blk00000023 + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance blk00000024 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000025 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance blk00000026 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000027 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000028 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000029 + (viewRef view_1 (cellRef FDR (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance blk0000002a + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000002b + (viewRef view_1 (cellRef dpr_ram_1_blk0000002b (libraryRef hbdec2_lib))) + (property BUS_INFO (string "2:INPUT:ADDRA<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:DA_IN<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "2:INPUT:ADDRB<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:DA_OUT<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:DB_OUT<47:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 2) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "dpr_ram_1_blk0000002b") (owner "Xilinx")) + ) + (instance blk0000008e + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance blk0000008f + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000090 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk00000091 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk00000092 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk00000093 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk00000094 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk00000095 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk00000096 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk00000097 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk00000098 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk00000099 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000009a + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000009b + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000009c + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000009d + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000009e + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000009f + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000a0 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000a1 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000a2 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000a3 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000a4 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000a5 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000a6 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000a7 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000a8 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000a9 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000aa + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000ab + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000ac + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000ad + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000ae + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000af + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000b0 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000b1 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000b2 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000b3 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000b4 + (viewRef view_1 (cellRef MUXCY_L (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000b5 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000b6 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000b7 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000b8 + (viewRef view_1 (cellRef MUXCY_L (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000b9 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000ba + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000bb + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000bc + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000bd + (viewRef view_1 (cellRef MUXCY_L (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000be + (viewRef view_1 (cellRef MUXCY_L (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000bf + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000c0 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000c1 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000c2 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000c3 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000c4 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance blk000000c5 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000c6 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000c7 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000c8 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000c9 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000ca + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000cb + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000cc + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000cd + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000ce + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance blk000000cf + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000d0 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000d1 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000d2 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000d3 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000d4 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000d5 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000d6 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000d7 + (viewRef view_1 (cellRef FDSE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "1") (owner "Xilinx")) + ) + (instance blk000000d8 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000d9 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000da + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000db + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000dc + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000dd + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000de + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000df + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000e0 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000e1 + (viewRef view_1 (cellRef MUXCY_L (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000e2 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000e3 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000e4 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000e5 + (viewRef view_1 (cellRef MUXCY_L (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000e6 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance blk000000e7 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000e8 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000e9 + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000ea + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000eb + (viewRef view_1 (cellRef MUXCY_L (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000ec + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000ed + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000ee + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000ef + (viewRef view_1 (cellRef MUXCY_L (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000f0 + (viewRef view_1 (cellRef MUXCY_L (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000f1 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000f2 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000f3 + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000000f4 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000f5 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000f6 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000f7 + (viewRef view_1 (cellRef DSP48E1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "3:INPUT:CARRYINSEL<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:CARRYOUT<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:INPUT:ALUMODE<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "7:INPUT:OPMODE<6:0>") (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:INMODE<4:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:OUTPUT:ACOUT<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:BCOUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:PCOUT<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:PCIN<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:BCIN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:ACIN<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:C<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:B<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "25:INPUT:D<24:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:P<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:A<29:0>") (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property ACASCREG (integer 1) (owner "Xilinx")) + (property ADREG (integer 1) (owner "Xilinx")) + (property ALUMODEREG (integer 0) (owner "Xilinx")) + (property AREG (integer 1) (owner "Xilinx")) + (property AUTORESET_PATDET (string "NO_RESET") (owner "Xilinx")) + (property A_INPUT (string "DIRECT") (owner "Xilinx")) + (property BCASCREG (integer 1) (owner "Xilinx")) + (property BREG (integer 1) (owner "Xilinx")) + (property B_INPUT (string "DIRECT") (owner "Xilinx")) + (property CARRYINREG (integer 1) (owner "Xilinx")) + (property CARRYINSELREG (integer 1) (owner "Xilinx")) + (property CREG (integer 1) (owner "Xilinx")) + (property DREG (integer 1) (owner "Xilinx")) + (property INMODEREG (integer 1) (owner "Xilinx")) + (property MASK (string "FFFFFFFFFFFE") (owner "Xilinx")) + (property MREG (integer 1) (owner "Xilinx")) + (property OPMODEREG (integer 0) (owner "Xilinx")) + (property PATTERN (string "000000000000") (owner "Xilinx")) + (property PREG (integer 1) (owner "Xilinx")) + (property SEL_MASK (string "MASK") (owner "Xilinx")) + (property SEL_PATTERN (string "PATTERN") (owner "Xilinx")) + (property USE_DPORT (string "TRUE") (owner "Xilinx")) + (property USE_MULT (string "MULTIPLY") (owner "Xilinx")) + (property USE_PATTERN_DETECT (string "NO_PATDET") (owner "Xilinx")) + (property USE_SIMD (string "ONE48") (owner "Xilinx")) + ) + (instance blk000000f8 + (viewRef view_1 (cellRef DSP48E1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "3:INPUT:CARRYINSEL<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:CARRYOUT<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:INPUT:ALUMODE<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "7:INPUT:OPMODE<6:0>") (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:INMODE<4:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:OUTPUT:ACOUT<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:BCOUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:PCOUT<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:PCIN<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:BCIN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:ACIN<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:C<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:B<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "25:INPUT:D<24:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:P<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:A<29:0>") (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property ACASCREG (integer 1) (owner "Xilinx")) + (property ADREG (integer 1) (owner "Xilinx")) + (property ALUMODEREG (integer 0) (owner "Xilinx")) + (property AREG (integer 1) (owner "Xilinx")) + (property AUTORESET_PATDET (string "NO_RESET") (owner "Xilinx")) + (property A_INPUT (string "DIRECT") (owner "Xilinx")) + (property BCASCREG (integer 1) (owner "Xilinx")) + (property BREG (integer 1) (owner "Xilinx")) + (property B_INPUT (string "DIRECT") (owner "Xilinx")) + (property CARRYINREG (integer 1) (owner "Xilinx")) + (property CARRYINSELREG (integer 1) (owner "Xilinx")) + (property CREG (integer 1) (owner "Xilinx")) + (property DREG (integer 1) (owner "Xilinx")) + (property INMODEREG (integer 1) (owner "Xilinx")) + (property MASK (string "FFFFFFFFFFFE") (owner "Xilinx")) + (property MREG (integer 1) (owner "Xilinx")) + (property OPMODEREG (integer 0) (owner "Xilinx")) + (property PATTERN (string "000000000000") (owner "Xilinx")) + (property PREG (integer 1) (owner "Xilinx")) + (property SEL_MASK (string "MASK") (owner "Xilinx")) + (property SEL_PATTERN (string "PATTERN") (owner "Xilinx")) + (property USE_DPORT (string "TRUE") (owner "Xilinx")) + (property USE_MULT (string "MULTIPLY") (owner "Xilinx")) + (property USE_PATTERN_DETECT (string "NO_PATDET") (owner "Xilinx")) + (property USE_SIMD (string "ONE48") (owner "Xilinx")) + ) + (instance blk000000f9 + (viewRef view_1 (cellRef DSP48E1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "3:INPUT:CARRYINSEL<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:CARRYOUT<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:INPUT:ALUMODE<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "7:INPUT:OPMODE<6:0>") (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:INMODE<4:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:OUTPUT:ACOUT<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:BCOUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:PCOUT<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:PCIN<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:BCIN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:ACIN<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:C<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:B<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "25:INPUT:D<24:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:P<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:A<29:0>") (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property ACASCREG (integer 1) (owner "Xilinx")) + (property ADREG (integer 1) (owner "Xilinx")) + (property ALUMODEREG (integer 0) (owner "Xilinx")) + (property AREG (integer 1) (owner "Xilinx")) + (property AUTORESET_PATDET (string "NO_RESET") (owner "Xilinx")) + (property A_INPUT (string "DIRECT") (owner "Xilinx")) + (property BCASCREG (integer 1) (owner "Xilinx")) + (property BREG (integer 1) (owner "Xilinx")) + (property B_INPUT (string "DIRECT") (owner "Xilinx")) + (property CARRYINREG (integer 1) (owner "Xilinx")) + (property CARRYINSELREG (integer 1) (owner "Xilinx")) + (property CREG (integer 1) (owner "Xilinx")) + (property DREG (integer 1) (owner "Xilinx")) + (property INMODEREG (integer 1) (owner "Xilinx")) + (property MASK (string "FFFFFFFFFFFE") (owner "Xilinx")) + (property MREG (integer 1) (owner "Xilinx")) + (property OPMODEREG (integer 0) (owner "Xilinx")) + (property PATTERN (string "000000000000") (owner "Xilinx")) + (property PREG (integer 1) (owner "Xilinx")) + (property SEL_MASK (string "MASK") (owner "Xilinx")) + (property SEL_PATTERN (string "PATTERN") (owner "Xilinx")) + (property USE_DPORT (string "TRUE") (owner "Xilinx")) + (property USE_MULT (string "MULTIPLY") (owner "Xilinx")) + (property USE_PATTERN_DETECT (string "NO_PATDET") (owner "Xilinx")) + (property USE_SIMD (string "ONE48") (owner "Xilinx")) + ) + (instance blk000000fa + (viewRef view_1 (cellRef DSP48E1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "3:INPUT:CARRYINSEL<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:CARRYOUT<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:INPUT:ALUMODE<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "7:INPUT:OPMODE<6:0>") (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:INMODE<4:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:OUTPUT:ACOUT<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:BCOUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:PCOUT<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:PCIN<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:BCIN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:ACIN<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:C<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:B<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "25:INPUT:D<24:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:P<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:A<29:0>") (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property ACASCREG (integer 1) (owner "Xilinx")) + (property ADREG (integer 1) (owner "Xilinx")) + (property ALUMODEREG (integer 0) (owner "Xilinx")) + (property AREG (integer 1) (owner "Xilinx")) + (property AUTORESET_PATDET (string "NO_RESET") (owner "Xilinx")) + (property A_INPUT (string "DIRECT") (owner "Xilinx")) + (property BCASCREG (integer 1) (owner "Xilinx")) + (property BREG (integer 1) (owner "Xilinx")) + (property B_INPUT (string "DIRECT") (owner "Xilinx")) + (property CARRYINREG (integer 1) (owner "Xilinx")) + (property CARRYINSELREG (integer 1) (owner "Xilinx")) + (property CREG (integer 1) (owner "Xilinx")) + (property DREG (integer 1) (owner "Xilinx")) + (property INMODEREG (integer 1) (owner "Xilinx")) + (property MASK (string "FFFFFFFFFFFE") (owner "Xilinx")) + (property MREG (integer 1) (owner "Xilinx")) + (property OPMODEREG (integer 0) (owner "Xilinx")) + (property PATTERN (string "000000000000") (owner "Xilinx")) + (property PREG (integer 1) (owner "Xilinx")) + (property SEL_MASK (string "MASK") (owner "Xilinx")) + (property SEL_PATTERN (string "PATTERN") (owner "Xilinx")) + (property USE_DPORT (string "TRUE") (owner "Xilinx")) + (property USE_MULT (string "MULTIPLY") (owner "Xilinx")) + (property USE_PATTERN_DETECT (string "NO_PATDET") (owner "Xilinx")) + (property USE_SIMD (string "ONE48") (owner "Xilinx")) + ) + (instance blk000000fb + (viewRef view_1 (cellRef DSP48E1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "3:INPUT:CARRYINSEL<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:CARRYOUT<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:INPUT:ALUMODE<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "7:INPUT:OPMODE<6:0>") (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:INMODE<4:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:OUTPUT:ACOUT<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:BCOUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:PCOUT<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:PCIN<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:BCIN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:ACIN<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:C<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:B<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "25:INPUT:D<24:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:P<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:A<29:0>") (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property ACASCREG (integer 1) (owner "Xilinx")) + (property ADREG (integer 1) (owner "Xilinx")) + (property ALUMODEREG (integer 0) (owner "Xilinx")) + (property AREG (integer 1) (owner "Xilinx")) + (property AUTORESET_PATDET (string "NO_RESET") (owner "Xilinx")) + (property A_INPUT (string "DIRECT") (owner "Xilinx")) + (property BCASCREG (integer 1) (owner "Xilinx")) + (property BREG (integer 1) (owner "Xilinx")) + (property B_INPUT (string "DIRECT") (owner "Xilinx")) + (property CARRYINREG (integer 1) (owner "Xilinx")) + (property CARRYINSELREG (integer 1) (owner "Xilinx")) + (property CREG (integer 1) (owner "Xilinx")) + (property DREG (integer 1) (owner "Xilinx")) + (property INMODEREG (integer 1) (owner "Xilinx")) + (property MASK (string "FFFFFFFFFFFE") (owner "Xilinx")) + (property MREG (integer 1) (owner "Xilinx")) + (property OPMODEREG (integer 0) (owner "Xilinx")) + (property PATTERN (string "000000000000") (owner "Xilinx")) + (property PREG (integer 1) (owner "Xilinx")) + (property SEL_MASK (string "MASK") (owner "Xilinx")) + (property SEL_PATTERN (string "PATTERN") (owner "Xilinx")) + (property USE_DPORT (string "TRUE") (owner "Xilinx")) + (property USE_MULT (string "MULTIPLY") (owner "Xilinx")) + (property USE_PATTERN_DETECT (string "NO_PATDET") (owner "Xilinx")) + (property USE_SIMD (string "ONE48") (owner "Xilinx")) + ) + (instance blk000000fc + (viewRef view_1 (cellRef DSP48E1 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property BUS_INFO (string "3:INPUT:CARRYINSEL<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:OUTPUT:CARRYOUT<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "4:INPUT:ALUMODE<3:0>") (owner "Xilinx")) + (property BUS_INFO (string "7:INPUT:OPMODE<6:0>") (owner "Xilinx")) + (property BUS_INFO (string "5:INPUT:INMODE<4:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:OUTPUT:ACOUT<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:BCOUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:PCOUT<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:PCIN<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:BCIN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:ACIN<29:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:INPUT:C<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:B<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "25:INPUT:D<24:0>") (owner "Xilinx")) + (property BUS_INFO (string "48:OUTPUT:P<47:0>") (owner "Xilinx")) + (property BUS_INFO (string "30:INPUT:A<29:0>") (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property ACASCREG (integer 1) (owner "Xilinx")) + (property ADREG (integer 1) (owner "Xilinx")) + (property ALUMODEREG (integer 0) (owner "Xilinx")) + (property AREG (integer 1) (owner "Xilinx")) + (property AUTORESET_PATDET (string "NO_RESET") (owner "Xilinx")) + (property A_INPUT (string "DIRECT") (owner "Xilinx")) + (property BCASCREG (integer 1) (owner "Xilinx")) + (property BREG (integer 1) (owner "Xilinx")) + (property B_INPUT (string "DIRECT") (owner "Xilinx")) + (property CARRYINREG (integer 1) (owner "Xilinx")) + (property CARRYINSELREG (integer 1) (owner "Xilinx")) + (property CREG (integer 1) (owner "Xilinx")) + (property DREG (integer 1) (owner "Xilinx")) + (property INMODEREG (integer 1) (owner "Xilinx")) + (property MASK (string "FFFFFFFFFFFE") (owner "Xilinx")) + (property MREG (integer 1) (owner "Xilinx")) + (property OPMODEREG (integer 0) (owner "Xilinx")) + (property PATTERN (string "000000000000") (owner "Xilinx")) + (property PREG (integer 1) (owner "Xilinx")) + (property SEL_MASK (string "MASK") (owner "Xilinx")) + (property SEL_PATTERN (string "PATTERN") (owner "Xilinx")) + (property USE_DPORT (string "TRUE") (owner "Xilinx")) + (property USE_MULT (string "MULTIPLY") (owner "Xilinx")) + (property USE_PATTERN_DETECT (string "NO_PATDET") (owner "Xilinx")) + (property USE_SIMD (string "ONE48") (owner "Xilinx")) + ) + (instance blk000000fd + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000fe + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000000ff + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000100 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000101 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000102 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000103 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000104 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000105 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000106 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000107 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000108 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000109 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000010a + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000010b + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000010c + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000010d + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000010e + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000010f + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000110 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000111 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000112 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000113 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000114 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000115 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000116 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000117 + (viewRef view_1 (cellRef sp_ram_blk00000117 (libraryRef hbdec2_lib))) + (property BUS_INFO (string "2:INPUT:ADDR<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 3) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_blk00000117") (owner "Xilinx")) + ) + (instance blk0000014a + (viewRef view_1 (cellRef sp_ram_NO1_blk0000014a (libraryRef hbdec2_lib))) + (property BUS_INFO (string "2:INPUT:ADDR<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 1) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 4) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO1_blk0000014a") (owner "Xilinx")) + ) + (instance blk0000017d + (viewRef view_1 (cellRef sp_ram_NO2_blk0000017d (libraryRef hbdec2_lib))) + (property BUS_INFO (string "2:INPUT:ADDR<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 2) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 5) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO2_blk0000017d") (owner "Xilinx")) + ) + (instance blk000001b0 + (viewRef view_1 (cellRef sp_ram_NO3_blk000001b0 (libraryRef hbdec2_lib))) + (property BUS_INFO (string "2:INPUT:ADDR<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 3) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 6) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO3_blk000001b0") (owner "Xilinx")) + ) + (instance blk000001e3 + (viewRef view_1 (cellRef sp_ram_NO4_blk000001e3 (libraryRef hbdec2_lib))) + (property BUS_INFO (string "2:INPUT:ADDR<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 4) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 7) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO4_blk000001e3") (owner "Xilinx")) + ) + (instance blk00000216 + (viewRef view_1 (cellRef sp_ram_NO5_blk00000216 (libraryRef hbdec2_lib))) + (property BUS_INFO (string "2:INPUT:ADDR<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 5) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 8) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO5_blk00000216") (owner "Xilinx")) + ) + (instance blk00000249 + (viewRef view_1 (cellRef sp_ram_NO6_blk00000249 (libraryRef hbdec2_lib))) + (property BUS_INFO (string "2:INPUT:ADDR<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 6) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 9) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO6_blk00000249") (owner "Xilinx")) + ) + (instance blk0000027c + (viewRef view_1 (cellRef sp_ram_NO7_blk0000027c (libraryRef hbdec2_lib))) + (property BUS_INFO (string "2:INPUT:ADDR<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 7) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 10) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO7_blk0000027c") (owner "Xilinx")) + ) + (instance blk000002af + (viewRef view_1 (cellRef sp_ram_NO8_blk000002af (libraryRef hbdec2_lib))) + (property BUS_INFO (string "2:INPUT:ADDR<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 8) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 11) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO8_blk000002af") (owner "Xilinx")) + ) + (instance blk000002e2 + (viewRef view_1 (cellRef sp_ram_NO9_blk000002e2 (libraryRef hbdec2_lib))) + (property BUS_INFO (string "2:INPUT:ADDR<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 9) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 12) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO9_blk000002e2") (owner "Xilinx")) + ) + (instance blk00000315 + (viewRef view_1 (cellRef sp_ram_NO10_blk00000315 (libraryRef hbdec2_lib))) + (property BUS_INFO (string "2:INPUT:ADDR<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 10) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 13) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO10_blk00000315") (owner "Xilinx")) + ) + (instance blk00000348 + (viewRef view_1 (cellRef sp_ram_NO11_blk00000348 (libraryRef hbdec2_lib))) + (property BUS_INFO (string "2:INPUT:ADDR<1:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:DATA_IN<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:DATA_OUT<23:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 11) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 14) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "sp_ram_NO11_blk00000348") (owner "Xilinx")) + ) + (instance blk0000037b + (viewRef view_1 (cellRef dpr_ram_2_blk0000037b (libraryRef hbdec2_lib))) + (property BUS_INFO (string "3:INPUT:ADDRA<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:DA_IN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "3:INPUT:ADDRB<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:DA_OUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:DB_OUT<17:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 15) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "dpr_ram_2_blk0000037b") (owner "Xilinx")) + ) + (instance blk000003b4 + (viewRef view_1 (cellRef dpr_ram_3_blk000003b4 (libraryRef hbdec2_lib))) + (property BUS_INFO (string "3:INPUT:ADDRA<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:DA_IN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "3:INPUT:ADDRB<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:DA_OUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:DB_OUT<17:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 16) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "dpr_ram_3_blk000003b4") (owner "Xilinx")) + ) + (instance blk000003ed + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000003ee + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000003ef + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000003f0 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000003f1 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000003f2 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000003f3 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000003f4 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000003f5 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000003f6 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000003f7 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000003f8 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000003f9 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000003fa + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000003fb + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000003fc + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000003fd + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000003fe + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000003ff + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000400 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000401 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000402 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000403 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000404 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000405 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000406 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000407 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000408 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000409 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000040a + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000040b + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000040c + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000040d + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000040e + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000040f + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000410 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000411 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000412 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000413 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000414 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000415 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000416 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000417 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000418 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000419 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000041a + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000041b + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000041c + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000041d + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000041e + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000041f + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000420 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000421 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000422 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000423 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000424 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000425 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000426 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000427 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000428 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000429 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000042a + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000042b + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000042c + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000042d + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000042e + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000042f + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000430 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000431 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000432 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000433 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000434 + (viewRef view_1 (cellRef FDRE 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"Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000043a + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000043b + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000043c + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000043d + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000043e + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000043f + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000440 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000441 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000442 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000443 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000444 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000445 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000446 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000447 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000448 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000449 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000044a + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000044b + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000044c + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000044d + (viewRef view_1 (cellRef dpr_ram_4_blk0000044d (libraryRef hbdec2_lib))) + (property BUS_INFO (string "3:INPUT:ADDRA<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:DA_IN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "3:INPUT:ADDRB<2:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:DA_OUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:DB_OUT<17:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 17) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "dpr_ram_4_blk0000044d") (owner "Xilinx")) + ) + (instance blk00000474 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000475 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000476 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000477 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000478 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000479 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000047a + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000047b + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000047c + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000047d + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000047e + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000047f + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000480 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000481 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000482 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000483 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000484 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000485 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000486 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000487 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000488 + (viewRef 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(true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000048e + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000048f + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000490 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000491 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000492 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000493 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000494 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000495 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000496 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000497 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000498 + (viewRef view_1 (cellRef FDRE (libraryRef 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(property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000049e + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000049f + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004a0 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004a1 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004a2 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004a3 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004a4 + (viewRef view_1 (cellRef dpr_ram_5_blk000004a4 (libraryRef hbdec2_lib))) + (property BUS_INFO (string "1:INPUT:ADDRA<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:INPUT:DA_IN<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "1:INPUT:ADDRB<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:DA_OUT<17:0>") (owner "Xilinx")) + (property BUS_INFO (string "18:OUTPUT:DB_OUT<17:0>") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 18) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "dpr_ram_5_blk000004a4") (owner "Xilinx")) + ) + (instance blk000004cb + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000004cc + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000004cd + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000004ce + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000004cf + (viewRef view_1 (cellRef XORCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000004d0 + (viewRef view_1 (cellRef MUXCY_D (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000004d1 + (viewRef view_1 (cellRef MUXCY_L (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000004d2 + (viewRef view_1 (cellRef MUXCY_L (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000004d3 + (viewRef view_1 (cellRef MUXCY_L (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000004d4 + (viewRef view_1 (cellRef MUXCY_L (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + ) + (instance blk000004d5 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004d6 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004d7 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004d8 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004d9 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004da + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004db + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004dc + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004dd + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004de + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004df + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004e0 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004e1 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004e2 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004e3 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004e4 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004e5 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004e6 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004e7 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004e8 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004e9 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004ea + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004eb + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004ec + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004ed + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004ee + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004ef + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004f0 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004f1 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004f2 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004f3 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004f4 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004f5 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004f6 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004f7 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004f8 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004f9 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004fa + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004fb + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004fc + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004fd + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004fe + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000004ff + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000500 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000501 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000502 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000503 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000504 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000505 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000506 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000507 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000508 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000509 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000050a + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000050b + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000050c + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000050d + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000050e + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000050f + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000510 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000511 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000512 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000513 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000514 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000515 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000516 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000517 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000518 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000519 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000051a + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000051b + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000051c + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000051d + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000051e + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk0000051f + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property OPTIMIZE_PRIMITIVES_NGC (string "no") (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000520 + (viewRef view_1 (cellRef FDRE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property 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(viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006a9 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006aa + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006ab + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006ac + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006ad + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006ae + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006af + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006b0 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006b1 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006b2 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006b3 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006b4 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006b5 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006b6 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006b7 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006b8 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006b9 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006ba + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006bb + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006bc + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006bd + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006be + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006bf + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006c0 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006c1 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006c2 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006c3 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006c4 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006c5 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006c6 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006c7 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006c8 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006c9 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006ca + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006cb + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006cc + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006cd + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006ce + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006cf + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006d0 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006d1 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006d2 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006d3 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006d4 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006d5 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006d6 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006d7 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006d8 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006d9 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006da + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006db + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006dc + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006dd + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006de + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006df + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006e0 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006e1 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006e2 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006e3 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006e4 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006e5 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006e6 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006e7 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006e8 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006e9 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006ea + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006eb + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006ec + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006ed + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006ee + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006ef + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006f0 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006f1 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006f2 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006f3 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006f4 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006f5 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006f6 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006f7 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006f8 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006f9 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006fa + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006fb + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006fc + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006fd + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk000006fe + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk000006ff + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000700 + (viewRef view_1 (cellRef SRLC16E (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0000") (owner "Xilinx")) + ) + (instance blk00000701 + (viewRef view_1 (cellRef FDE (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "0") (owner "Xilinx")) + ) + (instance blk00000702 + (viewRef view_1 (cellRef SRLC16E (libraryRef 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BUS_INFO (string "24:INPUT:din_5<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:din_6<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:din_7<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:din_8<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:din_9<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:din_10<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:din_11<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:din_12<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:din_13<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:din_14<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:din_15<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:INPUT:din_16<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "1:OUTPUT:chan_in<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "1:OUTPUT:chan_out<0:0>") (owner "Xilinx")) + (property BUS_INFO (string "47:OUTPUT:dout<46:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:dout_i<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "47:OUTPUT:dout_q<46:0>") (owner "Xilinx")) + (property BUS_INFO (string "47:OUTPUT:dout_1<46:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:dout_i_1<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "47:OUTPUT:dout_q_1<46:0>") (owner "Xilinx")) + (property BUS_INFO (string "47:OUTPUT:dout_2<46:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:dout_i_2<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "47:OUTPUT:dout_q_2<46:0>") (owner "Xilinx")) + (property BUS_INFO (string "47:OUTPUT:dout_3<46:0>") (owner "Xilinx")) + (property BUS_INFO (string "24:OUTPUT:dout_i_3<23:0>") (owner "Xilinx")) + (property BUS_INFO (string "47:OUTPUT:dout_q_3<46:0>") (owner "Xilinx")) + (property BUS_INFO (string "47:OUTPUT:dout_4<46:0>") (owner "Xilinx")) + (property BUS_INFO (string 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+// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +// 边沿检测子模块 + module edge_detect ( + input wire clk, + input wire rst_n, + input wire din, + output wire dout + ); + reg din_d1, din_d2; + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + din_d1 <= 1'b0; + din_d2 <= 1'b0; + end else begin + din_d1 <= din; + din_d2 <= din_d1; + end + end + assign dout = din_d1 & ~din_d2; // 上升沿 + endmodule + + diff --git a/top/b200/pps_switch.v b/top/b200/pps_switch.v new file mode 100644 index 0000000..a6c235b --- /dev/null +++ b/top/b200/pps_switch.v @@ -0,0 +1,72 @@ +`timescale 1ns / 1ps + +// pps_switch.v +module pps_switch ( + input wire clk, // 系统时钟（≥10 MHz 推荐） + input wire rst_n, // 低电平有效异步复位 + input wire gps_pps, // GPS_PPS 输入 + input wire ext_pps, // EXT_PPS 输入 + output reg pps_out // 最终输出的PPS脉冲 +); + + // 跟踪当前激活的PPS源 + reg active_pps_source; // 0=GPS, 1=EXT + + // 边沿检测：上升沿产生一个时钟周期的高脉冲 + wire gps_posedge; + wire ext_posedge; + + edge_detect u_gps_edge ( + .clk(clk), + .rst_n(rst_n), + .din(gps_pps), + .dout(gps_posedge) + ); + + edge_detect u_ext_edge ( + .clk(clk), + .rst_n(rst_n), + .din(ext_pps), + .dout(ext_posedge) + ); + + // 状态机：0=等待GPS，1=等待EXT + reg [1:0] state; + localparam S_GPS = 2'b00; + localparam S_EXT = 2'b01; + + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + state <= S_GPS; + active_pps_source <= 1'b0; // 默认GPS + end + else begin + case (state) + S_GPS: begin + if (gps_posedge) begin + state <= S_GPS; // 保持GPS优先 + active_pps_source <= 1'b0; // 激活GPS + end else if (ext_posedge) begin + state <= S_GPS; // 仍保持GPS优先，但允许EXT临时补位 + active_pps_source <= 1'b1; // 激活EXT + end + end + default: begin // 简化处理，实际应用中可扩展状态机 + if (ext_posedge) begin + state <= S_GPS; // 回到GPS等待 + active_pps_source <= 1'b1; // 激活EXT + end + end + endcase + end + end + + // 输出逻辑 + always @(posedge clk or negedge rst_n) begin + if (!rst_n) + pps_out <= 1'b0; + else + pps_out <= active_pps_source ? ext_pps : gps_pps; + end + +endmodule \ No newline at end of file diff --git a/vivado/b210_k7/ip/b200_clk_gen/b200_clk_gen.xci b/vivado/b210_k7/ip/b200_clk_gen/b200_clk_gen.xci new file mode 100644 index 0000000..aa790b7 --- /dev/null +++ b/vivado/b210_k7/ip/b200_clk_gen/b200_clk_gen.xci @@ -0,0 +1,705 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "b200_clk_gen", + "component_reference": "xilinx.com:ip:clk_wiz:6.0", + "ip_revision": "14", + "gen_directory": "../../../../B210_Project_Firmwire.gen/sources_1/ip/b200_clk_gen", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "b200_clk_gen", "resolve_type": "user", "usage": "all" } ], + "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": 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"float", "usage": "all" } ], + "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "NUM_OUT_CLKS": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT1_PORT": [ { "value": "CLK_OUT1_40_int", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT2_PORT": [ { "value": "CLK_OUT2_100_gpif", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT3_PORT": [ { "value": "CLK_OUT3_100_bus", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ], + "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ], + "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ], + "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ], + "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ], + "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ], + "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ], + "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ], + "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ], + "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ], + "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ], + "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "40", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIM_SOURCE": [ { "value": "Differential_clock_capable_pin", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ], + "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ], + "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_RESET": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ], + "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ], + "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ], + "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ], + "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ], + "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ], + "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ], + "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ], + "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ], + "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ], + "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], + "MMCM_CLKFBOUT_MULT_F": [ { "value": "25.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKIN1_PERIOD": [ { "value": "25.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ], + "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "25.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT1_DIVIDE": [ { "value": "10", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT2_DIVIDE": [ { "value": "10", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], + "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ], + "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ], + "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ], + "USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": 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at end of file