44 lines
998 B
Verilog
44 lines
998 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2025/07/03 01:29:39
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// Design Name:
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// Module Name: edge_detect
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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// 边沿检测子模块
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module edge_detect (
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input wire clk,
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input wire rst_n,
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input wire din,
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output wire dout
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);
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reg din_d1, din_d2;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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din_d1 <= 1'b0;
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din_d2 <= 1'b0;
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end else begin
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din_d1 <= din;
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din_d2 <= din_d1;
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end
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end
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assign dout = din_d1 & ~din_d2; // 上升沿
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endmodule
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