miegl/b210-k7-fpga
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miegl 3dc3446559 b200: import original Kintex-7 clone port
2026-08-23 11:42:22 +02:00
..
coregen
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
coregen_dsp
b200: import original Kintex-7 clone port
2026-08-23 11:42:22 +02:00
planahead
fpga: Shorten line length for Launchpad linter
2021-10-28 13:57:54 -07:00
sim
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
.gitignore
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
b200_core.v
b200: import original Kintex-7 clone port
2026-08-23 11:42:22 +02:00
b200_io.v
b200: import original Kintex-7 clone port
2026-08-23 11:42:22 +02:00
b200.ucf
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
b200.v
b200: import original Kintex-7 clone port
2026-08-23 11:42:22 +02:00
b210.xdc
b200: import original Kintex-7 clone port
2026-08-23 11:42:22 +02:00
check.sh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
core_compile
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Define.vh
b200: import original Kintex-7 clone port
2026-08-23 11:42:22 +02:00
edge_detect.v
b200: import original Kintex-7 clone port
2026-08-23 11:42:22 +02:00
gpio.ucf
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile
fpga: b2xx: Generate utilization report files
2022-02-10 11:35:47 -07:00
Makefile.b200.inc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
pps_switch.v
b200: import original Kintex-7 clone port
2026-08-23 11:42:22 +02:00
S6CLK2PIN.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
timing.ucf
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00