fpga: rfnoc: Add Signal Generator RFNoC block
Original-commit: 1e94f85b8bafc3f9acab7ef35d2675fa7e61f6f4
This commit is contained in:
Wade Fife
committed by
Aaron Rossetto
Aaron Rossetto
parent
3e1e0be3bc
commit
2eb71626fb
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//
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// Copyright 2020 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: rfnoc_block_siggen
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//
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// Description:
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//
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// Signal generator RFNoC block. This block outputs packets of one of three
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// output types based on the REG_WAVEFORM register setting. Supported modes
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// include constant, sinusoidal, and noise/random. The output is also run
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// through a gain stage that is configurable using the REG_GAIN register.
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// See the register descriptions in rfnoc_block_siggen_regs.vh for details.
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//
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// The sine output is based on the Xilinx CORDIC IP, configured for the
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// rotate function, with scaled radians as the units. See the CORDIC user
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// guide (PG105) and register descriptions for details.
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//
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// Parameters:
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//
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// THIS_PORTID : Control crossbar port to which this block is connected
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// CHDR_W : AXIS-CHDR data bus width
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// MTU : Maximum transmission unit (i.e., maximum packet size in
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// CHDR words is 2**MTU).
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// NUM_PORTS : Number of siggen cores to instantiate.
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//
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`default_nettype none
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module rfnoc_block_siggen #(
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parameter [9:0] THIS_PORTID = 10 'd0,
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parameter CHDR_W = 64,
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parameter [5:0] MTU = 10,
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parameter NUM_PORTS = 1
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) (
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// RFNoC Framework Clocks and Resets
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input wire rfnoc_chdr_clk,
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input wire rfnoc_ctrl_clk,
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input wire ce_clk,
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// RFNoC Backend Interface
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input wire [ 511:0] rfnoc_core_config,
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output wire [ 511:0] rfnoc_core_status,
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// AXIS-CHDR Input Ports (from framework)
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input wire [ CHDR_W-1:0] s_rfnoc_chdr_tdata,
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input wire s_rfnoc_chdr_tlast,
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input wire s_rfnoc_chdr_tvalid,
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output wire s_rfnoc_chdr_tready,
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// AXIS-CHDR Output Ports (to framework)
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output wire [NUM_PORTS*CHDR_W-1:0] m_rfnoc_chdr_tdata,
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output wire [ NUM_PORTS-1:0] m_rfnoc_chdr_tlast,
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output wire [ NUM_PORTS-1:0] m_rfnoc_chdr_tvalid,
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input wire [ NUM_PORTS-1:0] m_rfnoc_chdr_tready,
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// AXIS-Ctrl Input Port (from framework)
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input wire [ 31:0] s_rfnoc_ctrl_tdata,
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input wire s_rfnoc_ctrl_tlast,
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input wire s_rfnoc_ctrl_tvalid,
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output wire s_rfnoc_ctrl_tready,
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// AXIS-Ctrl Output Port (to framework)
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output wire [ 31:0] m_rfnoc_ctrl_tdata,
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output wire m_rfnoc_ctrl_tlast,
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output wire m_rfnoc_ctrl_tvalid,
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input wire m_rfnoc_ctrl_tready
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);
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`include "rfnoc_block_siggen_regs.vh"
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//---------------------------------------------------------------------------
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// Signal Declarations
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//---------------------------------------------------------------------------
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// CtrlPort Master
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wire m_ctrlport_req_wr;
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wire m_ctrlport_req_rd;
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wire [19:0] m_ctrlport_req_addr;
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wire [31:0] m_ctrlport_req_data;
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wire m_ctrlport_resp_ack;
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wire [31:0] m_ctrlport_resp_data;
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// Data Stream to User Logic: out
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wire [NUM_PORTS*32*1-1:0] s_out_axis_tdata;
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wire [ NUM_PORTS-1:0] s_out_axis_tlast;
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wire [ NUM_PORTS-1:0] s_out_axis_tvalid;
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wire [ NUM_PORTS-1:0] s_out_axis_tready;
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wire [ NUM_PORTS*16-1:0] s_out_axis_tlength;
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//---------------------------------------------------------------------------
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// NoC Shell
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//---------------------------------------------------------------------------
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wire ce_rst;
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noc_shell_siggen #(
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.CHDR_W (CHDR_W),
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.THIS_PORTID (THIS_PORTID),
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.MTU (MTU),
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.NUM_PORTS (NUM_PORTS)
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) noc_shell_siggen_i (
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//---------------------
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// Framework Interface
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//---------------------
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// Clock Inputs
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.rfnoc_chdr_clk (rfnoc_chdr_clk),
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.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
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.ce_clk (ce_clk),
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// Reset Outputs
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.rfnoc_chdr_rst (),
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.rfnoc_ctrl_rst (),
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.ce_rst (ce_rst),
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// RFNoC Backend Interface
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.rfnoc_core_config (rfnoc_core_config),
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.rfnoc_core_status (rfnoc_core_status),
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// CHDR Input Ports (from framework)
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.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata),
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.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast),
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.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
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.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
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// CHDR Output Ports (to framework)
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.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata),
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.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast),
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.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
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.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
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// AXIS-Ctrl Input Port (from framework)
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.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
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.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
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.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
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.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
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// AXIS-Ctrl Output Port (to framework)
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.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
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.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
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.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
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.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
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//---------------------
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// Client Interface
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//---------------------
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// CtrlPort Clock and Reset
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.ctrlport_clk (),
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.ctrlport_rst (),
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// CtrlPort Master
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.m_ctrlport_req_wr (m_ctrlport_req_wr),
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.m_ctrlport_req_rd (m_ctrlport_req_rd),
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.m_ctrlport_req_addr (m_ctrlport_req_addr),
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.m_ctrlport_req_data (m_ctrlport_req_data),
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.m_ctrlport_resp_ack (m_ctrlport_resp_ack),
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.m_ctrlport_resp_data (m_ctrlport_resp_data),
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// AXI-Stream Clock and Reset
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.axis_data_clk (),
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.axis_data_rst (),
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// Data Stream from User Logic: out
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.s_out_axis_tdata (s_out_axis_tdata),
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.s_out_axis_tkeep ({NUM_PORTS{1'b1}}),
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.s_out_axis_tlast (s_out_axis_tlast),
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.s_out_axis_tvalid (s_out_axis_tvalid),
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.s_out_axis_tready (s_out_axis_tready),
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.s_out_axis_ttimestamp ({NUM_PORTS{64'b0}}),
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.s_out_axis_thas_time ({NUM_PORTS{1'b0}}),
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.s_out_axis_tlength (s_out_axis_tlength),
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.s_out_axis_teov ({NUM_PORTS{1'b0}}),
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.s_out_axis_teob ({NUM_PORTS{1'b0}})
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);
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//---------------------------------------------------------------------------
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// CtrlPort Splitter
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//---------------------------------------------------------------------------
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// Create a CtrlPort bus for each port instance
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wire [ 1*NUM_PORTS-1:0] ctrlport_req_wr;
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wire [ 1*NUM_PORTS-1:0] ctrlport_req_rd;
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wire [20*NUM_PORTS-1:0] ctrlport_req_addr;
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wire [32*NUM_PORTS-1:0] ctrlport_req_data;
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wire [ 1*NUM_PORTS-1:0] ctrlport_resp_ack;
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wire [32*NUM_PORTS-1:0] ctrlport_resp_data;
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ctrlport_decoder #(
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.NUM_SLAVES (NUM_PORTS),
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.BASE_ADDR (0),
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.SLAVE_ADDR_W (SIGGEN_ADDR_W)
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) ctrlport_decoder_i (
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.ctrlport_clk (ce_clk),
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.ctrlport_rst (ce_rst),
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.s_ctrlport_req_wr (m_ctrlport_req_wr),
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.s_ctrlport_req_rd (m_ctrlport_req_rd),
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.s_ctrlport_req_addr (m_ctrlport_req_addr),
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.s_ctrlport_req_data (m_ctrlport_req_data),
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.s_ctrlport_req_byte_en (4'hF),
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.s_ctrlport_req_has_time (1'b0),
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.s_ctrlport_req_time (64'b0),
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.s_ctrlport_resp_ack (m_ctrlport_resp_ack),
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.s_ctrlport_resp_status (),
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.s_ctrlport_resp_data (m_ctrlport_resp_data),
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.m_ctrlport_req_wr (ctrlport_req_wr),
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.m_ctrlport_req_rd (ctrlport_req_rd),
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.m_ctrlport_req_addr (ctrlport_req_addr),
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.m_ctrlport_req_data (ctrlport_req_data),
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.m_ctrlport_req_byte_en (),
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.m_ctrlport_req_has_time (),
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.m_ctrlport_req_time (),
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.m_ctrlport_resp_ack (ctrlport_resp_ack),
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.m_ctrlport_resp_status ({NUM_PORTS{2'b0}}),
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.m_ctrlport_resp_data (ctrlport_resp_data)
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);
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//---------------------------------------------------------------------------
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// Port Instances
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//---------------------------------------------------------------------------
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genvar port;
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generate
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for (port = 0; port < NUM_PORTS; port = port+1) begin : gen_ports
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rfnoc_siggen_core rfnoc_siggen_core_i (
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.clk (ce_clk),
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.rst (ce_rst),
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.s_ctrlport_req_wr (ctrlport_req_wr [port* 1 +: 1]),
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.s_ctrlport_req_rd (ctrlport_req_rd [port* 1 +: 1]),
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.s_ctrlport_req_addr (ctrlport_req_addr [port*20 +: 20]),
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.s_ctrlport_req_data (ctrlport_req_data [port*32 +: 32]),
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.s_ctrlport_resp_ack (ctrlport_resp_ack [port* 1 +: 1]),
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.s_ctrlport_resp_data (ctrlport_resp_data [port*32 +: 32]),
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.m_tdata (s_out_axis_tdata [port*32 +: 32]),
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.m_tlast (s_out_axis_tlast [port* 1 +: 1]),
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.m_tvalid (s_out_axis_tvalid [port* 1 +: 1]),
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.m_tready (s_out_axis_tready [port* 1 +: 1]),
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.m_tlength (s_out_axis_tlength [port*16 +: 16])
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);
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end
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endgenerate
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endmodule // rfnoc_block_siggen
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`default_nettype wire
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