b2xx: Updating FPGA source with recent bugfixes.

Original-commit: 4b4365a517938b365af57674a3ab1462432c2c3a
2013-12-03 10:35:35 -08:00
parent c91b74de33
commit 29086f9001
103 changed files with 2001 additions and 608 deletions
@@ -1,10 +1,9 @@
 SET busformat = BusFormatAngleBracketNotRipped
 SET designentry = Verilog
-SET device = xc6slx75
+SET device = xc6slx150
 SET devicefamily = spartan6
 SET flowvendor = Foundation_ISE
 SET package = fgg484
 SET speedgrade = -3
 SET verilogsim = true
 SET vhdlsim = false
-