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b2xx: Updating FPGA source with recent bugfixes.

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Original-commit: 4b4365a517938b365af57674a3ab1462432c2c3a
This commit is contained in:
Ben Hilburn
2013-12-03 10:35:35 -08:00
parent c91b74de33
commit 29086f9001
103 changed files with 2001 additions and 608 deletions
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top/b200/coregen/chipscope_icon.asy
-4
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@@ -6,8 +6,4 @@ LINE Wide 576 112 544 112
PIN 576 112 RIGHT 36
PINATTR PinName control0[35:0]
PINATTR Polarity BOTH
LINE Wide 576 144 544 144
PIN 576 144 RIGHT 36
PINATTR PinName control1[35:0]
PINATTR Polarity BOTH
top/b200/coregen/chipscope_icon.ngc
+1 -1
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File diff suppressed because one or more lines are too long
top/b200/coregen/chipscope_icon.v
+2 -4
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@@ -8,7 +8,7 @@
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : chipscope_icon.v
// /___/ /\ Timestamp : Fri Mar 08 11:51:37 PST 2013
// /___/ /\ Timestamp : Tue Oct 22 17:04:59 PDT 2013
// \ \ / \
// \___\/\___\
//
@@ -19,11 +19,9 @@
`timescale 1ns/1ps
module chipscope_icon(
CONTROL0,
CONTROL1) /* synthesis syn_black_box syn_noprune=1 */;
CONTROL0) /* synthesis syn_black_box syn_noprune=1 */;
inout [35 : 0] CONTROL0;
inout [35 : 0] CONTROL1;
endmodule
top/b200/coregen/chipscope_icon.veo
+2 -3
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@@ -8,7 +8,7 @@
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : chipscope_icon.veo
// /___/ /\ Timestamp : Fri Mar 08 11:51:37 PST 2013
// /___/ /\ Timestamp : Tue Oct 22 17:05:00 PDT 2013
// \ \ / \
// \___\/\___\
//
@@ -21,8 +21,7 @@
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
chipscope_icon YourInstanceName (
.CONTROL0(CONTROL0), // INOUT BUS [35:0]
.CONTROL1(CONTROL1) // INOUT BUS [35:0]
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
top/b200/coregen/chipscope_icon.xco
+4 -4
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@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Fri Mar 8 19:51:09 2013
# Date: Wed Oct 23 00:04:31 2013
#
##############################################################
#
@@ -30,7 +30,7 @@ SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET simulationfiles = Structural
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = false
@@ -43,7 +43,7 @@ CSET component_name=chipscope_icon
CSET constraint_type=external
CSET enable_jtag_bufg=true
CSET example_design=false
CSET number_control_ports=2
CSET number_control_ports=1
CSET use_ext_bscan=false
CSET use_softbscan=false
CSET use_unused_bscan=false
@@ -53,4 +53,4 @@ CSET user_scan_chain=USER1
MISC pkg_timestamp=2012-12-18T02:47:25Z
# END Extra information
GENERATE
# CRC: 865957ec
# CRC: 5ccf4baf
top/b200/coregen/chipscope_icon.xise
+2 -2
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@@ -51,8 +51,8 @@
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="chipscope_icon" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-03-08T11:51:40" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BD46AAD29AD5653980780005171DAA9E" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-10-22T17:05:01" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="154D57BA825522169EAB357B0FF9F497" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
top/b200/coregen/chipscope_icon_readme.txt
+1 -1
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@@ -1,5 +1,5 @@
The following files were generated for 'chipscope_icon' in directory
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b200/coregen/
/home/ianb/fpgadev/usrp3/top/b200/coregen/
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
top/b200/coregen/chipscope_ila_128.cdc
+1 -1
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@@ -1,5 +1,5 @@
#ChipScope Core Generator Project File Version 3.0
#Fri Mar 08 11:53:53 PST 2013
#Tue Oct 22 15:45:46 PDT 2013
SignalExport.bus<0000>.channelList=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
SignalExport.bus<0000>.name=TRIG0
SignalExport.bus<0000>.offset=0.0
top/b200/coregen/chipscope_ila_128.ngc
+1 -1
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File diff suppressed because one or more lines are too long
top/b200/coregen/chipscope_ila_128.v
+1 -1
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@@ -8,7 +8,7 @@
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : chipscope_ila_128.v
// /___/ /\ Timestamp : Fri Mar 08 11:53:53 PST 2013
// /___/ /\ Timestamp : Tue Oct 22 15:45:46 PDT 2013
// \ \ / \
// \___\/\___\
//
top/b200/coregen/chipscope_ila_128.veo
+1 -1
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@@ -8,7 +8,7 @@
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : chipscope_ila_128.veo
// /___/ /\ Timestamp : Fri Mar 08 11:53:53 PST 2013
// /___/ /\ Timestamp : Tue Oct 22 15:45:46 PDT 2013
// \ \ / \
// \___\/\___\
//
top/b200/coregen/chipscope_ila_128.xco
+4 -4
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@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Fri Mar 8 19:52:17 2013
# Date: Tue Oct 22 22:44:09 2013
#
##############################################################
#
@@ -30,7 +30,7 @@ SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET simulationfiles = Structural
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = false
@@ -112,7 +112,7 @@ CSET match_units_6=1
CSET match_units_7=1
CSET match_units_8=1
CSET match_units_9=1
CSET max_sequence_levels=1
CSET max_sequence_levels=2
CSET number_of_trigger_ports=1
CSET sample_data_depth=1024
CSET sample_on=Rising
@@ -138,4 +138,4 @@ CSET use_rpms=false
MISC pkg_timestamp=2012-12-18T02:47:40Z
# END Extra information
GENERATE
# CRC: 194c140a
# CRC: e17f8549
top/b200/coregen/chipscope_ila_128.xise
+4 -4
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@@ -17,11 +17,11 @@
<files>
<file xil_pn:name="chipscope_ila_128.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="chipscope_ila_128.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
@@ -51,8 +51,8 @@
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="chipscope_ila_128" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-03-08T11:53:54" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="9340B6BAD141C451B74411D3998AD5A4" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-10-22T15:45:48" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="7648BEB3D1E056005214224EBE9A99B3" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
top/b200/coregen/chipscope_ila_128_readme.txt
+1 -1
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@@ -1,5 +1,5 @@
The following files were generated for 'chipscope_ila_128' in directory
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b200/coregen/
/home/ianb/fpgadev/usrp3/top/b200/coregen/
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
top/b200/coregen/coregen.cgp
+1 -2
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@@ -1,10 +1,9 @@
SET busformat = BusFormatAngleBracketNotRipped
SET designentry = Verilog
SET device = xc6slx75
SET device = xc6slx150
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET package = fgg484
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = false