b2xx: Updating FPGA source with recent bugfixes.
Original-commit: 4b4365a517938b365af57674a3ab1462432c2c3a
This commit is contained in:
Ben Hilburn committed
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103 files changed
+2001
-608
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+35
-37
@@ -1,7 +1,19 @@
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//
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// Copyright 2013 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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/***********************************************************
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* B200 Module Declaration
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@@ -23,8 +35,8 @@ module b200 (
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output pll_sclk,
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// UART
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input FPGA_RXD0,
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input FPGA_TXD0,
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input FPGA_RXD0, // These pins goto 3 pin 0.1" header on B2x0 and
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output FPGA_TXD0, // carry FX3 UART.
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// Catalina Controls
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output codec_enable,
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@@ -63,8 +75,8 @@ module b200 (
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output GPIF_CTL7, // n_pktend
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input GPIF_CTL4, // slfifo_flags[0]
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input GPIF_CTL5, // slfifo_flags[1]
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input GPIF_CTL6, // slfifo_flags[2]
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input GPIF_CTL8, // slfifo_flags[3]
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input GPIF_CTL6, // Serial settings bus from FX3. SDA
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input GPIF_CTL8, // Serial settings bus from FX3. SCL
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output GPIF_CTL11, // slfifo_addr[1]
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output GPIF_CTL12, // slfifo_addr[0]
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inout [31:0] GPIF_D,
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@@ -122,10 +134,14 @@ module b200 (
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b200_clk_gen gen_clks
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(
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.CLK_IN1_40_P(codec_main_clk_p), .CLK_IN1_40_N(codec_main_clk_n),
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.CLK_OUT1_40_int(), .CLK_OUT2_100_gpif(gpif_clk), .CLK_OUT3_100_bus(bus_clk),
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.CLK_OUT1_40_int(), .CLK_OUT2_100_gpif(gpif_clk), .CLK_OUT3_100_bus(),
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.RESET(reset_global), .LOCKED(locked)
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);
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// Bus Clock and GPIF Clock both same 100MHz clock.
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assign bus_clk = gpif_clk;
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//hold-off logic for clocks ready
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reg [15:0] clocks_ready_count;
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reg clocks_ready;
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@@ -193,32 +209,10 @@ module b200 (
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wire ctrl_tvalid, resp_tvalid, rx_tvalid, tx_tvalid;
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wire ctrl_tready, resp_tready, rx_tready, tx_tready;
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///////////////////////////////////////////////////////////////////////
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// loopback testers
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///////////////////////////////////////////////////////////////////////
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/*
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axi_fifo #(.WIDTH(65), .SIZE(13)) f0
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(
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.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
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.i_tdata({ctrl_tlast, ctrl_tdata}), .i_tvalid(ctrl_tvalid), .i_tready(ctrl_tready), .space(),
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.o_tdata({resp_tlast, resp_tdata}), .o_tvalid(resp_tvalid), .o_tready(resp_tready), .occupied()
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);
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//*/
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/*
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axi_fifo #(.WIDTH(65), .SIZE(13)) f1
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(
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.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
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.i_tdata({tx_tlast, tx_tdata}), .i_tvalid(tx_tvalid), .i_tready(tx_tready), .space(),
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.o_tdata({rx_tlast, rx_tdata}), .o_tvalid(rx_tvalid), .o_tready(rx_tready), .occupied()
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);
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//*/
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///////////////////////////////////////////////////////////////////////
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// frontend assignments
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///////////////////////////////////////////////////////////////////////
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wire [31:0] debug_radio;
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wire [31:0] fe_atr1, fe_atr2;
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assign {tx_enable1, SFDX1_RX, SFDX1_TX, SRX1_RX, SRX1_TX, LED_RX1, LED_TXRX1_RX, LED_TXRX1_TX} = fe_atr1[7:0];
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assign {tx_enable2, SFDX2_RX, SFDX2_TX, SRX2_RX, SRX2_TX, LED_RX2, LED_TXRX2_RX, LED_TXRX2_TX} = fe_atr2[7:0];
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@@ -237,7 +231,8 @@ module b200 (
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///////////////////////////////////////////////////////////////////////
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// b200 core
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///////////////////////////////////////////////////////////////////////
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b200_core #(.EXTRA_BUFF_SIZE(12)) b200_xfusion_core
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b200_core #(.EXTRA_BUFF_SIZE(12)) b200_core
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(
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.bus_clk(bus_clk), .bus_rst(bus_rst),
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.tx_tdata(tx_tdata), .tx_tlast(tx_tlast), .tx_tvalid(tx_tvalid), .tx_tready(tx_tready),
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@@ -253,15 +248,19 @@ module b200 (
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.rxd(gps_txd), .txd(gps_rxd),
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.sclk(sclk), .sen(sen), .mosi(mosi), .miso(miso),
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.rb_misc({31'b0, pll_lock}), .misc_outs(misc_outs)
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.rb_misc({31'b0, pll_lock}), .misc_outs(misc_outs),
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.debug_scl(GPIF_CTL8), .debug_sda(GPIF_CTL6),
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.debug_txd(FPGA_TXD0), .debug_rxd(FPGA_RXD0),
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.debug()
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);
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///////////////////////////////////////////////////////////////////////
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// GPIF2
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///////////////////////////////////////////////////////////////////////
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wire [31:0] debug_gpif;
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gpif2_slave_fifo32 #(.DATA_RX_FIFO_SIZE(14), .DATA_TX_FIFO_SIZE(14)) slave_fifo32
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gpif2_slave_fifo32 #(.DATA_RX_FIFO_SIZE(14), .DATA_TX_FIFO_SIZE(14)) slave_fifo32
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(
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.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), .gpif_enb(1'b1),
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.gpif_ctl({GPIF_CTL8, GPIF_CTL6, GPIF_CTL5, GPIF_CTL4}), .fifoadr({GPIF_CTL11,GPIF_CTL12}),
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@@ -274,13 +273,12 @@ module b200 (
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.ctrl_tdata(ctrl_tdata), .ctrl_tlast(ctrl_tlast), .ctrl_tvalid(ctrl_tvalid), .ctrl_tready(ctrl_tready),
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.resp_tdata(resp_tdata), .resp_tlast(resp_tlast), .resp_tvalid(resp_tvalid), .resp_tready(resp_tready),
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.debug(debug_gpif)
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.debug()
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);
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///////////////////////////////////////////////////////////////////////
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// Debug port
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///////////////////////////////////////////////////////////////////////
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assign debug_clk_int = { 1'b0, 1'b0 };
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assign debug = 32'b0;
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assign debug = 0;
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endmodule // B200
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+75
-11
@@ -1,7 +1,19 @@
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//
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// Copyright 2013 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
|
||||
//
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// You should have received a copy of the GNU General Public License
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||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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/***********************************************************
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* B200 Core Guts
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@@ -15,7 +27,10 @@ module b200_core
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parameter R0_DATA_SID = 8'h50,
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parameter R1_DATA_SID = 8'h60,
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parameter DEMUX_SID_MASK = 8'hf0,
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parameter EXTRA_BUFF_SIZE = 0
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parameter EXTRA_BUFF_SIZE = 0,
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parameter RADIO_FIFO_SIZE = 12,
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parameter SAMPLE_FIFO_SIZE = 11
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)
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(
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////////////////////////////////////////////////////////////////////
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@@ -53,8 +68,15 @@ module b200_core
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output [7:0] sen, output sclk, output mosi, input miso,
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input [31:0] rb_misc,
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output [31:0] misc_outs,
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output [31:0] debug
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////////////////////////////////////////////////////////////////////
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// debug UART
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////////////////////////////////////////////////////////////////////
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output debug_txd, input debug_rxd,
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input debug_scl, input debug_sda,
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////////////////////////////////////////////////////////////////////
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// debug signals
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////////////////////////////////////////////////////////////////////
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output [63:0] debug
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);
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localparam SR_CORE_SPI = 8'd8;
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localparam SR_CORE_MISC = 8'd16;
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@@ -62,7 +84,7 @@ module b200_core
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localparam SR_CORE_READBACK = 8'd32;
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localparam SR_CORE_GPSDO_ST = 8'd40;
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localparam SR_CORE_PPS_SEL = 8'd48;
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localparam COMPAT_MAJOR = 16'h0002;
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localparam COMPAT_MAJOR = 16'h0003;
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localparam COMPAT_MINOR = 16'h0000;
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/*******************************************************************
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@@ -119,14 +141,14 @@ module b200_core
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******************************************************************/
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wire [63:0] u0i_ctrl_tdata; wire u0i_ctrl_tlast, u0i_ctrl_tvalid, u0i_ctrl_tready;
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axi_fifo #(.WIDTH(65), .SIZE(0)) ushart_timing_fifo
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axi_fifo #(.WIDTH(65), .SIZE(0)) uart_timing_fifo
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(
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.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
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.i_tdata({u0_ctrl_tlast, u0_ctrl_tdata}), .i_tvalid(u0_ctrl_tvalid), .i_tready(u0_ctrl_tready), .space(),
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.o_tdata({u0i_ctrl_tlast, u0i_ctrl_tdata}), .o_tvalid(u0i_ctrl_tvalid), .o_tready(u0i_ctrl_tready), .occupied()
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);
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cvita_uart #(.SIZE(7)) ushart
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cvita_uart #(.SIZE(7)) uart
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(
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.clk(bus_clk), .rst(bus_rst), .rxd(rxd), .txd(txd),
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.i_tdata(u0i_ctrl_tdata), .i_tlast(u0i_ctrl_tlast), .i_tvalid(u0i_ctrl_tvalid), .i_tready(u0i_ctrl_tready),
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@@ -247,7 +269,9 @@ module b200_core
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/*******************************************************************
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* Radio 0
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******************************************************************/
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radio_b200 #(.FIFO_SIZE(13)) the_radio
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wire [63:0] radio0_debug;
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radio_b200 #(.RADIO_FIFO_SIZE(RADIO_FIFO_SIZE),.SAMPLE_FIFO_SIZE(SAMPLE_FIFO_SIZE)) radio_0
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(
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.radio_clk(radio_clk), .radio_rst(radio_rst),
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.rx(rx0), .tx(tx0), .fe_atr(fe_atr0), .pps(pps),
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@@ -258,7 +282,7 @@ module b200_core
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.ctrl_tdata(r0_ctrl_tdata), .ctrl_tlast(r0_ctrl_tlast), .ctrl_tvalid(r0_ctrl_tvalid), .ctrl_tready(r0_ctrl_tready),
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.resp_tdata(r0_resp_tdata), .resp_tlast(r0_resp_tlast), .resp_tvalid(r0_resp_tvalid), .resp_tready(r0_resp_tready),
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.debug()
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.debug(radio0_debug)
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);
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/*******************************************************************
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@@ -267,7 +291,7 @@ module b200_core
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`ifdef B200_CAN_HAZ_R1
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assign radio_st = 8'h2;
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radio_b200 #(.FIFO_SIZE(13)) the_radio_1
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radio_b200 #(.RADIO_FIFO_SIZE(RADIO_FIFO_SIZE),.SAMPLE_FIFO_SIZE(SAMPLE_FIFO_SIZE)) radio_1
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(
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.radio_clk(radio_clk), .radio_rst(radio_rst),
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.rx(rx1), .tx(tx1), .fe_atr(fe_atr1), .pps(pps),
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@@ -300,6 +324,46 @@ module b200_core
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assign r1_rx_tvalid = r1_tx_tvalid;
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assign r1_tx_tready = r1_tx_tready;
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`endif
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`endif // !`ifdef B200_CAN_HAZ_R1
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/*******************************************************************
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* Debug UART for FX3
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******************************************************************/
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wire debug_stb;
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wire [31:0] debug_data;
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wire [7:0] debug_addr;
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serial_to_settings serial_to_settings_i1
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(
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.clk(bus_clk),
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.reset(bus_rst),
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.scl(debug_scl),
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.sda(debug_sda),
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.set_stb(debug_stb),
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.set_addr(debug_addr),
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.set_data(debug_data)
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);
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simple_uart debug_uart
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(
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.clk_i(bus_clk),
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.rst_i(bus_rst),
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.we_i(debug_stb),
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.stb_i(debug_stb),
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.cyc_i(debug_stb),
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.ack_o(),
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.adr_i(debug_addr[2:0]),
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.dat_i(debug_data[31:0]),
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.dat_o(),
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.rx_int_o(),
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.tx_int_o(),
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.tx_o(debug_txd),
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.rx_i(debug_rxd),
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.baud_o()
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);
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endmodule // b200_core
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@@ -0,0 +1,213 @@
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module b200_tb ();
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wire cat_ce;
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wire cat_miso;
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wire cat_mosi;
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wire cat_sclk;
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wire fx3_ce;
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wire fx3_miso;
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wire fx3_mosi;
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wire fx3_sclk;
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wire pll_ce;
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wire pll_mosi;
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wire pll_sclk;
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// UART
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wire FPGA_RXD0;
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wire FPGA_TXD0;
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// Catalina Controls
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wire codec_enable;
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wire codec_en_agc;
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wire codec_reset;
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wire codec_sync;
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wire codec_txrx;
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wire [3:0] codec_ctrl_in; // These should be outputs
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wire [7:0] codec_ctrl_out; // MUST BE INPUT
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// Catalina Data
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wire codec_data_clk_p; // Clock from CAT (RX)
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wire codec_fb_clk_p; // Clock to CAT (TX)
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wire [11:0] rx_codec_d;
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wire [11:0] tx_codec_d;
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wire rx_frame_p;
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wire tx_frame_p;
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wire cat_clkout_fpga;
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//always on 40MHz clock
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wire codec_main_clk_p;
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wire codec_main_clk_n;
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// Debug Bus
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wire [31:0] debug;
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wire [1:0] debug_clk;
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// GPIF; FX3 Slave FIFO
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wire IFCLK; // pclk
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wire FX3_EXTINT;
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wire GPIF_CTL0; // n_slcs
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wire GPIF_CTL1; // n_slwr
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wire GPIF_CTL2; // n_sloe
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wire GPIF_CTL3; // n_slrd
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wire GPIF_CTL7; // n_pktend
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wire GPIF_CTL4; // slfifo_flags[0]
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wire GPIF_CTL5; // slfifo_flags[1]
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wire GPIF_CTL6; // slfifo_flags[2]
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wire GPIF_CTL8; // slfifo_flags[3]
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wire GPIF_CTL11; // slfifo_addr[1]
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wire GPIF_CTL12; // slfifo_addr[0]
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wire [31:0] GPIF_D;
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wire GPIF_CTL9; // global_reset
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// GPS
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wire gps_lock;
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wire gps_rxd;
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wire gps_txd;
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wire gps_txd_nmea;
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// LEDS
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wire LED_RX1;
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wire LED_RX2;
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wire LED_TXRX1_RX;
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wire LED_TXRX1_TX;
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wire LED_TXRX2_RX;
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wire LED_TXRX2_TX;
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// Misc Hardware Control
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wire ref_sel;
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wire pll_lock;
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wire FPGA_CFG_CS; // Driven by FX3 gpio.
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wire AUX_PWR_ON; // Driven by FX3 gpio.
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// PPS
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wire PPS_IN_EXT;
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wire PPS_IN_INT;
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// RF Hardware Control
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wire SFDX1_RX;
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wire SFDX1_TX;
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wire SFDX2_RX;
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wire SFDX2_TX;
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wire SRX1_RX;
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wire SRX1_TX;
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wire SRX2_RX;
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wire SRX2_TX;
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wire tx_bandsel_a;
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wire tx_bandsel_b;
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wire tx_enable1;
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wire tx_enable2;
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wire rx_bandsel_a;
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wire rx_bandsel_b;
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wire rx_bandsel_c;
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b200 b200_i1(
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// SPI Interfaces
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.cat_ce(),
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.cat_miso(),
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.cat_mosi(),
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.cat_sclk(),
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.fx3_ce(),
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.fx3_miso(),
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.fx3_mosi(),
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.fx3_sclk(),
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.pll_ce(),
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.pll_mosi(),
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.pll_sclk(),
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// UART
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.FPGA_RXD0(),
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.FPGA_TXD0(),
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// Catalina Controls
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.codec_enable(),
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.codec_en_agc(),
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.codec_reset(),
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.codec_sync(),
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.codec_txrx(),
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.codec_ctrl_in(), // These should be outputs
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.codec_ctrl_out(), // MUST BE INPUT
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// Catalina Data
|
||||
.codec_data_clk_p(), // Clock from CAT (RX)
|
||||
.codec_fb_clk_p(), // Clock to CAT (TX)
|
||||
.rx_codec_d(),
|
||||
.tx_codec_d(),
|
||||
.rx_frame_p(),
|
||||
.tx_frame_p(),
|
||||
|
||||
.cat_clkout_fpga(),
|
||||
|
||||
//always on 40MHz clock
|
||||
.codec_main_clk_p(),
|
||||
.codec_main_clk_n(),
|
||||
|
||||
// Debug Bus
|
||||
.debug(),
|
||||
.debug_clk(),
|
||||
|
||||
// GPIF, FX3 Slave FIFO
|
||||
.IFCLK(), // pclk
|
||||
.FX3_EXTINT(),
|
||||
.GPIF_CTL0(), // n_slcs
|
||||
.GPIF_CTL1(), // n_slwr
|
||||
.GPIF_CTL2(), // n_sloe
|
||||
.GPIF_CTL3(), // n_slrd
|
||||
.GPIF_CTL7(), // n_pktend
|
||||
.GPIF_CTL4(), // slfifo_flags[0]
|
||||
.GPIF_CTL5(), // slfifo_flags[1]
|
||||
.GPIF_CTL6(), // slfifo_flags[2]
|
||||
.GPIF_CTL8(), // slfifo_flags[3]
|
||||
.GPIF_CTL11(), // slfifo_addr[1]
|
||||
.GPIF_CTL12(), // slfifo_addr[0]
|
||||
.GPIF_D(),
|
||||
.GPIF_CTL9(), // global_reset
|
||||
|
||||
// GPS
|
||||
.gps_lock(),
|
||||
.gps_rxd(),
|
||||
.gps_txd(),
|
||||
.gps_txd_nmea(),
|
||||
|
||||
// LEDS
|
||||
.LED_RX1(),
|
||||
.LED_RX2(),
|
||||
.LED_TXRX1_RX(),
|
||||
.LED_TXRX1_TX(),
|
||||
.LED_TXRX2_RX(),
|
||||
.LED_TXRX2_TX(),
|
||||
|
||||
// Misc Hardware Control
|
||||
.ref_sel(),
|
||||
.pll_lock(),
|
||||
.FPGA_CFG_CS(), // Driven by FX3 gpio.
|
||||
.AUX_PWR_ON(), // Driven by FX3 gpio.
|
||||
|
||||
// PPS
|
||||
.PPS_IN_EXT(),
|
||||
.PPS_IN_INT(),
|
||||
|
||||
// RF Hardware Control
|
||||
.SFDX1_RX(),
|
||||
.SFDX1_TX(),
|
||||
.SFDX2_RX(),
|
||||
.SFDX2_TX(),
|
||||
.SRX1_RX(),
|
||||
.SRX1_TX(),
|
||||
.SRX2_RX(),
|
||||
.SRX2_TX(),
|
||||
.tx_bandsel_a(),
|
||||
.tx_bandsel_b(),
|
||||
.tx_enable1(),
|
||||
.tx_enable2(),
|
||||
.rx_bandsel_a(),
|
||||
.rx_bandsel_b(),
|
||||
.rx_bandsel_c()
|
||||
);
|
||||
|
||||
endmodule // b200_tb
|
||||
@@ -6,8 +6,4 @@ LINE Wide 576 112 544 112
|
||||
PIN 576 112 RIGHT 36
|
||||
PINATTR PinName control0[35:0]
|
||||
PINATTR Polarity BOTH
|
||||
LINE Wide 576 144 544 144
|
||||
PIN 576 144 RIGHT 36
|
||||
PINATTR PinName control1[35:0]
|
||||
PINATTR Polarity BOTH
|
||||
|
||||
@@ -1,3 +1,3 @@
|
||||
XILINX-XDB 0.1 STUB 0.1 ASCII
|
||||
XILINX-XDM V1.6e
|
||||
$33;7=*981;86>?00684565<2:;<9:4012;0>6799>0<=<?4:23052<892;86>>01684466<2:9<=:405230>6?89;0=95>0122?72<:9:;86<>01686377:28<=:5<6;KMKPR=KFD_^BB?<2794;703:<1ECAZT;ALJQTHD86897>11:67?1678813866?0133?=6?99:;==>?11235`=E[JKES^^NRUCM21=E]OM37O[\_HLEK4=D?2IJ\Y[]E39@A44<KAOHGRBFCDLPAZR^XL80OD:4CMI32>EKC82;:6MCK3531>EKC;R37NBD2Y3;40=DDB3;96MCK@34?FJLI8N9;6MCK@3G02=DDBK:H5;4CMIA50=DDBI:96MCKE36?FJLL_i0OAEKV^FJRLBB=2IGGKV7;BNHB]7?8:1H@_74CNONMQRBLk1HCCZ]OM2?4;e<KFD_^BB?<02=g>EHF]XD@=2>1?a8GJHSZFF;0<<1c:ALJQTHD96:?3m4CNLWVJJ748>5o6M@NUPLH5:6=7i0OB@[RNN38409k2IDBY\@L1>23;e<KFD_^BB?<0:=g>EHF]XD@=2>9?`8GJHSZFF;0<0l;BMMPWIK858;2n5LOOVQKI6;:84h7NAATSMO49456j1HCCZ]OM2?668d3JEEX_AC0=07:f=DGG^YCA>324<`?FII\[EG<1<9>b9@KKRUGE:7>:0l;BMMPWIK85832n5LOOVQKI6;:04i7NAATSMO4949k2IDBY\@L1>04;e<KFD_^BB?<23=g>EHF]XD@=2<2?a8GJHSZFF;0>=1c:ALJQTHD96883k4CNLWVJJ74:?1<3m4CNLWVJJ74:?5n6M@NUPLH5:46k1HCCZ]OM2?0;d<KFD_^BB?<4<a?FII\[EG<181b:ALJQTHD96<2o5LOOVQKI6;07h0OB@[RNN38<8e3JEEX_AC1=2=g>EHF]XD@<2>0?a8GJHSZFF:0<?1c:ALJQTHD86:>3m4CNLWVJJ64895o6M@NUPLH4:6<7i0OB@[RNN28439k2IDBY\@L0>22;e<KFD_^BB><05=g>EHF]XD@<2>8?a8GJHSZFF:0<71b:ALJQTHD86:2n5LOOVQKI7;:94h7NAATSMO59466j1HCCZ]OM3?678d3JEEX_AC1=00:f=DGG^YCA?325<`?FII\[EG=1<:>b9@KKRUGE;7>;0l;BMMPWIK958<2n5LOOVQKI7;:14h7NAATSMO594>6k1HCCZ]OM3?6;e<KFD_^BB><22=g>EHF]XD@<2<1?a8GJHSZFF:0><1c:ALJQTHD868?3m4CNLWVJJ64:>5i6M@NUPLH4:4=3:5o6M@NUPLH4:4=7h0OB@[RNN2868e3JEEX_AC1=6=f>EHF]XD@<2:>c9@KKRUGE;7:3l4CNLWVJJ64>4i7NAATSMO59>9j2IDBY\@L0>::42<KFXNSJKAESCWMJHXAGLD;6M]E@VF@4=C:2NB86J]CJ68A166;2LOO95IDBG0?CBB;2LO^95IDSG2?B5<OGN:7D<4I108M44<A;80E><4I508M0?<AGC__YO[E29JJSg<B]KLSNFNIO;8NQG@W]OXX?5CI39OK3=KGJANH:5COFK@EI2<D\^:86BZT368HPR4<2F^X9:4LTV53>KRPJST@85BUYD61>KRPO<97C>;;O3241=I98;?7C?>259M51333G;?:95A1551?K403GO_[B\D6:LLGIOW?2DDAH\HE09L52=HX]CFEWKPPSKNMQOQMZUEKN?4P69S*1?cWE>0\L\[a:RJJZDR[@NSn6^FN^@VWKGJM01[GRFCUULN2>VTLFDN=6_>;S78V@UB\>1YYCZJSU38W6=TME?0_EGIT038WMTBOVOSX_OLT^LDG`=T@[OLS@GA_RKYA3=TG\XHI;5\T@VVW6=SKB90XIG<;UFL7>RJ[=1_U]K<d:W3+PYNKFD$ERWJS^@PGDH)]VHX#DQ\6/KP]K(NW\YNS^AITCQ@EKYBY9$^SO]94:W3+PYNKFD$ERWJS^@PGDH)]VHX#DQZSD]PKCRE[JKESH_?.H]VW@Y_[]U_OFQXOSIBVJSILVOZ=#[PIBMM[GUDIGUIYKI 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|
||||
$0`47=*981;86>?00684565<2:;<9:4012;0>6799>0<=<?4:23052<892;86>>01684466<2:9<=:405230>6?89;0=95>0127?406881986<?016864679>18:7GAOTV9GJHSZFF;0>;50?3801=389::75:4812355=?89;3<=>?0133456b3KYHMCQ\P@PWEK033K_MK55MUR]JJCI63J=0OL^[USG1?FC6:2ICINEPLHAFJVCX\PZN>6MF4:AOO50<KEA:4=84CMI1353<KEA9T55LLJ0[5=623JF@5=;4CMIB52=DDBK:H?94CMIB5A203JF@M<J75:AOOG723JF@O<;4CMIG50=DDBN]o6MCKET\@LPNLL?0OAEIX99@HN@_91:87NB]9:ALIHOS\LNi7NAATSMO4969k2IDBY\@L1>24;e<KFD_^BB?<03=g>EHF]XD@=2>2?a8GJHSZFF;0<=1c:ALJQTHD96:83m4CNLWVJJ748?5o6M@NUPLH5:6>7i0OB@[RNN38419k2IDBY\@L1>2<;e<KFD_^BB?<0;=f>EHF]XD@=2>>b9@KKRUGE:7>=0l;BMMPWIK858:2n5LOOVQKI6;:;4h7NAATSMO49446j1HCCZ]OM2?618d3JEEX_AC0=06:f=DGG^YCA>327<`?FII\[EG<1<8>b9@KKRUGE:7>50l;BMMPWIK85822o5LOOVQKI6;:7i0OB@[RNN38669k2IDBY\@L1>05;e<KFD_^BB?<20=g>EHF]XD@=2<3?a8GJHSZFF;0>:1e:ALJQTHD96897>1c:ALJQTHD96893l4CNLWVJJ74:4i7NAATSMO4929j2IDBY\@L1>6:g=DGG^YCA>36?`8GJHSZFF;0:0m;BMMPWIK8525n6M@NUPLH5:>68>0OB\J_FGMAWGSAFDTECH@7:AQADRBL81O>6JF4:FQGN2<M=::?6HKC59E@FC43ONN?6HKR59E@WC63N90KCJ>;H08M54<A880E?<4I208M14<A<30ECG[SUCWA6=NF_k0FYOH_BJBMK?<B]KLSYK\T39OM7=KG?1GCNEJD69OKBODIE>0@XZ>4:NVP72<D\^?86BZT758IP^DQVF>7@[WF478IP^A>;1E<:5AEUULVN0<FFIGE]94NNOFVBC63F;<7B^[ILKYAZVUADC_E[K\_OE@5>V03Y$?5iQC4:RBVQg<X@DTNX]FDY`8TLHXJ\YEM@K6;QI\LISSFD<0\^J@ND38U4=U=2XN_HZ8;SWMP@US92Y87^KC5:QKMCR692YC^HIPEYVQEFRXFNIn7^F]EF]NMKYTASO=7^AZRBG5?VRF\\Y87YMD3:VGM6=SLF90X@];;U[SA6b<]9%^SDM@N.K\]@UXJZIJB#[PBR-J[V0)AZSE"DQZSD]PKCRE[JKESH_?.T]AW32<]9%^SDM@N.K\]@UXJZIJB#[PBR-J[PUBWZEMXO]LAO]FU5(NW\YNSU][_UAH[RIUCHXDYCJPEP3-QZODGGUI_NOA_CWEC*SXJ\LL>;5Z0.W\MFII'@URI^QMSBCM*PYE[&cO^NEPLNABH7d<]9%^SDM@N.W\GHB(OV^J^JK[[02^*LYIM9$^SYO]GDV1f>S7'\UBOB@ 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U^K@KK)RWJGO#XQLOLOBJAYTME%B8#HF[2_-QZJR\;i0Y=!Z_HALJ*SXKDN$YRM@MLCM@ZUBD&C?"KGT4\,V[ISS:j1^<"[PIBMM+PYDEM%^SNABM@LG[VCK'@>%JDU:]/W\HPR5k2_;#XQFCNL,QZEJL&_TOBCBAOF\W@J(A=$MEV8R.T]OQQ4d3\:$YRGLOO-V[FKC'\UHC@CNNE]PAI)N<'LBW:S!U^NVP7e<]9%^SDM@N.W\GHB(]VIDA@OAD^QFH*O3&OCP4P Z_MWW6f=R8&_TENAA/T]@IA)RWJEFAL@K_RGO+L2)N@Q2Q#[PLTV1g>S7'\UBOB@ U^AN@*SXKFXNSDJPSDN,M1(AAR:V"XQCUU0g?P6(]VCHCC!Z_BOG+PYDG[OTEIQ\EM-J0+@NS8:V"XQCUU0g?P6(]VCHCC!Z_BOG+PYDG[OTEIQ\EM-J0+@NS8;V"XQCUU0g?P6(]VCHCC!Z_BOG+PYDG[OTEIQ\EM-J0+@NS88V"XQCUU0g?P6(]VCHCC!Z_BOG+PYDG[OTEIQ\EM-J0+@NS89V"XQCUU0g?P6(]VCHCC!Z_BOG+PYDG[OTEIQ\EM-J0+@NS8>V"XQCUU0g?P6(]VCHCC!Z_BOG+PYDG[OTEIQ\EM-J0+@NS8?V"XQCUU0`?P6(]VCHCC!Z_BOG+PYDG[OTEIQ\EM-J0+@NS8W%YRBZT3a8Q5)RW@IDB"[PCLF,QZEHZLUBHR]JL.K7*CO\:T$^SA[[2b9V4*SXAJEE#XQLME-V[FIUMVCOS^KC/H6-BL]4U'_T@XZ=c:W3+PYNKFD$YRMBD.W\GJTBW@NT_HB I5,EM^2Z&\UGYY<l;T2,QZODGG%^SNCK/T]@KWCXAMUXIA!F4/DJ_0[)]VF^X?m4U1-V[LEHF&_TO@J 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U^AN@*oSI[MNX1711`9V4*SXAJEE#XQLME-jPDT@M]UHI?m4U1-V[LEHF&_TOY\C_NWW+CYIKYQ;Q#HPCLFX4X(RWAIN>n5Z0.W\MFII'\UHX_BPOTV,BZHDXR:V"KQLMEY3Y+SXDJO9h6[?/T]JGJH(]VI_^AQ@UU-E[KEWS9W%JRMBDZ33Y+SX@JO9h6[?/T]JGJH(]VI_^AQ@UU-E[KEWS9W%JRMBDZ33Y+SXDJO9h6[?/T]JGJH(]VI_^AQ@UU-E[KEWS9W%JRMBDZ32Y+SX@JO9h6[?/T]JGJH(]VI_^AQ@UU-E[KEWS9W%JRMBDZ32Y+SXDJO9h6[?/T]JGJH(]VI_^AQ@UU-E[KEWS9W%JRMBDZ31Y+SX@JO9h6[?/T]JGJH(]VI_^AQ@UU-E[KEWS9W%JRMBDZ31Y+SXDJO9h6[?/T]JGJH(]VI_^AQ@UU-E[KEWS9W%JRMBDZ30Y+SX@JO9h6[?/T]JGJH(]VI_^AQ@UU-E[KEWS9W%JRMBDZ30Y+SXDJO9h6[?/T]JGJH(]VI_^AQ@UU-E[KEWS9W%JRMBDZ37Y+SX@JO9h6[?/T]JGJH(]VI_^AQ@UU-E[KEWS9W%JRMBDZ37Y+SXDJO9h6[?/T]JGJH(]VI_^AQ@UU-E[KEWS9W%JRMBDZ36Y+SX@JO9h6[?/T]JGJH(]VI_^AQ@UU-E[KEWS9W%JRMBDZ36Y+SXDJO9o6[?/T]JGJH(]VI_^AQ@UU-E[KEWS9W%JRMBDZ3^*PYOKL8h7X> U^K@KK)RWJ^Y@RAZT.D\JFV\8T$MSNCK[0_-QZJDM;i0Y=!Z_HALJ*SXK]XGSB[[/G]MGU]7U'LTO@JT2\,V[MEB:j1^<"[PIBMM+PYD\[FTCXZ F^L@T^6Z&OUHAIU=]/W\HFC5k2_;#XQFCNL,QZESZEUDYY!I_OAS_5[)NVIFHV=R.T]KG@4d3\:$YRGLOO-V[FRUDVE^X"HPNBRX4X(AWJGOW>S!U^N@A7e<]9%^SDM@N.W\GQTKWF__#KQACQY3Y+@XKDNP8P Z_IAF6f=R8&_TENAA/T]@PWJXG\^$JR@LPZ2^*CYDEMQ?Q#[PLBG1g>S7'\UBOB@ U^AWVIYH]]%MSCM_[1_-BZEJLR?V"XQGCD0`?P6(]VCHCC!Z_BVQHZIR\<BN^T0\,E[FKCS<W%YRBLE3a8Q5)RW@IDB"[PCUPO[JSS'OUEO]U?]/D\GHB\>T$^SEMJ2b9V4*SXAJEE#XQLTSN\KPRLine truncated
|
||||
@@ -8,7 +8,7 @@
|
||||
// \ \ \/ Version : 14.4
|
||||
// \ \ Application: Xilinx CORE Generator
|
||||
// / / Filename : chipscope_icon.v
|
||||
// /___/ /\ Timestamp : Fri Mar 08 11:51:37 PST 2013
|
||||
// /___/ /\ Timestamp : Tue Oct 22 17:04:59 PDT 2013
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
@@ -19,11 +19,9 @@
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module chipscope_icon(
|
||||
CONTROL0,
|
||||
CONTROL1) /* synthesis syn_black_box syn_noprune=1 */;
|
||||
CONTROL0) /* synthesis syn_black_box syn_noprune=1 */;
|
||||
|
||||
|
||||
inout [35 : 0] CONTROL0;
|
||||
inout [35 : 0] CONTROL1;
|
||||
|
||||
endmodule
|
||||
@@ -8,7 +8,7 @@
|
||||
// \ \ \/ Version : 14.4
|
||||
// \ \ Application: Xilinx CORE Generator
|
||||
// / / Filename : chipscope_icon.veo
|
||||
// /___/ /\ Timestamp : Fri Mar 08 11:51:37 PST 2013
|
||||
// /___/ /\ Timestamp : Tue Oct 22 17:05:00 PDT 2013
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
@@ -21,8 +21,7 @@
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
chipscope_icon YourInstanceName (
|
||||
.CONTROL0(CONTROL0), // INOUT BUS [35:0]
|
||||
.CONTROL1(CONTROL1) // INOUT BUS [35:0]
|
||||
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.4
|
||||
# Date: Fri Mar 8 19:51:09 2013
|
||||
# Date: Wed Oct 23 00:04:31 2013
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
@@ -30,7 +30,7 @@ SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fgg484
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET simulationfiles = Structural
|
||||
SET speedgrade = -3
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = false
|
||||
@@ -43,7 +43,7 @@ CSET component_name=chipscope_icon
|
||||
CSET constraint_type=external
|
||||
CSET enable_jtag_bufg=true
|
||||
CSET example_design=false
|
||||
CSET number_control_ports=2
|
||||
CSET number_control_ports=1
|
||||
CSET use_ext_bscan=false
|
||||
CSET use_softbscan=false
|
||||
CSET use_unused_bscan=false
|
||||
@@ -53,4 +53,4 @@ CSET user_scan_chain=USER1
|
||||
MISC pkg_timestamp=2012-12-18T02:47:25Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: 865957ec
|
||||
# CRC: 5ccf4baf
|
||||
@@ -51,8 +51,8 @@
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="chipscope_icon" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-03-08T11:51:40" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BD46AAD29AD5653980780005171DAA9E" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-10-22T17:05:01" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="154D57BA825522169EAB357B0FF9F497" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
The following files were generated for 'chipscope_icon' in directory
|
||||
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b200/coregen/
|
||||
/home/ianb/fpgadev/usrp3/top/b200/coregen/
|
||||
|
||||
XCO file generator:
|
||||
Generate an XCO file for compatibility with legacy flows.
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
#ChipScope Core Generator Project File Version 3.0
|
||||
#Fri Mar 08 11:53:53 PST 2013
|
||||
#Tue Oct 22 15:45:46 PDT 2013
|
||||
SignalExport.bus<0000>.channelList=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
|
||||
SignalExport.bus<0000>.name=TRIG0
|
||||
SignalExport.bus<0000>.offset=0.0
|
||||
|
||||
@@ -1,3 +1,3 @@
|
||||
XILINX-XDB 0.1 STUB 0.1 ASCII
|
||||
XILINX-XDM V1.6e
|
||||
$ed17=*981;86>?01784567811;<=>?012:?56789:;<=:?;123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0028456789:;<=>?0122<>6789::<=:401270>67;O>0<<>>1193547788;;==??0137?54?I8:0<?6N47AF56?E=>NM86>8F1684C4592;?7<??F04857>=AGZ^X7Z]IF2?571=87;j7<=5IORVP?GCL[K\^LJKR=31>586i2;86D@_UU8B@ATEZMKOH_2>2;2=51=6<3CE\XZ5AEFQE974294:86?;:HLSQQ<FLMXI0<=50?37?40=AGZ^X7JFAEK?50<768>0=;4FNQWW>AOEL@6:97>114922?IR\Y__6IANDN>21?699<1::7AZTQWW>AIELF6:97>11:01?766<281EC^ZT;FJTDBNX5;1<3?;;38JJUSS2MC[NIG_<083:45<:3CE\XZ5WDCTAI:6294:?6<5IORVP?QBJ^O^0<4?>0786?IR\Y__6IA_AEMS84<768?0>7AZTQWW>AIWJME[0<4?>00877<NFY__6IGN<2394;753:81EC^ZT;FJF956294:?6==:NWWTPR=LFK7?<4?>01877<H]]Z^X7J@B=12>586>29=6D@@UU8@KKRUGE6897>11:67?17788;087GAPTV9@LVF4:0;2<?44;KMTPR=L@ZI0>4?>0280?OIX\^1[HO33;2=55=32@D[YY4XEC>0>586:2>1CXZ_UU8GKUG;;3:5=?5;:NWWTPR=LFZI0>4?>0281177??9999??5533a>3=AGZ^X7O34;2=5>>53H:97L?=;@0;?D4A:H=M;?5N359B85833H6:295N<3<7?D:46?1J094?>59B818?3HNO^L2?>89B@ATF48:556OKDSC?548>3HNO^L2>2?`8EABUI5;86=06;@FGVD:6;720MIJ]A=3=<>GCL[K7>364AEFQE95902KOH_O34?:8EABUI5?546OKDSC?2;><IMNYM1918:CG@WG;0720MIJ]A=;=a>GCL[K\^LJKR=2=b>GCL[K\^LJKR=33:c=FLMXJ[_OKDS>25;763HNO^LY]AEFQ844=87l0MIJ]AVPB@AT;9;4n7LJKR@UQEABU484n7LJKR@UQEABU4;4n7LJKR@UQEABU4:4n7LJKR@UQEABU4=4n7LJKR@UQEABU4<4n7LJKR@UQEABU4?4n7LJKR@UQEABU4>4n7LJKR@UQEABU414n7LJKR@UQEABU40437LJKRC>3:<=FLMXI0<>19:CG@WD;98427LJKRC>26;d<IMNYN1?<:1<:?DBCZK6:?364AEFQF97902KOH_L32?:8EABUJ59546OKDS@?0;><IMNYN1;18:CG@WD;>720MIJ]B=5=<>GCL[H74364AEFQF9?9m2KOH_L]D@FGV969n2KOH_L]D@FGV9776o1JHI\MRECG@W:697;:7LJKRCPGEABU4881<3h4AEFQFWBFLMX7=?0j;@FGVGTCIMNY0<0j;@FGVGTCIMNY0?0j;@FGVGTCIMNY0>0j;@FGVGTCIMNY090j;@FGVGTCIMNY080j;@FGVGTCIMNY0;0j;@FGVGTCIMNY0:0j;@FGVGTCIMNY050j;@FGVGTCIMNY040>0:@EFGGBIH9<?>>;01:8FPUXAGLD=6M=;BC1?FC6:2ICINEPLHAFJVCX\PZN>6MF3:AOO1=DDB:=7NBD1925?FJL:>:>7NBD2Y:8GIM5P82;96MCK827?FJLI<1H@FO>7:AOOD7C:>1H@FO>D558GIMF9M227NBDAVP@HN2<KEAI96MCKC3:?FJLJ[NH@F;4CMI@50=DDBN:96MCKET`?FJLL_UOE[GKE49@HN@_02IGGKV>8118GIT>3JEFADZ[EEc8GJHSZFF7<3l4CNLWVJJ;994i7NAATSMO8479j2IDBY\@L=31:g=DGG^YCA2>3?`8GJHSZFF7=90m;BMMPWIK48?5n6M@NUPLH9716k1HCCZ]OM>23;d<KFD_^BB319<a?FII\[EG0<71a:ALJQTHD5;5n6M@NUPLH9476k1HCCZ]OM>15;d<KFD_^BB323<a?FII\[EG0?=1b:ALJQTHD58?2o5LOOVQKI:5=7h0OB@[RNN?638e3JEEX_AC<35=f>EHF]XD@1<7>c9@KKRUGE6953o4CNLWVJJ;:7h0OB@[RNN?758e3JEEX_AC<23=f>EHF]XD@1==>c9@KKRUGE68?3l4CNLWVJJ;;=4o7NAATSMO863=87h0OB@[RNN?708f3JEEX_AC<2<b?FII\[EG090n;BMMPWIK4<4j7NAATSMO838f3JEEX_AC<6<b?FII\[EG050n;BMMPWIK404:86M@RD]DAKCUI]CDBRGAFN58GWCF\LN:7I64D133G567k2NJXLQXIEVK[De<LH^JSZGKTI]A6>BN>2NBM1>17:FJE9776>1OEL2>1?58@LG;9;4<7IGN<01=3>BNI5;?2:5KI@>21;1<L@K7=;08;EKB8419?2NBM1?7>69GMD:617<0HDO31?58@LG;:94<7IGN<33=3>BNI5892:5KI@>17;1<L@K7>908;EKB8739?2NBM1<9>69GMD:5?7=0HDO329<4?AOF4;35:6JFA=0=3>BNI59;245KI@>05?69?2NBM1=>>79GMD:46?1OEL2;>79GMD:26?1OEL29>79GMD:06?1OEL27>79GMD:>611OELJF<1<:?AOFL@6:<374DHCGM976601OELJF<00==>BNIMC7=>06;EKB@L:6<7h0HDOKI=36>58>3MCJHD2>5?:8@LGCA5;546JFAEK?6;><L@KOE1=18:FJEAO;<720HDOKI=7=<>BNIMC7:364DHCGM91902NBMIG38?:8@LGCA535:6JFB=2=3>BNJ5;;2:5KIC>25;1<L@H7=?08;EKA8459?2NBN1?;>69GMG:6=7=0HDL317<4?AOE48=5;6JFB=3;:2=CAK6:5384DH@?5;1<L@H7>=08;EKA8779?2NBN1<=>69GMG:5;7=0HDL325<4?AOE4;?5;6JFB=05:2=CAK69;394DH@?6=803MCI0?716:FJF949?2NBN1=?>89GMG:493:5;6JFB=12:3=CAK682;5KIC>7:3=CAK6>2;5KIC>5:3=CAK6<2;5KIC>;:3=CAK62255KICFJ858>3MCIHD2>0?;8@LDCA5;:245KICFJ844912NBNIG312<:?AOEL@6:83l4DH@GM97229427IGMDH>21;><L@HOE1?18:FJFAO;:720HDLKI=1=<>BNJMC78364DH@GM93902NBNIG36?:8@LDCA5=546JFBEK?<;><L@HOE1717:FJTD:76>1OE]O31?58@LVF4;427IG_A=194;1<L@ZJ0>0n;EKSEAOW494h7IG_AEKS84<76h1OE]OKIQ>2:2=CAYH7<394DHRA84803MC[N1<19:FJTG:4294<7IG_B=1=e>BNXKNB\1>1c:FJTGBNX5;1<3o4DHRA@LV;97<0HBO30?58@JG;994<7IAN<03=3>BHI5;92:5KO@>27;1<LFK7=908;EMB8439?2NDM1?9>69GKD:6?7=0HBO319<4?AIF4835:6J@A=3=3>BHI58;2:5KO@>15;1<LFK7>?08;EMB8759?2NDM1<;>69GKD:5=7=0HBO327<4?AIF4;=5;6J@A=0;:2=CGH695384DNC?6;1<LFK7?=06;EMB867=87=0HBO330<5?AIF4:4=7IAN<5<5?AIF4<4=7IAN<7<5?AIF4>4=7IAN<9<5?AIF40437IANDN>3:<=CGHND0<>19:FLEAI;98427IANDN>26;?<LFKOC1?<>89GKDBH48>5n6J@AEM?50<7601OCLJ@<07=<>BHIME7=364DNCGK94902NDMIA33?:8@JGCG5>546J@AEM?1;><LFKOC1818:FLEAI;?720HBOKO=:=<>BHIME75394DNC\V@A13MEI0=08;EMA8469?2NDN1?>>69GKG:6:7=0HBL312<4?AIE48>5;6J@B=36:2=CGK6::394DN@?52803MEI0<617:FLF97>6?1OCO2>>69GKG:587=0HBL320<4?AIE4;85;6J@B=00:2=CGK698394DN@?60803MEI0?817:FLF9406>1OCO2=8?58@JD;:04=7IAM<3<4?AIE4::556J@B=12>5803MEI0>?16:FLF959>2NDN1:16:FLF939>2NDN1816:FLF919>2NDN1616:FLF9?902NDNIA30?;8@JDCG5;;245KOCFL847912NDNIA313<:?AIELF6:?374DN@GK9736k1OCOJ@<0794;?<LFHOC1?:>99GKGBH48437IAMDN>1:==CGKND0>07;EMA@J:3611OCOJ@<4<;?AIELF6=255KOCFL828?3MEIHB27>99GKGBH404<7IAM_SGD3>BHXH6;2:5KOQC?5;1<LFZJ0?06;EMSE95=87=0HB^N<2<b?AIWIME[0=0l;EMSEAIW480;2l5KOQCGKU:66>1OC]L30?58@JVE484<7IA_B=0==>BHXK686=08;EMSF959i2ND\OJ@P=2=g>BHXKND\1?50?c8@JVELFZ7=3?4E39F01=B<9897HH<;DLB3>CII^XNB>5JNC58AKDULLDi7H@PRRVQEHYFj2OES_][R@O\F1=A89=:<6H?D1G3G5D799K;<=:4F7331>@FDZO97KJ>0:DG30D>;8OH:9O72118BAE33ONHI>5IDD:8BA@?0M23?6HKP29E@W2<NMXN?6HKS59EAAE682LMIHHJEDDFA@@BML>0JKH?4:DEB@><NOLM99??119EBC@F:1:J>5>N29224>@Line truncated
|
||||
$d267=*981;86>?01784567811;<=>?012:?56789:;<=:?;123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0028456789:;<=>?0122<>6789::<=:401360>67;O>0<<>>1193547788;;==??0137?54?I8:0<?6N47AF56?E=>NM86>8F1684C4592;?7<??F04857>=AGZ^X7Z]IF2?571=87;j7<=5IORVP?GCL[K\^LJKR=31>586i2;86D@_UU8B@ATEZMKOH_2>2;2=51=6<3CE\XZ5AEFQE974294:86?;:HLSQQ<FLMXI0<=50?37?40=AGZ^X7JFAEK?50<768>0=;4FNQWW>AOEL@6:97>114922?IR\Y__6IANDN>21?699<1::7AZTQWW>AIELF6:97>11:01?766<281EC^ZT;FJTDBNX5;1<3?;;38JJUSS2MC[NIG_<083:45<:3CE\XZ5WDCTAI:6294:?6<5IORVP?QBJ^O^0<4?>0786?IR\Y__6IA_AEMS84<768?0>7AZTQWW>AIWJME[0<4?>00877<NFY__6IGN<2394;753:81EC^ZT;FJF956294:?6==:NWWTPR=LFK7?<4?>01877<H]]Z^X7J@B=12>586>29=6D@@UU8@KKRUGE6897>11:67?17788;087GAPTV9@LVF4:0;2<?44;KMTPR=L@ZI0>4?>0280?OIX\^1[HO33;2=55=32@D[YY4XEC>0>586:2>1CXZ_UU8GKUG;;3:5=?5;:NWWTPR=LFZI0>4?>0281177??9999??5533a>3=AGZ^X7O34;2=5>>53H:97L?=;@0;?D4A:H=M;?5N359B85833H6:295N<3<7?D:46?1J094?>59B818?3HNO^L2?>89B@ATF48:556OKDSC?548>3HNO^L2>2?`8EABUI5;86=06;@FGVD:6;720MIJ]A=3=<>GCL[K7>364AEFQE95902KOH_O34?:8EABUI5?546OKDSC?2;><IMNYM1918:CG@WG;0720MIJ]A=;=a>GCL[K\^LJKR=2=b>GCL[K\^LJKR=33:c=FLMXJ[_OKDS>25;763HNO^LY]AEFQ844=87l0MIJ]AVPB@AT;9;4n7LJKR@UQEABU484n7LJKR@UQEABU4;4n7LJKR@UQEABU4:4n7LJKR@UQEABU4=4n7LJKR@UQEABU4<4n7LJKR@UQEABU4?4n7LJKR@UQEABU4>4n7LJKR@UQEABU414n7LJKR@UQEABU40437LJKRC>3:<=FLMXI0<>19:CG@WD;98427LJKRC>26;d<IMNYN1?<:1<:?DBCZK6:?364AEFQF97902KOH_L32?:8EABUJ59546OKDS@?0;><IMNYN1;18:CG@WD;>720MIJ]B=5=<>GCL[H74364AEFQF9?9m2KOH_L]D@FGV969n2KOH_L]D@FGV9776o1JHI\MRECG@W:697;:7LJKRCPGEABU4881<3h4AEFQFWBFLMX7=?0j;@FGVGTCIMNY0<0j;@FGVGTCIMNY0?0j;@FGVGTCIMNY0>0j;@FGVGTCIMNY090j;@FGVGTCIMNY080j;@FGVGTCIMNY0;0j;@FGVGTCIMNY0:0j;@FGVGTCIMNY050j;@FGVGTCIMNY040>0:@EFGGBIH9<?>>;01:8FPUXAGLD=6M=;BC1?FC6:2ICINEPLHAFJVCX\PZN>6MF3:AOO1=DDB:=7NBD1925?FJL:>:>7NBD2Y:8GIM5P82;96MCK827?FJLI<1H@FO>7:AOOD7C:>1H@FO>D558GIMF9M227NBDAVP@HN2<KEAI96MCKC3:?FJLJ[NH@F;4CMI@50=DDBN:96MCKET`?FJLL_UOE[GKE49@HN@_02IGGKV>8118GIT>3JEFADZ[EEc8GJHSZFF7<3l4CNLWVJJ;994i7NAATSMO8479j2IDBY\@L=31:g=DGG^YCA2>3?`8GJHSZFF7=90m;BMMPWIK48?5n6M@NUPLH9716k1HCCZ]OM>23;d<KFD_^BB319<a?FII\[EG0<71a:ALJQTHD5;5n6M@NUPLH9476k1HCCZ]OM>15;d<KFD_^BB323<a?FII\[EG0?=1b:ALJQTHD58?2o5LOOVQKI:5=7h0OB@[RNN?638e3JEEX_AC<35=f>EHF]XD@1<7>c9@KKRUGE6953o4CNLWVJJ;:7h0OB@[RNN?758e3JEEX_AC<23=f>EHF]XD@1==>c9@KKRUGE68?3l4CNLWVJJ;;=4o7NAATSMO863=87h0OB@[RNN?708f3JEEX_AC<2<b?FII\[EG090n;BMMPWIK4<4j7NAATSMO838f3JEEX_AC<6<b?FII\[EG050n;BMMPWIK404:86M@RD]DAKCUI]CDBRGAFN58GWCF\LN:7I64D133G567k2NJXLQXIEVK[De<LH^JSZGKTI]A6>BN>2NBM1>17:FJE9776>1OEL2>1?58@LG;9;4<7IGN<01=3>BNI5;?2:5KI@>21;1<L@K7=;08;EKB8419?2NBM1?7>69GMD:617<0HDO31?58@LG;:94<7IGN<33=3>BNI5892:5KI@>17;1<L@K7>908;EKB8739?2NBM1<9>69GMD:5?7=0HDO329<4?AOF4;35:6JFA=0=3>BNI59;245KI@>05?69?2NBM1=>>79GMD:46?1OEL2;>79GMD:26?1OEL29>79GMD:06?1OEL27>79GMD:>611OELJF<1<:?AOFL@6:<374DHCGM976601OELJF<00==>BNIMC7=>06;EKB@L:6<7h0HDOKI=36>58>3MCJHD2>5?:8@LGCA5;546JFAEK?6;><L@KOE1=18:FJEAO;<720HDOKI=7=<>BNIMC7:364DHCGM91902NBMIG38?:8@LGCA535:6JFB=2=3>BNJ5;;2:5KIC>25;1<L@H7=?08;EKA8459?2NBN1?;>69GMG:6=7=0HDL317<4?AOE48=5;6JFB=3;:2=CAK6:5384DH@?5;1<L@H7>=08;EKA8779?2NBN1<=>69GMG:5;7=0HDL325<4?AOE4;?5;6JFB=05:2=CAK69;394DH@?6=803MCI0?716:FJF949?2NBN1=?>89GMG:493:5;6JFB=12:3=CAK682;5KIC>7:3=CAK6>2;5KIC>5:3=CAK6<2;5KIC>;:3=CAK62255KICFJ858>3MCIHD2>0?;8@LDCA5;:245KICFJ844912NBNIG312<:?AOEL@6:83l4DH@GM97229427IGMDH>21;><L@HOE1?18:FJFAO;:720HDLKI=1=<>BNJMC78364DH@GM93902NBNIG36?:8@LDCA5=546JFBEK?<;><L@HOE1717:FJTD:76>1OE]O31?58@LVF4;427IG_A=194;1<L@ZJ0>0n;EKSEAOW494h7IG_AEKS84<76h1OE]OKIQ>2:2=CAYH7<394DHRA84803MC[N1<19:FJTG:4294<7IG_B=1=e>BNXKNB\1>1c:FJTGBNX5;1<3o4DHRA@LV;97<0HBO30?58@JG;994<7IAN<03=3>BHI5;92:5KO@>27;1<LFK7=908;EMB8439?2NDM1?9>69GKD:6?7=0HBO319<4?AIF4835:6J@A=3=3>BHI58;2:5KO@>15;1<LFK7>?08;EMB8759?2NDM1<;>69GKD:5=7=0HBO327<4?AIF4;=5;6J@A=0;:2=CGH695384DNC?6;1<LFK7?=06;EMB867=87=0HBO330<5?AIF4:4=7IAN<5<5?AIF4<4=7IAN<7<5?AIF4>4=7IAN<9<5?AIF40437IANDN>3:<=CGHND0<>19:FLEAI;98427IANDN>26;?<LFKOC1?<>89GKDBH48>5n6J@AEM?50<7601OCLJ@<07=<>BHIME7=364DNCGK94902NDMIA33?:8@JGCG5>546J@AEM?1;><LFKOC1818:FLEAI;?720HBOKO=:=<>BHIME75394DNC\V@A13MEI0=08;EMA8469?2NDN1?>>69GKG:6:7=0HBL312<4?AIE48>5;6J@B=36:2=CGK6::394DN@?52803MEI0<617:FLF97>6?1OCO2>>69GKG:587=0HBL320<4?AIE4;85;6J@B=00:2=CGK698394DN@?60803MEI0?817:FLF9406>1OCO2=8?58@JD;:04=7IAM<3<4?AIE4::556J@B=12>5803MEI0>?16:FLF959>2NDN1:16:FLF939>2NDN1816:FLF919>2NDN1616:FLF9?902NDNIA30?;8@JDCG5;;245KOCFL847912NDNIA313<:?AIELF6:?374DN@GK9736k1OCOJ@<0794;?<LFHOC1?:>99GKGBH48437IAMDN>1:==CGKND0>07;EMA@J:3611OCOJ@<4<;?AIELF6=255KOCFL828?3MEIHB27>99GKGBH404<7IAM_SGD3>BHXH6;2:5KOQC?5;1<LFZJ0?06;EMSE95=87=0HB^N<2<b?AIWIME[0=0l;EMSEAIW480;2l5KOQCGKU:66>1OC]L30?58@JVE484<7IA_B=0==>BHXK686=08;EMSF959i2ND\OJ@P=2=g>BHXKND\1?50?c8@JVELFZ7=3?4E39F01=B<9897HH<;DLB3>CII^XNB>5JNC58AKDULLDi7H@PRRVQEHYFj2OES_][R@O\F1=A89=:<6H?D1G3G5D799K;<=:4F7331>@FDZO97KJ>0:DG30D>;8OH:9O72118BAE33ONHI>5IDD:8BA@?0M23?6HKP29E@W2<NMXN?6HKS59EAAE682LMIHHJEDDFA@@BML>0JKH?4:DEB@><NOLM99??119EBC@F:1:J>5>N29224>@Line truncated
|
||||
@@ -8,7 +8,7 @@
|
||||
// \ \ \/ Version : 14.4
|
||||
// \ \ Application: Xilinx CORE Generator
|
||||
// / / Filename : chipscope_ila_128.v
|
||||
// /___/ /\ Timestamp : Fri Mar 08 11:53:53 PST 2013
|
||||
// /___/ /\ Timestamp : Tue Oct 22 15:45:46 PDT 2013
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
|
||||
@@ -8,7 +8,7 @@
|
||||
// \ \ \/ Version : 14.4
|
||||
// \ \ Application: Xilinx CORE Generator
|
||||
// / / Filename : chipscope_ila_128.veo
|
||||
// /___/ /\ Timestamp : Fri Mar 08 11:53:53 PST 2013
|
||||
// /___/ /\ Timestamp : Tue Oct 22 15:45:46 PDT 2013
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.4
|
||||
# Date: Fri Mar 8 19:52:17 2013
|
||||
# Date: Tue Oct 22 22:44:09 2013
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
@@ -30,7 +30,7 @@ SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fgg484
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET simulationfiles = Structural
|
||||
SET speedgrade = -3
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = false
|
||||
@@ -112,7 +112,7 @@ CSET match_units_6=1
|
||||
CSET match_units_7=1
|
||||
CSET match_units_8=1
|
||||
CSET match_units_9=1
|
||||
CSET max_sequence_levels=1
|
||||
CSET max_sequence_levels=2
|
||||
CSET number_of_trigger_ports=1
|
||||
CSET sample_data_depth=1024
|
||||
CSET sample_on=Rising
|
||||
@@ -138,4 +138,4 @@ CSET use_rpms=false
|
||||
MISC pkg_timestamp=2012-12-18T02:47:40Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: 194c140a
|
||||
# CRC: e17f8549
|
||||
@@ -17,11 +17,11 @@
|
||||
<files>
|
||||
<file xil_pn:name="chipscope_ila_128.ngc" xil_pn:type="FILE_NGC">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="chipscope_ila_128.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
|
||||
@@ -51,8 +51,8 @@
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="chipscope_ila_128" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-03-08T11:53:54" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="9340B6BAD141C451B74411D3998AD5A4" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-10-22T15:45:48" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="7648BEB3D1E056005214224EBE9A99B3" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
The following files were generated for 'chipscope_ila_128' in directory
|
||||
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b200/coregen/
|
||||
/home/ianb/fpgadev/usrp3/top/b200/coregen/
|
||||
|
||||
XCO file generator:
|
||||
Generate an XCO file for compatibility with legacy flows.
|
||||
|
||||
@@ -1,10 +1,9 @@
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET designentry = Verilog
|
||||
SET device = xc6slx75
|
||||
SET device = xc6slx150
|
||||
SET devicefamily = spartan6
|
||||
SET flowvendor = Foundation_ISE
|
||||
SET package = fgg484
|
||||
SET speedgrade = -3
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = false
|
||||
|
||||
+22
-54
@@ -1,14 +1,27 @@
|
||||
//
|
||||
// Copyright 2013 Ettus Research LLC
|
||||
//
|
||||
|
||||
// This program is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
|
||||
// radio top level module for b200
|
||||
// Contains all clock-rate DSP components, all radio and hardware controls and settings
|
||||
|
||||
module radio_b200
|
||||
#(
|
||||
parameter FIFO_SIZE = 13
|
||||
parameter RADIO_FIFO_SIZE = 13,
|
||||
parameter SAMPLE_FIFO_SIZE = 11
|
||||
)
|
||||
(input radio_clk, input radio_rst,
|
||||
input [31:0] rx, output [31:0] tx,
|
||||
@@ -20,7 +33,7 @@ module radio_b200
|
||||
input [63:0] ctrl_tdata, input ctrl_tlast, input ctrl_tvalid, output ctrl_tready,
|
||||
output [63:0] resp_tdata, output resp_tlast, output resp_tvalid, input resp_tready,
|
||||
|
||||
output [31:0] debug
|
||||
output [63:0] debug
|
||||
);
|
||||
|
||||
// ///////////////////////////////////////////////////////////////////////////////
|
||||
@@ -66,7 +79,7 @@ module radio_b200
|
||||
.i_aclk(bus_clk), .i_tvalid(ctrl_tvalid), .i_tready(ctrl_tready), .i_tdata({ctrl_tlast, ctrl_tdata}),
|
||||
.o_aclk(radio_clk), .o_tvalid(ctrl_tvalid_r), .o_tready(ctrl_tready_r), .o_tdata({ctrl_tlast_r, ctrl_tdata_r}));
|
||||
|
||||
axi_fifo_2clk #(.WIDTH(65), .SIZE(FIFO_SIZE)) tx_fifo
|
||||
axi_fifo_2clk #(.WIDTH(65), .SIZE(RADIO_FIFO_SIZE)) tx_fifo
|
||||
(.reset(bus_rst),
|
||||
.i_aclk(bus_clk), .i_tvalid(tx_tvalid), .i_tready(tx_tready), .i_tdata({tx_tlast, tx_tdata}),
|
||||
.o_aclk(radio_clk), .o_tvalid(tx_tvalid_r), .o_tready(tx_tready_r), .o_tdata({tx_tlast_r, tx_tdata_r}));
|
||||
@@ -76,7 +89,7 @@ module radio_b200
|
||||
.i_aclk(radio_clk), .i_tvalid(rmux_tvalid_r), .i_tready(rmux_tready_r), .i_tdata({rmux_tlast_r, rmux_tdata_r}),
|
||||
.o_aclk(bus_clk), .o_tvalid(resp_tvalid), .o_tready(resp_tready), .o_tdata({resp_tlast, resp_tdata}));
|
||||
|
||||
axi_fifo_2clk #(.WIDTH(65), .SIZE(FIFO_SIZE)) rx_fifo
|
||||
axi_fifo_2clk #(.WIDTH(65), .SIZE(RADIO_FIFO_SIZE)) rx_fifo
|
||||
(.reset(radio_rst),
|
||||
.i_aclk(radio_clk), .i_tvalid(rx_mux_tvalid_r), .i_tready(rx_mux_tready_r), .i_tdata({rx_mux_tlast_r, rx_mux_tdata_r}),
|
||||
.o_aclk(bus_clk), .o_tvalid(rx_tvalid), .o_tready(rx_tready), .o_tdata({rx_tlast, rx_tdata}));
|
||||
@@ -162,6 +175,8 @@ module radio_b200
|
||||
wire [31:0] sid;
|
||||
wire [23:0] tx_fe_i, tx_fe_q;
|
||||
|
||||
wire [31:0] debug_tx_control;
|
||||
|
||||
assign tx[31:16] = (run_tx)? tx_fe_i[23:8] : tx_idle[31:16];
|
||||
assign tx[15:0] = (run_tx)? tx_fe_q[23:8] : tx_idle[15:0];
|
||||
|
||||
@@ -180,7 +195,7 @@ module radio_b200
|
||||
.seqnum(seqnum), .error_code(error_code), .sid(sid),
|
||||
.sample_tdata(txsample_tdata), .sample_tvalid(txsample_tvalid), .sample_tready(txsample_tready),
|
||||
.sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
|
||||
.debug());
|
||||
.debug(debug_tx_control));
|
||||
|
||||
tx_responder #(.BASE(SR_TX_CTRL+2)) tx_responder
|
||||
(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
|
||||
@@ -213,7 +228,7 @@ module radio_b200
|
||||
wire [11:0] rx_seqnum;
|
||||
wire [63:0] rx_tdata_i; wire rx_tlast_i, rx_tvalid_i, rx_tready_i;
|
||||
|
||||
new_rx_framer #(.BASE(SR_RX_CTRL+4)) new_rx_framer
|
||||
new_rx_framer #(.BASE(SR_RX_CTRL+4),.SAMPLE_FIFO_SIZE(SAMPLE_FIFO_SIZE)) new_rx_framer
|
||||
(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
|
||||
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
|
||||
.vita_time(vita_time),
|
||||
@@ -266,53 +281,6 @@ module radio_b200
|
||||
.i3_tdata(), .i3_tlast(), .i3_tvalid(1'b0), .i3_tready(),
|
||||
.o_tdata(rmux_tdata_r), .o_tlast(rmux_tlast_r), .o_tvalid(rmux_tvalid_r), .o_tready(rmux_tready_r));
|
||||
|
||||
wire [255:0] debug1;
|
||||
|
||||
reg [255:0] debug2;
|
||||
|
||||
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
|
||||
always @(posedge radio_clk)
|
||||
debug2 <= debug1;
|
||||
|
||||
wire [35:0] CONTROL0,CONTROL1;
|
||||
|
||||
chipscope_ila_256 chipscope_ila_256(
|
||||
.CONTROL(CONTROL0), // INOUT BUS [35:0]
|
||||
.CLK(radio_clk), // IN
|
||||
.TRIG0(debug2) // IN BUS [31:0]
|
||||
);
|
||||
|
||||
chipscope_ila_32 chipscope_ila_32(
|
||||
.CONTROL(CONTROL1), // INOUT BUS [35:0]
|
||||
.CLK(radio_clk), // IN
|
||||
.TRIG0(32'd0) // IN BUS [31:0]
|
||||
);
|
||||
|
||||
chipscope_icon chipscope_icon(
|
||||
.CONTROL0(CONTROL0), // INOUT BUS [35:0]
|
||||
.CONTROL1(CONTROL1) // INOUT BUS [35:0]
|
||||
);
|
||||
|
||||
assign debug1 = {
|
||||
debug_tx_framer, // [214:206]
|
||||
debug_tx_control, // [205:177]
|
||||
set_data, // [176:145]
|
||||
set_addr, // [144:137]
|
||||
set_stb, // [136]
|
||||
run_tx, // [135]
|
||||
run_rx, // [134]
|
||||
tx_tlast, // [133]
|
||||
tx_tready, // [132]
|
||||
tx_tvalid, // [131]
|
||||
ctrl_tlast, // [130]
|
||||
ctrl_tready, // [129]
|
||||
ctrl_tvalid, // [128]
|
||||
tx_tdata, // [127:64]
|
||||
ctrl_tdata // [63:0]
|
||||
};
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
|
||||
|
||||
endmodule // radio_b200
|
||||
+22
-17
@@ -20,21 +20,26 @@ TIMESPEC "TS_codec_data_clk_p" = PERIOD "codec_data_clk_p" 16276 ps HIGH 50 %;
|
||||
INST "GPIF_*" IOB = TRUE;
|
||||
|
||||
#low speed misc output group
|
||||
INST "SFDX*" TNM = ls_misc_out;
|
||||
INST "SRX*" TNM = ls_misc_out;
|
||||
INST "LED_*" TNM = ls_misc_out;
|
||||
INST "tx_enable*" TNM = ls_misc_out;
|
||||
INST "tx_bandsel_*" TNM = ls_misc_out;
|
||||
INST "rx_bandsel_*" TNM = ls_misc_out;
|
||||
INST "ref_sel" TNM = ls_misc_out;
|
||||
INST "*_ce" TNM = ls_misc_out;
|
||||
INST "*_miso" TNM = ls_misc_out;
|
||||
INST "*_mosi" TNM = ls_misc_out;
|
||||
INST "*_sclk" TNM = ls_misc_out;
|
||||
INST "gps_*" TNM = ls_misc_out;
|
||||
INST "FPGA_*D0" TNM = ls_misc_out;
|
||||
INST "SFDX*" TNM = radio_misc_out; # Radio Clk domain
|
||||
INST "SRX*" TNM = radio_misc_out; # Radio Clk domain
|
||||
INST "LED_*" TNM = radio_misc_out; # Radio Clk domain
|
||||
INST "tx_enable*" TNM = radio_misc_out; # Radio Clk domain
|
||||
INST "tx_bandsel_*" TNM = ls_misc_out; # Bus clk domain
|
||||
INST "rx_bandsel_*" TNM = ls_misc_out; # Bus clk domain
|
||||
INST "ref_sel" TNM = ls_misc_out; # Bus clk domain
|
||||
INST "pll_ce" TNM = ls_misc_out; # Bus clk domain
|
||||
INST "cat_ce" TNM = ls_misc_out; # Bus clk domain + combinatorial
|
||||
#INST "fx3_miso" TNM = ls_misc_out; # Combinatorial
|
||||
INST "cat_miso" TNM = ls_misc_out; # Bus clk domain (I)
|
||||
INST "cat_mosi" TNM = ls_misc_out; # Bus clk domain + combinatorial
|
||||
INST "pll_mosi" TNM = ls_misc_out; # Bus clk domain + combinatorial
|
||||
INST "*_sclk" TNM = ls_misc_out; # Bus clk domain + combinatorial
|
||||
INST "gps_*" TNM = ls_misc_out; # Bus clk domain
|
||||
#INST "FPGA_*D0" TNM = ls_misc_out; # UNUSED
|
||||
|
||||
#constrain the misc IOs to the clocks
|
||||
NET "gpif_clk" TNM_NET = "gpif_clk";
|
||||
TIMESPEC "TS_gpif_clk" = PERIOD "gpif_clk" 10 ns HIGH 50 %;
|
||||
TIMEGRP "ls_misc_out" OFFSET = OUT 15 ns AFTER "gpif_clk" RISING;
|
||||
TIMEGRP "radio_misc_out" OFFSET = OUT 15 ns AFTER "radio_clk" RISING;
|
||||
|
||||
#constrain the misc IOs to the bus clock
|
||||
NET "bus_clk" TNM_NET = "bus_clk";
|
||||
TIMESPEC "TS_bus_clk" = PERIOD "bus_clk" 10 ns HIGH 50 %;
|
||||
TIMEGRP "ls_misc_out" OFFSET = OUT 15 ns AFTER "bus_clk" RISING;
|
||||
@@ -2,8 +2,19 @@
|
||||
#
|
||||
# Copyright 2010 Ettus Research LLC
|
||||
#
|
||||
|
||||
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Description:
|
||||
# generates a list of inputs and outputs from the top-level Verilog file and cross-references them to the .ucf.
|
||||
# outputs errors for pins that aren't found in the UCF, checks for capitalization errors and other common mistakes
|
||||
|
||||
@@ -2,6 +2,18 @@
|
||||
#
|
||||
# Copyright 2011-2012 Ettus Research LLC
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
import sys
|
||||
import re
|
||||
|
||||
@@ -2,6 +2,19 @@
|
||||
#
|
||||
# Copyright 2012 Ettus Research LLC
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
|
||||
|
||||
import xml.etree.ElementTree as et
|
||||
|
||||
@@ -1,6 +1,21 @@
|
||||
#
|
||||
# Copyright 2008 Ettus Research LLC
|
||||
#
|
||||
# GNU Radio is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; either version 3, or (at your option)
|
||||
# any later version.
|
||||
#
|
||||
# GNU Radio is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with GNU Radio; see the file COPYING. If not, write to
|
||||
# the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
# Boston, MA 02110-1301, USA.
|
||||
#
|
||||
|
||||
proc set_props {process options} {
|
||||
if ![string compare $options ""] {
|
||||
|
||||
Reference in new issue
Block a user