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b2xx: Updating FPGA source with recent bugfixes.

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Original-commit: 4b4365a517938b365af57674a3ab1462432c2c3a
This commit is contained in:
Ben Hilburn
2013-12-03 10:35:35 -08:00
parent c91b74de33
commit 29086f9001
103 changed files with 2001 additions and 608 deletions
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top/b200/b200.v
+35 -37
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@@ -1,7 +1,19 @@
//
// Copyright 2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
/***********************************************************
* B200 Module Declaration
@@ -23,8 +35,8 @@ module b200 (
output pll_sclk,
// UART
input FPGA_RXD0,
input FPGA_TXD0,
input FPGA_RXD0, // These pins goto 3 pin 0.1" header on B2x0 and
output FPGA_TXD0, // carry FX3 UART.
// Catalina Controls
output codec_enable,
@@ -63,8 +75,8 @@ module b200 (
output GPIF_CTL7, // n_pktend
input GPIF_CTL4, // slfifo_flags[0]
input GPIF_CTL5, // slfifo_flags[1]
input GPIF_CTL6, // slfifo_flags[2]
input GPIF_CTL8, // slfifo_flags[3]
input GPIF_CTL6, // Serial settings bus from FX3. SDA
input GPIF_CTL8, // Serial settings bus from FX3. SCL
output GPIF_CTL11, // slfifo_addr[1]
output GPIF_CTL12, // slfifo_addr[0]
inout [31:0] GPIF_D,
@@ -122,10 +134,14 @@ module b200 (
b200_clk_gen gen_clks
(
.CLK_IN1_40_P(codec_main_clk_p), .CLK_IN1_40_N(codec_main_clk_n),
.CLK_OUT1_40_int(), .CLK_OUT2_100_gpif(gpif_clk), .CLK_OUT3_100_bus(bus_clk),
.CLK_OUT1_40_int(), .CLK_OUT2_100_gpif(gpif_clk), .CLK_OUT3_100_bus(),
.RESET(reset_global), .LOCKED(locked)
);
// Bus Clock and GPIF Clock both same 100MHz clock.
assign bus_clk = gpif_clk;
//hold-off logic for clocks ready
reg [15:0] clocks_ready_count;
reg clocks_ready;
@@ -193,32 +209,10 @@ module b200 (
wire ctrl_tvalid, resp_tvalid, rx_tvalid, tx_tvalid;
wire ctrl_tready, resp_tready, rx_tready, tx_tready;
///////////////////////////////////////////////////////////////////////
// loopback testers
///////////////////////////////////////////////////////////////////////
/*
axi_fifo #(.WIDTH(65), .SIZE(13)) f0
(
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
.i_tdata({ctrl_tlast, ctrl_tdata}), .i_tvalid(ctrl_tvalid), .i_tready(ctrl_tready), .space(),
.o_tdata({resp_tlast, resp_tdata}), .o_tvalid(resp_tvalid), .o_tready(resp_tready), .occupied()
);
//*/
/*
axi_fifo #(.WIDTH(65), .SIZE(13)) f1
(
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
.i_tdata({tx_tlast, tx_tdata}), .i_tvalid(tx_tvalid), .i_tready(tx_tready), .space(),
.o_tdata({rx_tlast, rx_tdata}), .o_tvalid(rx_tvalid), .o_tready(rx_tready), .occupied()
);
//*/
///////////////////////////////////////////////////////////////////////
// frontend assignments
///////////////////////////////////////////////////////////////////////
wire [31:0] debug_radio;
wire [31:0] fe_atr1, fe_atr2;
assign {tx_enable1, SFDX1_RX, SFDX1_TX, SRX1_RX, SRX1_TX, LED_RX1, LED_TXRX1_RX, LED_TXRX1_TX} = fe_atr1[7:0];
assign {tx_enable2, SFDX2_RX, SFDX2_TX, SRX2_RX, SRX2_TX, LED_RX2, LED_TXRX2_RX, LED_TXRX2_TX} = fe_atr2[7:0];
@@ -237,7 +231,8 @@ module b200 (
///////////////////////////////////////////////////////////////////////
// b200 core
///////////////////////////////////////////////////////////////////////
b200_core #(.EXTRA_BUFF_SIZE(12)) b200_xfusion_core
b200_core #(.EXTRA_BUFF_SIZE(12)) b200_core
(
.bus_clk(bus_clk), .bus_rst(bus_rst),
.tx_tdata(tx_tdata), .tx_tlast(tx_tlast), .tx_tvalid(tx_tvalid), .tx_tready(tx_tready),
@@ -253,15 +248,19 @@ module b200 (
.rxd(gps_txd), .txd(gps_rxd),
.sclk(sclk), .sen(sen), .mosi(mosi), .miso(miso),
.rb_misc({31'b0, pll_lock}), .misc_outs(misc_outs)
.rb_misc({31'b0, pll_lock}), .misc_outs(misc_outs),
.debug_scl(GPIF_CTL8), .debug_sda(GPIF_CTL6),
.debug_txd(FPGA_TXD0), .debug_rxd(FPGA_RXD0),
.debug()
);
///////////////////////////////////////////////////////////////////////
// GPIF2
///////////////////////////////////////////////////////////////////////
wire [31:0] debug_gpif;
gpif2_slave_fifo32 #(.DATA_RX_FIFO_SIZE(14), .DATA_TX_FIFO_SIZE(14)) slave_fifo32
gpif2_slave_fifo32 #(.DATA_RX_FIFO_SIZE(14), .DATA_TX_FIFO_SIZE(14)) slave_fifo32
(
.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), .gpif_enb(1'b1),
.gpif_ctl({GPIF_CTL8, GPIF_CTL6, GPIF_CTL5, GPIF_CTL4}), .fifoadr({GPIF_CTL11,GPIF_CTL12}),
@@ -274,13 +273,12 @@ module b200 (
.ctrl_tdata(ctrl_tdata), .ctrl_tlast(ctrl_tlast), .ctrl_tvalid(ctrl_tvalid), .ctrl_tready(ctrl_tready),
.resp_tdata(resp_tdata), .resp_tlast(resp_tlast), .resp_tvalid(resp_tvalid), .resp_tready(resp_tready),
.debug(debug_gpif)
.debug()
);
///////////////////////////////////////////////////////////////////////
// Debug port
///////////////////////////////////////////////////////////////////////
assign debug_clk_int = { 1'b0, 1'b0 };
assign debug = 32'b0;
assign debug = 0;
endmodule // B200
top/b200/b200_core.v
+75 -11
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@@ -1,7 +1,19 @@
//
// Copyright 2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
/***********************************************************
* B200 Core Guts
@@ -15,7 +27,10 @@ module b200_core
parameter R0_DATA_SID = 8'h50,
parameter R1_DATA_SID = 8'h60,
parameter DEMUX_SID_MASK = 8'hf0,
parameter EXTRA_BUFF_SIZE = 0
parameter EXTRA_BUFF_SIZE = 0,
parameter RADIO_FIFO_SIZE = 12,
parameter SAMPLE_FIFO_SIZE = 11
)
(
////////////////////////////////////////////////////////////////////
@@ -53,8 +68,15 @@ module b200_core
output [7:0] sen, output sclk, output mosi, input miso,
input [31:0] rb_misc,
output [31:0] misc_outs,
output [31:0] debug
////////////////////////////////////////////////////////////////////
// debug UART
////////////////////////////////////////////////////////////////////
output debug_txd, input debug_rxd,
input debug_scl, input debug_sda,
////////////////////////////////////////////////////////////////////
// debug signals
////////////////////////////////////////////////////////////////////
output [63:0] debug
);
localparam SR_CORE_SPI = 8'd8;
localparam SR_CORE_MISC = 8'd16;
@@ -62,7 +84,7 @@ module b200_core
localparam SR_CORE_READBACK = 8'd32;
localparam SR_CORE_GPSDO_ST = 8'd40;
localparam SR_CORE_PPS_SEL = 8'd48;
localparam COMPAT_MAJOR = 16'h0002;
localparam COMPAT_MAJOR = 16'h0003;
localparam COMPAT_MINOR = 16'h0000;
/*******************************************************************
@@ -119,14 +141,14 @@ module b200_core
******************************************************************/
wire [63:0] u0i_ctrl_tdata; wire u0i_ctrl_tlast, u0i_ctrl_tvalid, u0i_ctrl_tready;
axi_fifo #(.WIDTH(65), .SIZE(0)) ushart_timing_fifo
axi_fifo #(.WIDTH(65), .SIZE(0)) uart_timing_fifo
(
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
.i_tdata({u0_ctrl_tlast, u0_ctrl_tdata}), .i_tvalid(u0_ctrl_tvalid), .i_tready(u0_ctrl_tready), .space(),
.o_tdata({u0i_ctrl_tlast, u0i_ctrl_tdata}), .o_tvalid(u0i_ctrl_tvalid), .o_tready(u0i_ctrl_tready), .occupied()
);
cvita_uart #(.SIZE(7)) ushart
cvita_uart #(.SIZE(7)) uart
(
.clk(bus_clk), .rst(bus_rst), .rxd(rxd), .txd(txd),
.i_tdata(u0i_ctrl_tdata), .i_tlast(u0i_ctrl_tlast), .i_tvalid(u0i_ctrl_tvalid), .i_tready(u0i_ctrl_tready),
@@ -247,7 +269,9 @@ module b200_core
/*******************************************************************
* Radio 0
******************************************************************/
radio_b200 #(.FIFO_SIZE(13)) the_radio
wire [63:0] radio0_debug;
radio_b200 #(.RADIO_FIFO_SIZE(RADIO_FIFO_SIZE),.SAMPLE_FIFO_SIZE(SAMPLE_FIFO_SIZE)) radio_0
(
.radio_clk(radio_clk), .radio_rst(radio_rst),
.rx(rx0), .tx(tx0), .fe_atr(fe_atr0), .pps(pps),
@@ -258,7 +282,7 @@ module b200_core
.ctrl_tdata(r0_ctrl_tdata), .ctrl_tlast(r0_ctrl_tlast), .ctrl_tvalid(r0_ctrl_tvalid), .ctrl_tready(r0_ctrl_tready),
.resp_tdata(r0_resp_tdata), .resp_tlast(r0_resp_tlast), .resp_tvalid(r0_resp_tvalid), .resp_tready(r0_resp_tready),
.debug()
.debug(radio0_debug)
);
/*******************************************************************
@@ -267,7 +291,7 @@ module b200_core
`ifdef B200_CAN_HAZ_R1
assign radio_st = 8'h2;
radio_b200 #(.FIFO_SIZE(13)) the_radio_1
radio_b200 #(.RADIO_FIFO_SIZE(RADIO_FIFO_SIZE),.SAMPLE_FIFO_SIZE(SAMPLE_FIFO_SIZE)) radio_1
(
.radio_clk(radio_clk), .radio_rst(radio_rst),
.rx(rx1), .tx(tx1), .fe_atr(fe_atr1), .pps(pps),
@@ -300,6 +324,46 @@ module b200_core
assign r1_rx_tvalid = r1_tx_tvalid;
assign r1_tx_tready = r1_tx_tready;
`endif
`endif // !`ifdef B200_CAN_HAZ_R1
/*******************************************************************
* Debug UART for FX3
******************************************************************/
wire debug_stb;
wire [31:0] debug_data;
wire [7:0] debug_addr;
serial_to_settings serial_to_settings_i1
(
.clk(bus_clk),
.reset(bus_rst),
.scl(debug_scl),
.sda(debug_sda),
.set_stb(debug_stb),
.set_addr(debug_addr),
.set_data(debug_data)
);
simple_uart debug_uart
(
.clk_i(bus_clk),
.rst_i(bus_rst),
.we_i(debug_stb),
.stb_i(debug_stb),
.cyc_i(debug_stb),
.ack_o(),
.adr_i(debug_addr[2:0]),
.dat_i(debug_data[31:0]),
.dat_o(),
.rx_int_o(),
.tx_int_o(),
.tx_o(debug_txd),
.rx_i(debug_rxd),
.baud_o()
);
endmodule // b200_core
top/b200/b200_tb.v
+213
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@@ -0,0 +1,213 @@
module b200_tb ();
wire cat_ce;
wire cat_miso;
wire cat_mosi;
wire cat_sclk;
wire fx3_ce;
wire fx3_miso;
wire fx3_mosi;
wire fx3_sclk;
wire pll_ce;
wire pll_mosi;
wire pll_sclk;
// UART
wire FPGA_RXD0;
wire FPGA_TXD0;
// Catalina Controls
wire codec_enable;
wire codec_en_agc;
wire codec_reset;
wire codec_sync;
wire codec_txrx;
wire [3:0] codec_ctrl_in; // These should be outputs
wire [7:0] codec_ctrl_out; // MUST BE INPUT
// Catalina Data
wire codec_data_clk_p; // Clock from CAT (RX)
wire codec_fb_clk_p; // Clock to CAT (TX)
wire [11:0] rx_codec_d;
wire [11:0] tx_codec_d;
wire rx_frame_p;
wire tx_frame_p;
wire cat_clkout_fpga;
//always on 40MHz clock
wire codec_main_clk_p;
wire codec_main_clk_n;
// Debug Bus
wire [31:0] debug;
wire [1:0] debug_clk;
// GPIF; FX3 Slave FIFO
wire IFCLK; // pclk
wire FX3_EXTINT;
wire GPIF_CTL0; // n_slcs
wire GPIF_CTL1; // n_slwr
wire GPIF_CTL2; // n_sloe
wire GPIF_CTL3; // n_slrd
wire GPIF_CTL7; // n_pktend
wire GPIF_CTL4; // slfifo_flags[0]
wire GPIF_CTL5; // slfifo_flags[1]
wire GPIF_CTL6; // slfifo_flags[2]
wire GPIF_CTL8; // slfifo_flags[3]
wire GPIF_CTL11; // slfifo_addr[1]
wire GPIF_CTL12; // slfifo_addr[0]
wire [31:0] GPIF_D;
wire GPIF_CTL9; // global_reset
// GPS
wire gps_lock;
wire gps_rxd;
wire gps_txd;
wire gps_txd_nmea;
// LEDS
wire LED_RX1;
wire LED_RX2;
wire LED_TXRX1_RX;
wire LED_TXRX1_TX;
wire LED_TXRX2_RX;
wire LED_TXRX2_TX;
// Misc Hardware Control
wire ref_sel;
wire pll_lock;
wire FPGA_CFG_CS; // Driven by FX3 gpio.
wire AUX_PWR_ON; // Driven by FX3 gpio.
// PPS
wire PPS_IN_EXT;
wire PPS_IN_INT;
// RF Hardware Control
wire SFDX1_RX;
wire SFDX1_TX;
wire SFDX2_RX;
wire SFDX2_TX;
wire SRX1_RX;
wire SRX1_TX;
wire SRX2_RX;
wire SRX2_TX;
wire tx_bandsel_a;
wire tx_bandsel_b;
wire tx_enable1;
wire tx_enable2;
wire rx_bandsel_a;
wire rx_bandsel_b;
wire rx_bandsel_c;
b200 b200_i1(
// SPI Interfaces
.cat_ce(),
.cat_miso(),
.cat_mosi(),
.cat_sclk(),
.fx3_ce(),
.fx3_miso(),
.fx3_mosi(),
.fx3_sclk(),
.pll_ce(),
.pll_mosi(),
.pll_sclk(),
// UART
.FPGA_RXD0(),
.FPGA_TXD0(),
// Catalina Controls
.codec_enable(),
.codec_en_agc(),
.codec_reset(),
.codec_sync(),
.codec_txrx(),
.codec_ctrl_in(), // These should be outputs
.codec_ctrl_out(), // MUST BE INPUT
// Catalina Data
.codec_data_clk_p(), // Clock from CAT (RX)
.codec_fb_clk_p(), // Clock to CAT (TX)
.rx_codec_d(),
.tx_codec_d(),
.rx_frame_p(),
.tx_frame_p(),
.cat_clkout_fpga(),
//always on 40MHz clock
.codec_main_clk_p(),
.codec_main_clk_n(),
// Debug Bus
.debug(),
.debug_clk(),
// GPIF, FX3 Slave FIFO
.IFCLK(), // pclk
.FX3_EXTINT(),
.GPIF_CTL0(), // n_slcs
.GPIF_CTL1(), // n_slwr
.GPIF_CTL2(), // n_sloe
.GPIF_CTL3(), // n_slrd
.GPIF_CTL7(), // n_pktend
.GPIF_CTL4(), // slfifo_flags[0]
.GPIF_CTL5(), // slfifo_flags[1]
.GPIF_CTL6(), // slfifo_flags[2]
.GPIF_CTL8(), // slfifo_flags[3]
.GPIF_CTL11(), // slfifo_addr[1]
.GPIF_CTL12(), // slfifo_addr[0]
.GPIF_D(),
.GPIF_CTL9(), // global_reset
// GPS
.gps_lock(),
.gps_rxd(),
.gps_txd(),
.gps_txd_nmea(),
// LEDS
.LED_RX1(),
.LED_RX2(),
.LED_TXRX1_RX(),
.LED_TXRX1_TX(),
.LED_TXRX2_RX(),
.LED_TXRX2_TX(),
// Misc Hardware Control
.ref_sel(),
.pll_lock(),
.FPGA_CFG_CS(), // Driven by FX3 gpio.
.AUX_PWR_ON(), // Driven by FX3 gpio.
// PPS
.PPS_IN_EXT(),
.PPS_IN_INT(),
// RF Hardware Control
.SFDX1_RX(),
.SFDX1_TX(),
.SFDX2_RX(),
.SFDX2_TX(),
.SRX1_RX(),
.SRX1_TX(),
.SRX2_RX(),
.SRX2_TX(),
.tx_bandsel_a(),
.tx_bandsel_b(),
.tx_enable1(),
.tx_enable2(),
.rx_bandsel_a(),
.rx_bandsel_b(),
.rx_bandsel_c()
);
endmodule // b200_tb
top/b200/coregen/chipscope_icon.asy
-4
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@@ -6,8 +6,4 @@ LINE Wide 576 112 544 112
PIN 576 112 RIGHT 36
PINATTR PinName control0[35:0]
PINATTR Polarity BOTH
LINE Wide 576 144 544 144
PIN 576 144 RIGHT 36
PINATTR PinName control1[35:0]
PINATTR Polarity BOTH
top/b200/coregen/chipscope_icon.ngc
+1 -1
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File diff suppressed because one or more lines are too long
top/b200/coregen/chipscope_icon.v
+2 -4
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@@ -8,7 +8,7 @@
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : chipscope_icon.v
// /___/ /\ Timestamp : Fri Mar 08 11:51:37 PST 2013
// /___/ /\ Timestamp : Tue Oct 22 17:04:59 PDT 2013
// \ \ / \
// \___\/\___\
//
@@ -19,11 +19,9 @@
`timescale 1ns/1ps
module chipscope_icon(
CONTROL0,
CONTROL1) /* synthesis syn_black_box syn_noprune=1 */;
CONTROL0) /* synthesis syn_black_box syn_noprune=1 */;
inout [35 : 0] CONTROL0;
inout [35 : 0] CONTROL1;
endmodule
top/b200/coregen/chipscope_icon.veo
+2 -3
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@@ -8,7 +8,7 @@
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : chipscope_icon.veo
// /___/ /\ Timestamp : Fri Mar 08 11:51:37 PST 2013
// /___/ /\ Timestamp : Tue Oct 22 17:05:00 PDT 2013
// \ \ / \
// \___\/\___\
//
@@ -21,8 +21,7 @@
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
chipscope_icon YourInstanceName (
.CONTROL0(CONTROL0), // INOUT BUS [35:0]
.CONTROL1(CONTROL1) // INOUT BUS [35:0]
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
top/b200/coregen/chipscope_icon.xco
+4 -4
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@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Fri Mar 8 19:51:09 2013
# Date: Wed Oct 23 00:04:31 2013
#
##############################################################
#
@@ -30,7 +30,7 @@ SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET simulationfiles = Structural
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = false
@@ -43,7 +43,7 @@ CSET component_name=chipscope_icon
CSET constraint_type=external
CSET enable_jtag_bufg=true
CSET example_design=false
CSET number_control_ports=2
CSET number_control_ports=1
CSET use_ext_bscan=false
CSET use_softbscan=false
CSET use_unused_bscan=false
@@ -53,4 +53,4 @@ CSET user_scan_chain=USER1
MISC pkg_timestamp=2012-12-18T02:47:25Z
# END Extra information
GENERATE
# CRC: 865957ec
# CRC: 5ccf4baf
top/b200/coregen/chipscope_icon.xise
+2 -2
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@@ -51,8 +51,8 @@
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="chipscope_icon" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-03-08T11:51:40" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BD46AAD29AD5653980780005171DAA9E" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-10-22T17:05:01" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="154D57BA825522169EAB357B0FF9F497" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
top/b200/coregen/chipscope_icon_readme.txt
+1 -1
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@@ -1,5 +1,5 @@
The following files were generated for 'chipscope_icon' in directory
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b200/coregen/
/home/ianb/fpgadev/usrp3/top/b200/coregen/
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
top/b200/coregen/chipscope_ila_128.cdc
+1 -1
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@@ -1,5 +1,5 @@
#ChipScope Core Generator Project File Version 3.0
#Fri Mar 08 11:53:53 PST 2013
#Tue Oct 22 15:45:46 PDT 2013
SignalExport.bus<0000>.channelList=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
SignalExport.bus<0000>.name=TRIG0
SignalExport.bus<0000>.offset=0.0
top/b200/coregen/chipscope_ila_128.ngc
+1 -1
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File diff suppressed because one or more lines are too long
top/b200/coregen/chipscope_ila_128.v
+1 -1
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@@ -8,7 +8,7 @@
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : chipscope_ila_128.v
// /___/ /\ Timestamp : Fri Mar 08 11:53:53 PST 2013
// /___/ /\ Timestamp : Tue Oct 22 15:45:46 PDT 2013
// \ \ / \
// \___\/\___\
//
top/b200/coregen/chipscope_ila_128.veo
+1 -1
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@@ -8,7 +8,7 @@
// \ \ \/ Version : 14.4
// \ \ Application: Xilinx CORE Generator
// / / Filename : chipscope_ila_128.veo
// /___/ /\ Timestamp : Fri Mar 08 11:53:53 PST 2013
// /___/ /\ Timestamp : Tue Oct 22 15:45:46 PDT 2013
// \ \ / \
// \___\/\___\
//
top/b200/coregen/chipscope_ila_128.xco
+4 -4
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@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Fri Mar 8 19:52:17 2013
# Date: Tue Oct 22 22:44:09 2013
#
##############################################################
#
@@ -30,7 +30,7 @@ SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET simulationfiles = Structural
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = false
@@ -112,7 +112,7 @@ CSET match_units_6=1
CSET match_units_7=1
CSET match_units_8=1
CSET match_units_9=1
CSET max_sequence_levels=1
CSET max_sequence_levels=2
CSET number_of_trigger_ports=1
CSET sample_data_depth=1024
CSET sample_on=Rising
@@ -138,4 +138,4 @@ CSET use_rpms=false
MISC pkg_timestamp=2012-12-18T02:47:40Z
# END Extra information
GENERATE
# CRC: 194c140a
# CRC: e17f8549
top/b200/coregen/chipscope_ila_128.xise
+4 -4
View File
@@ -17,11 +17,11 @@
<files>
<file xil_pn:name="chipscope_ila_128.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="chipscope_ila_128.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
@@ -51,8 +51,8 @@
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="chipscope_ila_128" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-03-08T11:53:54" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="9340B6BAD141C451B74411D3998AD5A4" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-10-22T15:45:48" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="7648BEB3D1E056005214224EBE9A99B3" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
top/b200/coregen/chipscope_ila_128_readme.txt
+1 -1
View File
@@ -1,5 +1,5 @@
The following files were generated for 'chipscope_ila_128' in directory
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b200/coregen/
/home/ianb/fpgadev/usrp3/top/b200/coregen/
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
top/b200/coregen/coregen.cgp
+1 -2
View File
@@ -1,10 +1,9 @@
SET busformat = BusFormatAngleBracketNotRipped
SET designentry = Verilog
SET device = xc6slx75
SET device = xc6slx150
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET package = fgg484
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = false
top/b200/radio_b200.v
+22 -54
View File
@@ -1,14 +1,27 @@
//
// Copyright 2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// radio top level module for b200
// Contains all clock-rate DSP components, all radio and hardware controls and settings
module radio_b200
#(
parameter FIFO_SIZE = 13
parameter RADIO_FIFO_SIZE = 13,
parameter SAMPLE_FIFO_SIZE = 11
)
(input radio_clk, input radio_rst,
input [31:0] rx, output [31:0] tx,
@@ -20,7 +33,7 @@ module radio_b200
input [63:0] ctrl_tdata, input ctrl_tlast, input ctrl_tvalid, output ctrl_tready,
output [63:0] resp_tdata, output resp_tlast, output resp_tvalid, input resp_tready,
output [31:0] debug
output [63:0] debug
);
// ///////////////////////////////////////////////////////////////////////////////
@@ -66,7 +79,7 @@ module radio_b200
.i_aclk(bus_clk), .i_tvalid(ctrl_tvalid), .i_tready(ctrl_tready), .i_tdata({ctrl_tlast, ctrl_tdata}),
.o_aclk(radio_clk), .o_tvalid(ctrl_tvalid_r), .o_tready(ctrl_tready_r), .o_tdata({ctrl_tlast_r, ctrl_tdata_r}));
axi_fifo_2clk #(.WIDTH(65), .SIZE(FIFO_SIZE)) tx_fifo
axi_fifo_2clk #(.WIDTH(65), .SIZE(RADIO_FIFO_SIZE)) tx_fifo
(.reset(bus_rst),
.i_aclk(bus_clk), .i_tvalid(tx_tvalid), .i_tready(tx_tready), .i_tdata({tx_tlast, tx_tdata}),
.o_aclk(radio_clk), .o_tvalid(tx_tvalid_r), .o_tready(tx_tready_r), .o_tdata({tx_tlast_r, tx_tdata_r}));
@@ -76,7 +89,7 @@ module radio_b200
.i_aclk(radio_clk), .i_tvalid(rmux_tvalid_r), .i_tready(rmux_tready_r), .i_tdata({rmux_tlast_r, rmux_tdata_r}),
.o_aclk(bus_clk), .o_tvalid(resp_tvalid), .o_tready(resp_tready), .o_tdata({resp_tlast, resp_tdata}));
axi_fifo_2clk #(.WIDTH(65), .SIZE(FIFO_SIZE)) rx_fifo
axi_fifo_2clk #(.WIDTH(65), .SIZE(RADIO_FIFO_SIZE)) rx_fifo
(.reset(radio_rst),
.i_aclk(radio_clk), .i_tvalid(rx_mux_tvalid_r), .i_tready(rx_mux_tready_r), .i_tdata({rx_mux_tlast_r, rx_mux_tdata_r}),
.o_aclk(bus_clk), .o_tvalid(rx_tvalid), .o_tready(rx_tready), .o_tdata({rx_tlast, rx_tdata}));
@@ -162,6 +175,8 @@ module radio_b200
wire [31:0] sid;
wire [23:0] tx_fe_i, tx_fe_q;
wire [31:0] debug_tx_control;
assign tx[31:16] = (run_tx)? tx_fe_i[23:8] : tx_idle[31:16];
assign tx[15:0] = (run_tx)? tx_fe_q[23:8] : tx_idle[15:0];
@@ -180,7 +195,7 @@ module radio_b200
.seqnum(seqnum), .error_code(error_code), .sid(sid),
.sample_tdata(txsample_tdata), .sample_tvalid(txsample_tvalid), .sample_tready(txsample_tready),
.sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
.debug());
.debug(debug_tx_control));
tx_responder #(.BASE(SR_TX_CTRL+2)) tx_responder
(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
@@ -213,7 +228,7 @@ module radio_b200
wire [11:0] rx_seqnum;
wire [63:0] rx_tdata_i; wire rx_tlast_i, rx_tvalid_i, rx_tready_i;
new_rx_framer #(.BASE(SR_RX_CTRL+4)) new_rx_framer
new_rx_framer #(.BASE(SR_RX_CTRL+4),.SAMPLE_FIFO_SIZE(SAMPLE_FIFO_SIZE)) new_rx_framer
(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.vita_time(vita_time),
@@ -266,53 +281,6 @@ module radio_b200
.i3_tdata(), .i3_tlast(), .i3_tvalid(1'b0), .i3_tready(),
.o_tdata(rmux_tdata_r), .o_tlast(rmux_tlast_r), .o_tvalid(rmux_tvalid_r), .o_tready(rmux_tready_r));
wire [255:0] debug1;
reg [255:0] debug2;
/* -----\/----- EXCLUDED -----\/-----
always @(posedge radio_clk)
debug2 <= debug1;
wire [35:0] CONTROL0,CONTROL1;
chipscope_ila_256 chipscope_ila_256(
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.CLK(radio_clk), // IN
.TRIG0(debug2) // IN BUS [31:0]
);
chipscope_ila_32 chipscope_ila_32(
.CONTROL(CONTROL1), // INOUT BUS [35:0]
.CLK(radio_clk), // IN
.TRIG0(32'd0) // IN BUS [31:0]
);
chipscope_icon chipscope_icon(
.CONTROL0(CONTROL0), // INOUT BUS [35:0]
.CONTROL1(CONTROL1) // INOUT BUS [35:0]
);
assign debug1 = {
debug_tx_framer, // [214:206]
debug_tx_control, // [205:177]
set_data, // [176:145]
set_addr, // [144:137]
set_stb, // [136]
run_tx, // [135]
run_rx, // [134]
tx_tlast, // [133]
tx_tready, // [132]
tx_tvalid, // [131]
ctrl_tlast, // [130]
ctrl_tready, // [129]
ctrl_tvalid, // [128]
tx_tdata, // [127:64]
ctrl_tdata // [63:0]
};
-----/\----- EXCLUDED -----/\----- */
endmodule // radio_b200
top/b200/timing.ucf
+22 -17
View File
@@ -20,21 +20,26 @@ TIMESPEC "TS_codec_data_clk_p" = PERIOD "codec_data_clk_p" 16276 ps HIGH 50 %;
INST "GPIF_*" IOB = TRUE;
#low speed misc output group
INST "SFDX*" TNM = ls_misc_out;
INST "SRX*" TNM = ls_misc_out;
INST "LED_*" TNM = ls_misc_out;
INST "tx_enable*" TNM = ls_misc_out;
INST "tx_bandsel_*" TNM = ls_misc_out;
INST "rx_bandsel_*" TNM = ls_misc_out;
INST "ref_sel" TNM = ls_misc_out;
INST "*_ce" TNM = ls_misc_out;
INST "*_miso" TNM = ls_misc_out;
INST "*_mosi" TNM = ls_misc_out;
INST "*_sclk" TNM = ls_misc_out;
INST "gps_*" TNM = ls_misc_out;
INST "FPGA_*D0" TNM = ls_misc_out;
INST "SFDX*" TNM = radio_misc_out; # Radio Clk domain
INST "SRX*" TNM = radio_misc_out; # Radio Clk domain
INST "LED_*" TNM = radio_misc_out; # Radio Clk domain
INST "tx_enable*" TNM = radio_misc_out; # Radio Clk domain
INST "tx_bandsel_*" TNM = ls_misc_out; # Bus clk domain
INST "rx_bandsel_*" TNM = ls_misc_out; # Bus clk domain
INST "ref_sel" TNM = ls_misc_out; # Bus clk domain
INST "pll_ce" TNM = ls_misc_out; # Bus clk domain
INST "cat_ce" TNM = ls_misc_out; # Bus clk domain + combinatorial
#INST "fx3_miso" TNM = ls_misc_out; # Combinatorial
INST "cat_miso" TNM = ls_misc_out; # Bus clk domain (I)
INST "cat_mosi" TNM = ls_misc_out; # Bus clk domain + combinatorial
INST "pll_mosi" TNM = ls_misc_out; # Bus clk domain + combinatorial
INST "*_sclk" TNM = ls_misc_out; # Bus clk domain + combinatorial
INST "gps_*" TNM = ls_misc_out; # Bus clk domain
#INST "FPGA_*D0" TNM = ls_misc_out; # UNUSED
#constrain the misc IOs to the clocks
NET "gpif_clk" TNM_NET = "gpif_clk";
TIMESPEC "TS_gpif_clk" = PERIOD "gpif_clk" 10 ns HIGH 50 %;
TIMEGRP "ls_misc_out" OFFSET = OUT 15 ns AFTER "gpif_clk" RISING;
TIMEGRP "radio_misc_out" OFFSET = OUT 15 ns AFTER "radio_clk" RISING;
#constrain the misc IOs to the bus clock
NET "bus_clk" TNM_NET = "bus_clk";
TIMESPEC "TS_bus_clk" = PERIOD "bus_clk" 10 ns HIGH 50 %;
TIMEGRP "ls_misc_out" OFFSET = OUT 15 ns AFTER "bus_clk" RISING;
top/python/check_inout.py
+13 -2
View File
@@ -2,8 +2,19 @@
#
# Copyright 2010 Ettus Research LLC
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
# Description:
# generates a list of inputs and outputs from the top-level Verilog file and cross-references them to the .ucf.
# outputs errors for pins that aren't found in the UCF, checks for capitalization errors and other common mistakes
top/python/check_timing.py
+12
View File
@@ -2,6 +2,18 @@
#
# Copyright 2011-2012 Ettus Research LLC
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
import sys
import re
top/python/make_lvbitx.py
+13
View File
@@ -2,6 +2,19 @@
#
# Copyright 2012 Ettus Research LLC
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
import xml.etree.ElementTree as et
top/tcl/ise_helper.tcl
+15
View File
@@ -1,6 +1,21 @@
#
# Copyright 2008 Ettus Research LLC
#
# GNU Radio is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3, or (at your option)
# any later version.
#
# GNU Radio is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with GNU Radio; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
#
proc set_props {process options} {
if ![string compare $options ""] {