b2xx: Updating FPGA source with recent bugfixes.
Original-commit: 4b4365a517938b365af57674a3ab1462432c2c3a
This commit is contained in:
Ben Hilburn
+219
-180
@@ -1,221 +1,260 @@
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//
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// Copyright 2013 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module chdr_16sc_to_12sc
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#(parameter BASE=0)
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( input set_stb, input [7:0] set_addr, input [31:0] set_data,
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//left side of device
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input clk, input reset,
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(
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// Clocks and resets
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input clk,
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input reset,
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// Settings bus
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input set_stb,
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input [7:0] set_addr,
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input [31:0] set_data,
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// Input CHDR bus
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input [63:0] i_tdata,
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input i_tlast,
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input i_tvalid,
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output i_tready,
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//right side of device
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output reg [63:0] o_tdata = 0,
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// Output CHDR bus
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output reg [63:0] o_tdata,
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output o_tlast,
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output o_tvalid,
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input o_tready,
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// Debug
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output [31:0] debug
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);
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wire chdr_has_hdr = 1'b1;
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wire chdr_has_time = i_tdata[61];
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wire chdr_has_tlr = 1'b0;
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);
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wire [11:0] imag0;
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wire [11:0] real0;
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wire [11:0] imag1;
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wire [11:0] real1;
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wire [11:0] imag2;
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wire [11:0] real2;
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wire chdr_has_time = i_tdata[61];
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wire [16:0] round_i0;
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wire [16:0] round_r0;
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wire [16:0] round_i1;
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wire [16:0] round_r1;
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wire [16:0] round_i2;
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wire [16:0] round_r2;
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wire [11:0] q0;
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wire [11:0] i0;
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wire [11:0] q1;
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wire [11:0] i1;
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wire [11:0] q2;
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wire [11:0] i2;
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//pipiline registers
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wire [16:0] round_q0;
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wire [16:0] round_i0;
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wire [16:0] round_q1;
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wire [16:0] round_i1;
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wire [16:0] round_q2;
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wire [16:0] round_i2;
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reg [11:0] imag0_out;
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reg [11:0] real0_out;
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reg [11:0] imag1_out;
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reg [11:0] real1_out;
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// Pipeline registers
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reg [11:0] q0_out;
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reg [11:0] i0_out;
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reg [11:0] q1_out;
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reg [11:0] i1_out;
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reg [15:0] len_data;
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// CHDR has either 8 bytes of header or 16 if VITA time is included.
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wire [15:0] chdr_header_lines = chdr_has_time? 16 : 8;
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// Calculate size of samples input in bytes by taking CHDR size filed and subtracting header length.
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wire [15:0] sample_byte_count_in = i_tdata[47:32] - chdr_header_lines;
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// Calculate size of samples to be output by taking input size and scaling by 3/4
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wire [15:0] sample_byte_count_out = (sample_byte_count_in*3) >> 2;
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// Calculate size of output CHDR packet by adding back header size to new payload size.
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wire [15:0] output_chdr_pkt_size = sample_byte_count_out + chdr_header_lines;
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//chdr length calculations
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wire [15:0] chdr_header_lines = chdr_has_time? 16 : 8;
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wire [15:0] in_samples = i_tdata[47:32] - chdr_header_lines;
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wire [15:0] samples = (in_samples*3) >> 2;
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wire [15:0] chdr_payload_lines = samples + chdr_header_lines;
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reg needs_extra_line;
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reg in_extra_line;
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wire set_sid;
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wire [15:0] new_sid_dst;
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reg needs_exline = 0;
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reg in_exline = 0;
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wire set_sid;
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wire [15:0] my_newhome;
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setting_reg #(.my_addr(BASE), .width(17)) new_destination
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(.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
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.out({set_sid, my_newhome[15:0]}));
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//state machine
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.out({set_sid, new_sid_dst[15:0]}));
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// state machine
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localparam HEADER = 3'd0; // IDLE
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localparam TIME = 3'd1;
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localparam LINE_ODD_ZERO = 3'd2;
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localparam LINE_EVEN_ONE = 3'd3;
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localparam LINE_ODD_TWO = 3'd4;
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localparam REG_STATE = 3'd5;
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reg [2:0] state;
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always @(posedge clk) begin
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if (reset) begin
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state <= HEADER;
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needs_exline <= 0;
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in_exline <= 0;
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end
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localparam HEADER = 3'd0;
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localparam TIME = 3'd1;
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localparam SAMPLE1 = 3'd2;
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localparam SAMPLE2 = 3'd3;
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localparam SAMPLE3 = 3'd4;
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localparam SAMPLE4 = 3'd5;
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else if ((o_tvalid && o_tready) || (i_tready && i_tvalid)) case(state)
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reg [2:0] state;
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HEADER: begin
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needs_exline <= (in_samples[4:2] == 3 || in_samples[4:2] == 4 || in_samples[4:2] == 6);
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state <= (i_tdata[61])? TIME: REG_STATE;
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end
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always @(posedge clk)
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if (reset) begin
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state <= HEADER;
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needs_extra_line <= 0;
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in_extra_line <= 0;
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end else begin
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case(state)
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//
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// Process Header line of input packet or idle in this state waiting for new packet.
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// If the the input packet has SAMPLE_COUNT MODULO 8 == 3 or 4 or 6 then when tlast is asserted we will need one more
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// output cycle to finish outputing processed samples.
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//
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HEADER: begin
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if (o_tready && i_tvalid)
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begin
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needs_extra_line <= (sample_byte_count_in[4:2] == 3 || sample_byte_count_in[4:2] == 4 || sample_byte_count_in[4:2] == 6);
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// If the input packet had time, then add time to output packet
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state <= (i_tdata[61])? TIME: SAMPLE1;
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end
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end
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//
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// Process time field of input packet
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//
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TIME: begin
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if (o_tready && i_tvalid)
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begin
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// If we get a premature end of line go back to searching for start of new packet.
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state <= (i_tlast) ? HEADER: SAMPLE1;
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end
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end
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//
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// Process line of sample data from input packet.
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// Not yet enough data to prepare first of three repeating output lines
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// unless this the last line of a packet when the lats output line
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// is composed of data from one or both samples in this input packet.
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//
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SAMPLE1: begin
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if ((i_tlast && !needs_extra_line && o_tready && i_tvalid) || (in_extra_line && o_tready)) begin
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// We can finish this packet immediately.
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state <= HEADER;
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in_extra_line <= 0;
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end else if (i_tlast && needs_extra_line && o_tready && i_tvalid) begin
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// We still need one more output line to drain all samples into this packet.
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// (SHOULD NOT BE POSSIBLE TO GET HERE!)
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state <= SAMPLE2;
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in_extra_line <= 1;
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end else if (o_tready && i_tvalid)
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state <= SAMPLE2;
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end
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//
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// First of three repeating output line patterns
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//
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SAMPLE2: begin
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if ((i_tlast && !needs_extra_line && o_tready && i_tvalid) || (in_extra_line && o_tready)) begin
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// We can finish this packet immediately.
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state <= HEADER;
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in_extra_line <= 0;
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end else if (i_tlast && needs_extra_line && o_tready && i_tvalid) begin
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// We still need one more output line to drain all samples into this packet.
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state <= SAMPLE3;
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in_extra_line <= 1;
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end else if (o_tready && i_tvalid)
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state <= SAMPLE3;
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end
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//
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// Second of three repeating output line patterns
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//
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SAMPLE3: begin
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if ((i_tlast && !needs_extra_line && o_tready && i_tvalid) || (in_extra_line && o_tready)) begin
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// We can finish this packet immediately.
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state <= HEADER;
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in_extra_line <= 0;
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end else if (i_tlast && needs_extra_line && o_tready && i_tvalid) begin
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// We still need one more output line to drain all samples into this packet.
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state <= SAMPLE4;
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in_extra_line <= 1;
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end else if (o_tready && i_tvalid)
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state <= SAMPLE4;
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end
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//
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// Third of three repeating output line patterns
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//
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SAMPLE4: begin
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if ((i_tlast && !needs_extra_line && o_tready && i_tvalid) || (in_extra_line && o_tready)) begin
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// We can finish this packet immediately.
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state <= HEADER;
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in_extra_line <= 0;
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end else if (i_tlast && needs_extra_line && o_tready && i_tvalid) begin
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// We still need one more output line to drain all samples into this packet.
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// (SHOULD NOT BE POSSIBLE TO GET HERE!!)
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state <= SAMPLE1;
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in_extra_line <= 1;
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end else if (o_tready && i_tvalid)
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state <= SAMPLE1;
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end
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//
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// Should never get here.
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//
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default: state <= HEADER;
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TIME: begin
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state <= (i_tlast) ? HEADER: REG_STATE;
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end
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REG_STATE: begin
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if (i_tlast & !needs_exline || in_exline) begin
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state <= HEADER;
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in_exline <= 0;
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end
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else if (i_tlast & needs_exline) begin
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state <= LINE_EVEN_ONE;
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in_exline <= 1;
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end
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else
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state <= LINE_EVEN_ONE;
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end
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endcase
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end
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LINE_EVEN_ONE: begin
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if (i_tlast & !needs_exline || in_exline) begin
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state <= HEADER;
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in_exline <= 0;
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end
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else if (i_tlast & needs_exline) begin
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state <= LINE_ODD_TWO;
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in_exline <= 1;
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end
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else
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state <= LINE_ODD_TWO;
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end
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// Add rounding value into 16bit samples before trunctaion
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assign round_q0 = ({i_tdata[63],i_tdata[63:48]} + 'h0008);
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assign round_i0 = ({i_tdata[47],i_tdata[47:32]} + 'h0008);
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// Truncate with saturation to 12bits precision.
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assign q0 = (round_q0[16:15] == 2'b01) ? 12'h7FF : ((round_q0[16:15] == 2'b10) ? 12'h800 : round_q0[15:4]);
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assign i0 = (round_i0[16:15] == 2'b01) ? 12'h7FF : ((round_i0[16:15] == 2'b10) ? 12'h800 : round_i0[15:4]);
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// Add rounding value into 16bit samples before trunctaion
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assign round_q1 = ({i_tdata[31],i_tdata[31:16]} + 'h0008);
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assign round_i1 = ({i_tdata[15],i_tdata[15:0]} + 'h0008);
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// Truncate with saturation to 12bits precision.
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assign q1 = (round_q1[16:15] == 2'b01) ? 12'h7FF : ((round_q1[16:15] == 2'b10) ? 12'h800 : round_q1[15:4]);
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assign i1 = (round_i1[16:15] == 2'b01) ? 12'h7FF : ((round_i1[16:15] == 2'b10) ? 12'h800 : round_i1[15:4]);
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LINE_ODD_TWO: begin
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if (i_tlast & !needs_exline || in_exline) begin
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state <= HEADER;
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in_exline <= 0;
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end
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else if (i_tlast & needs_exline) begin
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state <= LINE_ODD_ZERO;
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in_exline <= 1;
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end
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else
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state <= LINE_ODD_ZERO;
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end
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LINE_ODD_ZERO: begin
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if (i_tlast & !needs_exline || in_exline) begin
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state <= HEADER;
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in_exline <= 0;
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end
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else if (i_tlast & needs_exline) begin
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state <= REG_STATE;
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in_exline <= 1;
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end
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else
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state <= REG_STATE;
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end
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default: state <= HEADER;
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endcase
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end
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assign round_i0 = ({i_tdata[63],i_tdata[63:48]} + 'h0008);
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assign round_r0 = ({i_tdata[47],i_tdata[47:32]} + 'h0008);
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assign imag0 = (round_i0[16] == 0 && round_i0[15] == 1)?(12'h7FF):(round_i0[16] == 1 && round_i0[15] == 0)? (12'h800):(round_i0[15:4]);
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assign real0 = (round_r0[16] == 0 && round_r0[15] == 1)?(12'h7FF):(round_r0[16] == 1 && round_r0[15] == 0)? (12'h800):(round_r0[15:4]);
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assign round_i1 = ({i_tdata[31],i_tdata[31:16]} + 'h0008);
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assign round_r1 = ({i_tdata[15],i_tdata[15:0]} + 'h0008);
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assign imag1 = (round_i1[16] == 0 && round_i1[15] == 1)?(12'h7FF):(round_i1[16] == 1 && round_i1[15] == 0)? (12'h800):(round_i1[15:4]);
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assign real1 = (round_r1[16] == 0 && round_r1[15] == 1)?(12'h7FF):(round_r1[16] == 1 && round_r1[15] == 0)? (12'h800):(round_r1[15:4]);
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//
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// Keep values from current input line to populate fields in next cycles output line
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//
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always @(posedge clk)
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if (i_tvalid && o_tready)
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begin
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imag0_out <= imag0;
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real0_out <= real0;
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imag1_out <= imag1;
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real1_out <= real1;
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q0_out <= q0;
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i0_out <= i0;
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q1_out <= q1;
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i1_out <= i1;
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end
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//
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// Mux Output data
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//
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always @(*)
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case(state)
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HEADER: o_tdata <= {i_tdata[63:48], chdr_payload_lines,
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set_sid ? {i_tdata[15:0], my_newhome[15:0]}:i_tdata[31:0]};
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TIME: o_tdata <= i_tdata;
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// Populate header with CHDR fields
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HEADER: o_tdata = {i_tdata[63:48], output_chdr_pkt_size,
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set_sid ? {i_tdata[15:0], new_sid_dst[15:0]}:i_tdata[31:0]};
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// Add 64bit VITA time to packet
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TIME: o_tdata = i_tdata;
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// Special ending corner case for input packets with SAMPLE_COUNT MODULO 8 == (1 | 2)
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SAMPLE1: o_tdata = {q0,i0,q1, i1, 16'b0};
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// Line one of repeating 12bit packed data pattern
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SAMPLE2: o_tdata = {q0_out, i0_out, q1_out, i1_out, q0, i0[11:8]};
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// Line two of repeating 12bit packed data pattern
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SAMPLE3: o_tdata = {i0_out[7:0], q1_out, i1_out, q0, i0,q1[11:4]};
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// Line three of repeating 12bit packed data pattern
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SAMPLE4: o_tdata = {q1_out[3:0], i1_out, q0, i0, q1, i1};
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default : o_tdata = i_tdata;
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endcase // case(state)
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REG_STATE: o_tdata <= {imag0,real0,imag1, real1, 16'b0};
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LINE_EVEN_ONE: o_tdata <= {imag0_out, real0_out, imag1_out, real1_out, imag0, real0[11:8]};
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LINE_ODD_TWO: o_tdata <= {real0_out[7:0], imag1_out, real1_out, imag0, real0,imag1[11:4]};
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LINE_ODD_ZERO: o_tdata <= {imag1_out[3:0], real1_out, imag0, real0, imag1, real1};
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default : o_tdata <= i_tdata;
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endcase
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assign o_tvalid =((in_exline) || (state != REG_STATE & i_tvalid) || (i_tlast & i_tvalid & !needs_exline));
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assign i_tready = (o_tready & !in_exline)||(state == REG_STATE && !i_tlast);
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assign o_tlast = (needs_exline)? in_exline: i_tlast;
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assign o_tvalid =
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// We are outputing the (extra) last line of a packet
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in_extra_line ||
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// When not in the SAMPLE1 state and there's new input data (Unless its the last line....)
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(state != SAMPLE1 & i_tvalid) ||
|
||||
// Last line of input packet and we can finish this cycle. (Includes when state is SAMPLE1)
|
||||
(i_tlast & i_tvalid & !needs_extra_line);
|
||||
|
||||
assign i_tready =
|
||||
// Downstream is ready and we are not currently outputing last (extra) line of packet.
|
||||
(o_tready && !in_extra_line) ||
|
||||
// We don't create output data in SAMPLE1 unless its last line so don't need downstream ready to proceed.
|
||||
((state == SAMPLE1) && !i_tlast);
|
||||
|
||||
assign o_tlast = (needs_extra_line) ? in_extra_line : i_tlast;
|
||||
|
||||
endmodule
|
||||
|
||||
Reference in New Issue
Block a user