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b2xx: Updating FPGA source with recent bugfixes.

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Original-commit: 4b4365a517938b365af57674a3ab1462432c2c3a
This commit is contained in:
Ben Hilburn
2013-12-03 10:35:35 -08:00
parent c91b74de33
commit 29086f9001
103 changed files with 2001 additions and 608 deletions
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lib/packet_proc/cvita_chunker.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Quantize cvita packets to a configurable quantum value. o_tlast and
// i_tready will be held off until the entire quantized packet is xferred.
// If quantum is changed, it is the responsibility of the client to clear
lib/packet_proc/cvita_chunker_tb.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`timescale 500ps/1ps
lib/packet_proc/cvita_dechunker.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module cvita_dechunker # (
parameter PAD_VALUE = 64'hFFFFFFFF_FFFFFFFF
lib/packet_proc/cvita_dechunker_tb.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`timescale 500ps/1ps
lib/packet_proc/eth_dispatch.v
+12 -8
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@@ -72,6 +72,7 @@ module eth_dispatch
output xo_tvalid,
input xo_tready,
// Debug
output [2:0] debug_flags,
output [31:0] debug
);
@@ -93,6 +94,7 @@ module eth_dispatch
//
// Small RAM stores packet header during parsing.
//
// IJB consider changing HEADER_RAM_SIZE to 7
localparam HEADER_RAM_SIZE = 9;
(*ram_style="distributed"*)
reg [68:0] header_ram [HEADER_RAM_SIZE-1:0];
@@ -100,7 +102,7 @@ module eth_dispatch
reg drop_this_packet;
wire header_done = (header_ram_addr == HEADER_RAM_SIZE-1);
reg fwd_input;
reg fwd_input;
//
reg [63:0] in_tdata_reg;
@@ -112,10 +114,8 @@ module eth_dispatch
wire [3:0] out_tuser;
wire [63:0] out_tdata;
//
// Output AXI-STream interface to VITA Radio Core
// Output AXI-Stream interface to VITA Radio Core
wire [63:0] vita_pre_tdata;
wire [3:0] vita_pre_tuser;
wire vita_pre_tlast;
@@ -147,10 +147,6 @@ module eth_dispatch
reg is_icmp_no_fwd;
reg is_chdr;
//
// Settings regs
//
@@ -417,12 +413,14 @@ module eth_dispatch
end
7: begin
// Look for a possible CHDR header string
// IJB. NOTE this is not a good test for a CHDR packet, we perhaps don;t need this state anyhow.
if (in_tdata_reg[63:32] != 32'h0)
is_chdr <= 1'b1;
end
8: begin
// Check VRT Stream ID
// ADD THIS HERE.
// IJB. Perhaps delete this state.
end
endcase // case (header_ram_addr)
end // if (in_tvalid && in_tready)
@@ -452,9 +450,12 @@ module eth_dispatch
(out_tready && fwd_input);
//
// Because we can forward to both the ZPU and XO FIFO's concurrently
// we have to make sure both can accept data in the same cycle.
// This makes it possible for either destination to block the other.
// Make sure (both) destination(s) can accept data before passing it.
//
assign xo_pre_tvalid = out_tvalid &&
((state == FORWARD_XO) ||
((state == FORWARD_ZPU_AND_XO) && zpu_pre_tready));
@@ -524,6 +525,9 @@ module eth_dispatch
.space(),
.occupied()
);
assign debug_flags = {vita_pre_tready,xo_pre_tready,zpu_pre_tready};
/* -----\/----- EXCLUDED -----\/-----
lib/packet_proc/eth_dispatch_tb.v
+13 -1
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@@ -1,7 +1,19 @@
//
// Copyright 2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`timescale 1 ps / 1 ps
module eth_dispatch_tb();
lib/packet_proc/eth_interface.v
+51 -4
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@@ -21,7 +21,8 @@ module eth_interface
// ZPU
output [63:0] e2z_tdata, output [3:0] e2z_tuser, output e2z_tlast, output e2z_tvalid, input e2z_tready,
input [63:0] z2e_tdata, input [3:0] z2e_tuser, input z2e_tlast, input z2e_tvalid, output z2e_tready,
// Debug
output [31:0] debug_flags,
output [31:0] debug
);
@@ -36,7 +37,12 @@ module eth_interface
wire [63:0] epg_tdata_int;
wire [3:0] epg_tuser_int;
wire epg_tlast_int, epg_tvalid_int, epg_tready_int;
//
// Packet gate ensures on entire ingressing packet is buffered before feeding it downstream so that it bursts
// efficiently internally without holding resources allocted for longer than optimal. This also means that an upstream
// error discovered in the packet can allow the packet to be destroyed here, before it gets deeper into the USRP.
//
axi_packet_gate #(.WIDTH(68), .SIZE(10)) packet_gater //holds 8K pkts
(.clk(clk), .reset(reset), .clear(clear),
@@ -47,10 +53,14 @@ module eth_interface
.o_tdata({epg_tuser_int, epg_tdata_int}), .o_tlast(epg_tlast_int),
.o_tvalid(epg_tvalid_int), .o_tready(epg_tready_int));
//
// Based on programmed rules, parse network headers and decide which internal destination(s) this packet will be forwarded to.
//
wire [63:0] e2z_tdata_int;
wire [3:0] e2z_tuser_int;
wire e2z_tlast_int, e2z_tvalid_int, e2z_tready_int;
wire [2:0] dispatch_debug_flags;
eth_dispatch #(.BASE(BASE+8)) eth_dispatch
(.clk(clk), .reset(reset), .clear(clear),
.set_stb(set_stb), .set_addr(set_addr) , .set_data(set_data),
@@ -58,8 +68,11 @@ module eth_interface
.vita_tdata(e2v_tdata), .vita_tlast(e2v_tlast), .vita_tvalid(e2v_tvalid), .vita_tready(e2v_tready),
.zpu_tdata(e2z_tdata_int), .zpu_tuser(e2z_tuser_int), .zpu_tlast(e2z_tlast_int), .zpu_tvalid(e2z_tvalid_int), .zpu_tready(e2z_tready_int),
.xo_tdata(xo_tdata), .xo_tuser(xo_tuser), .xo_tlast(xo_tlast), .xo_tvalid(xo_tvalid), .xo_tready(xo_tready), // to other eth port
.debug(debug));
.debug_flags(dispatch_debug_flags),.debug(debug));
//
// ZPU can be slow to respond (relative to packet wirespeed) so extra buffer for packets destined there so it doesn't back up.
//
axi_fifo #(.WIDTH(69),.SIZE(ZPU_FIFOSIZE)) zpu_fifo
(.clk(clk), .reset(reset), .clear(clear),
.i_tdata({e2z_tlast_int,e2z_tuser_int,e2z_tdata_int}), .i_tvalid(e2z_tvalid_int), .i_tready(e2z_tready_int),
@@ -110,4 +123,38 @@ module eth_interface
.i_tdata({eth_tx_tlast_int,eth_tx_tuser_int,eth_tx_tdata_int}), .i_tvalid(eth_tx_tvalid_int), .i_tready(eth_tx_tready_int),
.o_tdata({eth_tx_tlast,eth_tx_tuser,eth_tx_tdata}), .o_tvalid(eth_tx_tvalid), .o_tready(eth_tx_tready));
//
// Provide instrumentation so that abnormal FIFO conditions can be identifed.
//
/* -----\/----- EXCLUDED -----\/-----
setting_reg #(.my_addr(BASE+15), .awidth(16), .width(1)) sr_reset_fifo_debug
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(),.changed(clear_debug_flags));
always @(posedge clk)
if (reset)
debug_flags <= 0;
else if (clear_debug_flags)
debug_flags <= 0;
else
debug_flags <= debug_flags | {eth_rx_tuser[3],
~eth_tx_tready_int,
~xi_tready,
~v2e_tready,
~e2z_tready_int,
~eth_rx_tready,
~dispatch_debug_flags[2:0]};
-----/\----- EXCLUDED -----/\----- */
assign debug_flags = {eth_rx_tuser[3],
~eth_tx_tready_int,
~xi_tready,
~v2e_tready,
~e2z_tready_int,
~eth_rx_tready,
~dispatch_debug_flags[2:0]};
endmodule // eth_interface