fpga: n3xx: Add CE clock

Adds a 266.667 MHz compute engine clock and uses it instead of the radio clock for the DDC and DUC. Using a faster clock than the radio allows the DDC and DUC to drain after a stall in the data flow. Original-commit: ff55d406a02cc934a5c238d22c836bea08ade3d1
2023-10-18 22:23:55 -05:00
parent e4d9a9a448
commit 2612487d43
12 changed files with 761 additions and 658 deletions
@@ -36,6 +36,7 @@ module n3xx_core #(
  input         bus_rst,
  input         ddr3_dma_clk,
  input         clk40,
+  input         ce_clk,

  // Clocking and PPS Controls/Indicators
  input            pps,
@@ -1138,6 +1139,7 @@ module n3xx_core #(
    .device_id               (device_id  ),
    .radio_clk               (radio_clk  ),
    .dram_clk                (ddr3_dma_clk),
+    .ce_clk                  (ce_clk),
    `ifndef N300
      .m_ctrlport_radio1_req_wr       (m_ctrlport_req_wr_radio1      ),
      .m_ctrlport_radio1_req_rd       (m_ctrlport_req_rd_radio1      ),