From 2612487d435850a92fb7e40296a1f73447ea173d Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Wed, 11 Oct 2023 16:42:01 -0500 Subject: [PATCH] fpga: n3xx: Add CE clock Adds a 266.667 MHz compute engine clock and uses it instead of the radio clock for the DDC and DUC. Using a faster clock than the radio allows the DDC and DUC to drain after a stall in the data flow. Original-commit: ff55d406a02cc934a5c238d22c836bea08ade3d1 --- top/n3xx/dboards/mg/n3xx.v | 4 + top/n3xx/dboards/rh/n3xx.v | 4 + top/n3xx/mb_clocks.xdc | 4 + top/n3xx/n300_bist_image_core.v | 201 ++++++++++++------------- top/n3xx/n300_rfnoc_image_core.v | 201 ++++++++++++------------- top/n3xx/n310_bist_image_core.v | 225 ++++++++++++++-------------- top/n3xx/n310_rfnoc_image_core.v | 225 ++++++++++++++-------------- top/n3xx/n320_bist_image_core.v | 225 ++++++++++++++-------------- top/n3xx/n320_rfnoc_image_core.v | 233 +++++++++++++++-------------- top/n3xx/n320_rfnoc_image_core.yml | 8 +- top/n3xx/n3xx_clocking.v | 87 ++++++++++- top/n3xx/n3xx_core.v | 2 + 12 files changed, 761 insertions(+), 658 deletions(-) diff --git a/top/n3xx/dboards/mg/n3xx.v b/top/n3xx/dboards/mg/n3xx.v index ea55171..b60070a 100644 --- a/top/n3xx/dboards/mg/n3xx.v +++ b/top/n3xx/dboards/mg/n3xx.v @@ -737,6 +737,7 @@ module n3xx ( wire clk40; wire meas_clk_ref; wire bus_clk; + wire ce_clk; wire gige_refclk; wire gige_refclk_bufg; wire xgige_refclk; @@ -860,6 +861,8 @@ module n3xx ( .ddr3_dma_clk(ddr3_dma_clk), .misc_clks_reset(meas_clk_reset), .misc_clks_locked(meas_clk_locked), + .clk200(bus_clk), + .ce_clk(ce_clk), .ext_pps_from_pin(REF_1PPS_IN), .gps_pps_from_pin(GPS_1PPS), .pps_select(pps_select), @@ -3573,6 +3576,7 @@ module n3xx ( .bus_rst(bus_rst), .ddr3_dma_clk(ddr3_dma_clk), .clk40(clk40), + .ce_clk(ce_clk), // Clocking and PPS Controls/Indicators .pps(pps_radioclk1x), diff --git a/top/n3xx/dboards/rh/n3xx.v b/top/n3xx/dboards/rh/n3xx.v index aa7f40e..8bf265c 100644 --- a/top/n3xx/dboards/rh/n3xx.v +++ b/top/n3xx/dboards/rh/n3xx.v @@ -724,6 +724,7 @@ module n3xx ( wire clk40; wire meas_clk_ref; wire bus_clk; + wire ce_clk; wire gige_refclk; wire gige_refclk_bufg; wire xgige_refclk; @@ -849,6 +850,8 @@ module n3xx ( .ddr3_dma_clk(ddr3_dma_clk), .misc_clks_reset(meas_clk_reset), .misc_clks_locked(meas_clk_locked), + .clk200(bus_clk), + .ce_clk(ce_clk), .ext_pps_from_pin(REF_1PPS_IN), .gps_pps_from_pin(GPS_1PPS), .pps_select(pps_select), @@ -3493,6 +3496,7 @@ module n3xx ( .bus_rst(bus_rst), .ddr3_dma_clk(ddr3_dma_clk), .clk40(clk40), + .ce_clk(ce_clk), // Clocking and PPS Controls/Indicators .pps(pps_radioclk1x), diff --git a/top/n3xx/mb_clocks.xdc b/top/n3xx/mb_clocks.xdc index 3073615..217e83e 100644 --- a/top/n3xx/mb_clocks.xdc +++ b/top/n3xx/mb_clocks.xdc @@ -64,6 +64,10 @@ set_input_jitter [get_clocks bus_clk] $bus_clk_jitter create_generated_clock -name meas_clk_fb [get_pins {n3xx_clocking_i/misc_clock_gen_i/inst/mmcm_adv_inst/CLKFBOUT}] create_generated_clock -name meas_clk [get_pins {n3xx_clocking_i/misc_clock_gen_i/inst/mmcm_adv_inst/CLKOUT0}] +# CE Clock +create_generated_clock -name ce_clk_fb [get_pins {n3xx_clocking_i/ce_clk_gen_i/CLKFBOUT}] +create_generated_clock -name ce_clk [get_pins {n3xx_clocking_i/ce_clk_gen_i/CLKOUT0}] + #******************************************************************************* ## White Rabbit DAC # Constrain the DIN and NSYNC bits around the clock output. No readback. diff --git a/top/n3xx/n300_bist_image_core.v b/top/n3xx/n300_bist_image_core.v index d73ef9c..b7ef8ca 100644 --- a/top/n3xx/n300_bist_image_core.v +++ b/top/n3xx/n300_bist_image_core.v @@ -35,6 +35,7 @@ module rfnoc_image_core #( input wire core_arst, input wire radio_clk, input wire dram_clk, + input wire ce_clk, // Basic input wire [ 15:0] device_id, @@ -54,58 +55,58 @@ module rfnoc_image_core #( // time input wire [ 63:0] radio_time, // radio0 - input wire [ 255:0] radio_rx_data_radio0, - input wire [ 7:0] radio_rx_stb_radio0, - output wire [ 7:0] radio_rx_running_radio0, - output wire [ 255:0] radio_tx_data_radio0, - input wire [ 7:0] radio_tx_stb_radio0, - output wire [ 7:0] radio_tx_running_radio0, + input wire [1023:0] radio_rx_data_radio0, + input wire [ 31:0] radio_rx_stb_radio0, + output wire [ 31:0] radio_rx_running_radio0, + output wire [1023:0] radio_tx_data_radio0, + input wire [ 31:0] radio_tx_stb_radio0, + output wire [ 31:0] radio_tx_running_radio0, // dram input wire [ 0:0] axi_rst, - output wire [ 3:0] m_axi_awid, - output wire [ 191:0] m_axi_awaddr, - output wire [ 31:0] m_axi_awlen, - output wire [ 11:0] m_axi_awsize, - output wire [ 7:0] m_axi_awburst, - output wire [ 3:0] m_axi_awlock, - output wire [ 15:0] m_axi_awcache, - output wire [ 11:0] m_axi_awprot, - output wire [ 15:0] m_axi_awqos, - output wire [ 15:0] m_axi_awregion, - output wire [ 3:0] m_axi_awuser, - output wire [ 3:0] m_axi_awvalid, - input wire [ 3:0] m_axi_awready, - output wire [2047:0] m_axi_wdata, - output wire [ 255:0] m_axi_wstrb, - output wire [ 3:0] m_axi_wlast, - output wire [ 3:0] m_axi_wuser, - output wire [ 3:0] m_axi_wvalid, - input wire [ 3:0] m_axi_wready, - input wire [ 3:0] m_axi_bid, - input wire [ 7:0] m_axi_bresp, - input wire [ 3:0] m_axi_buser, - input wire [ 3:0] m_axi_bvalid, - output wire [ 3:0] m_axi_bready, - output wire [ 3:0] m_axi_arid, - output wire [ 191:0] m_axi_araddr, - output wire [ 31:0] m_axi_arlen, - output wire [ 11:0] m_axi_arsize, - output wire [ 7:0] m_axi_arburst, - output wire [ 3:0] m_axi_arlock, - output wire [ 15:0] m_axi_arcache, - output wire [ 11:0] m_axi_arprot, - output wire [ 15:0] m_axi_arqos, - output wire [ 15:0] m_axi_arregion, - output wire [ 3:0] m_axi_aruser, - output wire [ 3:0] m_axi_arvalid, - input wire [ 3:0] m_axi_arready, - input wire [ 3:0] m_axi_rid, - input wire [2047:0] m_axi_rdata, - input wire [ 7:0] m_axi_rresp, - input wire [ 3:0] m_axi_rlast, - input wire [ 3:0] m_axi_ruser, - input wire [ 3:0] m_axi_rvalid, - output wire [ 3:0] m_axi_rready, + output wire [ 7:0] m_axi_awid, + output wire [ 383:0] m_axi_awaddr, + output wire [ 63:0] m_axi_awlen, + output wire [ 23:0] m_axi_awsize, + output wire [ 15:0] m_axi_awburst, + output wire [ 7:0] m_axi_awlock, + output wire [ 31:0] m_axi_awcache, + output wire [ 23:0] m_axi_awprot, + output wire [ 31:0] m_axi_awqos, + output wire [ 31:0] m_axi_awregion, + output wire [ 7:0] m_axi_awuser, + output wire [ 7:0] m_axi_awvalid, + input wire [ 7:0] m_axi_awready, + output wire [4191:0] m_axi_wdata, + output wire [ 511:0] m_axi_wstrb, + output wire [ 7:0] m_axi_wlast, + output wire [ 7:0] m_axi_wuser, + output wire [ 7:0] m_axi_wvalid, + input wire [ 7:0] m_axi_wready, + input wire [ 7:0] m_axi_bid, + input wire [ 15:0] m_axi_bresp, + input wire [ 7:0] m_axi_buser, + input wire [ 7:0] m_axi_bvalid, + output wire [ 7:0] m_axi_bready, + output wire [ 7:0] m_axi_arid, + output wire [ 383:0] m_axi_araddr, + output wire [ 63:0] m_axi_arlen, + output wire [ 23:0] m_axi_arsize, + output wire [ 15:0] m_axi_arburst, + output wire [ 7:0] m_axi_arlock, + output wire [ 31:0] m_axi_arcache, + output wire [ 31:0] m_axi_arprot, + output wire [ 31:0] m_axi_arqos, + output wire [ 31:0] m_axi_arregion, + output wire [ 7:0] m_axi_aruser, + output wire [ 7:0] m_axi_arvalid, + input wire [ 7:0] m_axi_arready, + input wire [ 7:0] m_axi_rid, + input wire [4191:0] m_axi_rdata, + input wire [ 15:0] m_axi_rresp, + input wire [ 7:0] m_axi_rlast, + input wire [ 7:0] m_axi_ruser, + input wire [ 7:0] m_axi_rvalid, + output wire [ 7:0] m_axi_rready, // Transport Adapters /////////////// @@ -633,12 +634,12 @@ module rfnoc_image_core #( // time wire [ 63:0] radio0_radio_time; // radio - wire [ 255:0] radio0_radio_rx_data; - wire [ 7:0] radio0_radio_rx_stb; - wire [ 7:0] radio0_radio_rx_running; - wire [ 255:0] radio0_radio_tx_data; - wire [ 7:0] radio0_radio_tx_stb; - wire [ 7:0] radio0_radio_tx_running; + wire [1023:0] radio0_radio_rx_data; + wire [ 31:0] radio0_radio_rx_stb; + wire [ 31:0] radio0_radio_rx_running; + wire [1023:0] radio0_radio_tx_data; + wire [ 31:0] radio0_radio_tx_stb; + wire [ 31:0] radio0_radio_tx_running; rfnoc_block_radio #( .THIS_PORTID (2), @@ -704,50 +705,50 @@ module rfnoc_image_core #( // axi_ram wire [ 0:0] fifo0_axi_rst; - wire [ 3:0] fifo0_m_axi_awid; - wire [ 191:0] fifo0_m_axi_awaddr; - wire [ 31:0] fifo0_m_axi_awlen; - wire [ 11:0] fifo0_m_axi_awsize; - wire [ 7:0] fifo0_m_axi_awburst; - wire [ 3:0] fifo0_m_axi_awlock; - wire [ 15:0] fifo0_m_axi_awcache; - wire [ 11:0] fifo0_m_axi_awprot; - wire [ 15:0] fifo0_m_axi_awqos; - wire [ 15:0] fifo0_m_axi_awregion; - wire [ 3:0] fifo0_m_axi_awuser; - wire [ 3:0] fifo0_m_axi_awvalid; - wire [ 3:0] fifo0_m_axi_awready; - wire [2047:0] fifo0_m_axi_wdata; - wire [ 255:0] fifo0_m_axi_wstrb; - wire [ 3:0] fifo0_m_axi_wlast; - wire [ 3:0] fifo0_m_axi_wuser; - wire [ 3:0] fifo0_m_axi_wvalid; - wire [ 3:0] fifo0_m_axi_wready; - wire [ 3:0] fifo0_m_axi_bid; - wire [ 7:0] fifo0_m_axi_bresp; - wire [ 3:0] fifo0_m_axi_buser; - wire [ 3:0] fifo0_m_axi_bvalid; - wire [ 3:0] fifo0_m_axi_bready; - wire [ 3:0] fifo0_m_axi_arid; - wire [ 191:0] fifo0_m_axi_araddr; - wire [ 31:0] fifo0_m_axi_arlen; - wire [ 11:0] fifo0_m_axi_arsize; - wire [ 7:0] fifo0_m_axi_arburst; - wire [ 3:0] fifo0_m_axi_arlock; - wire [ 15:0] fifo0_m_axi_arcache; - wire [ 11:0] fifo0_m_axi_arprot; - wire [ 15:0] fifo0_m_axi_arqos; - wire [ 15:0] fifo0_m_axi_arregion; - wire [ 3:0] fifo0_m_axi_aruser; - wire [ 3:0] fifo0_m_axi_arvalid; - wire [ 3:0] fifo0_m_axi_arready; - wire [ 3:0] fifo0_m_axi_rid; - wire [2047:0] fifo0_m_axi_rdata; - wire [ 7:0] fifo0_m_axi_rresp; - wire [ 3:0] fifo0_m_axi_rlast; - wire [ 3:0] fifo0_m_axi_ruser; - wire [ 3:0] fifo0_m_axi_rvalid; - wire [ 3:0] fifo0_m_axi_rready; + wire [ 7:0] fifo0_m_axi_awid; + wire [ 383:0] fifo0_m_axi_awaddr; + wire [ 63:0] fifo0_m_axi_awlen; + wire [ 23:0] fifo0_m_axi_awsize; + wire [ 15:0] fifo0_m_axi_awburst; + wire [ 7:0] fifo0_m_axi_awlock; + wire [ 31:0] fifo0_m_axi_awcache; + wire [ 23:0] fifo0_m_axi_awprot; + wire [ 31:0] fifo0_m_axi_awqos; + wire [ 31:0] fifo0_m_axi_awregion; + wire [ 7:0] fifo0_m_axi_awuser; + wire [ 7:0] fifo0_m_axi_awvalid; + wire [ 7:0] fifo0_m_axi_awready; + wire [4191:0] fifo0_m_axi_wdata; + wire [ 511:0] fifo0_m_axi_wstrb; + wire [ 7:0] fifo0_m_axi_wlast; + wire [ 7:0] fifo0_m_axi_wuser; + wire [ 7:0] fifo0_m_axi_wvalid; + wire [ 7:0] fifo0_m_axi_wready; + wire [ 7:0] fifo0_m_axi_bid; + wire [ 15:0] fifo0_m_axi_bresp; + wire [ 7:0] fifo0_m_axi_buser; + wire [ 7:0] fifo0_m_axi_bvalid; + wire [ 7:0] fifo0_m_axi_bready; + wire [ 7:0] fifo0_m_axi_arid; + wire [ 383:0] fifo0_m_axi_araddr; + wire [ 63:0] fifo0_m_axi_arlen; + wire [ 23:0] fifo0_m_axi_arsize; + wire [ 15:0] fifo0_m_axi_arburst; + wire [ 7:0] fifo0_m_axi_arlock; + wire [ 31:0] fifo0_m_axi_arcache; + wire [ 31:0] fifo0_m_axi_arprot; + wire [ 31:0] fifo0_m_axi_arqos; + wire [ 31:0] fifo0_m_axi_arregion; + wire [ 7:0] fifo0_m_axi_aruser; + wire [ 7:0] fifo0_m_axi_arvalid; + wire [ 7:0] fifo0_m_axi_arready; + wire [ 7:0] fifo0_m_axi_rid; + wire [4191:0] fifo0_m_axi_rdata; + wire [ 15:0] fifo0_m_axi_rresp; + wire [ 7:0] fifo0_m_axi_rlast; + wire [ 7:0] fifo0_m_axi_ruser; + wire [ 7:0] fifo0_m_axi_rvalid; + wire [ 7:0] fifo0_m_axi_rready; rfnoc_block_axi_ram_fifo #( .THIS_PORTID (3), diff --git a/top/n3xx/n300_rfnoc_image_core.v b/top/n3xx/n300_rfnoc_image_core.v index d2bfe57..10499a3 100644 --- a/top/n3xx/n300_rfnoc_image_core.v +++ b/top/n3xx/n300_rfnoc_image_core.v @@ -35,6 +35,7 @@ module rfnoc_image_core #( input wire core_arst, input wire radio_clk, input wire dram_clk, + input wire ce_clk, // Basic input wire [ 15:0] device_id, @@ -54,58 +55,58 @@ module rfnoc_image_core #( // time input wire [ 63:0] radio_time, // radio0 - input wire [ 255:0] radio_rx_data_radio0, - input wire [ 7:0] radio_rx_stb_radio0, - output wire [ 7:0] radio_rx_running_radio0, - output wire [ 255:0] radio_tx_data_radio0, - input wire [ 7:0] radio_tx_stb_radio0, - output wire [ 7:0] radio_tx_running_radio0, + input wire [1023:0] radio_rx_data_radio0, + input wire [ 31:0] radio_rx_stb_radio0, + output wire [ 31:0] radio_rx_running_radio0, + output wire [1023:0] radio_tx_data_radio0, + input wire [ 31:0] radio_tx_stb_radio0, + output wire [ 31:0] radio_tx_running_radio0, // dram input wire [ 0:0] axi_rst, - output wire [ 3:0] m_axi_awid, - output wire [ 191:0] m_axi_awaddr, - output wire [ 31:0] m_axi_awlen, - output wire [ 11:0] m_axi_awsize, - output wire [ 7:0] m_axi_awburst, - output wire [ 3:0] m_axi_awlock, - output wire [ 15:0] m_axi_awcache, - output wire [ 11:0] m_axi_awprot, - output wire [ 15:0] m_axi_awqos, - output wire [ 15:0] m_axi_awregion, - output wire [ 3:0] m_axi_awuser, - output wire [ 3:0] m_axi_awvalid, - input wire [ 3:0] m_axi_awready, - output wire [2047:0] m_axi_wdata, - output wire [ 255:0] m_axi_wstrb, - output wire [ 3:0] m_axi_wlast, - output wire [ 3:0] m_axi_wuser, - output wire [ 3:0] m_axi_wvalid, - input wire [ 3:0] m_axi_wready, - input wire [ 3:0] m_axi_bid, - input wire [ 7:0] m_axi_bresp, - input wire [ 3:0] m_axi_buser, - input wire [ 3:0] m_axi_bvalid, - output wire [ 3:0] m_axi_bready, - output wire [ 3:0] m_axi_arid, - output wire [ 191:0] m_axi_araddr, - output wire [ 31:0] m_axi_arlen, - output wire [ 11:0] m_axi_arsize, - output wire [ 7:0] m_axi_arburst, - output wire [ 3:0] m_axi_arlock, - output wire [ 15:0] m_axi_arcache, - output wire [ 11:0] m_axi_arprot, - output wire [ 15:0] m_axi_arqos, - output wire [ 15:0] m_axi_arregion, - output wire [ 3:0] m_axi_aruser, - output wire [ 3:0] m_axi_arvalid, - input wire [ 3:0] m_axi_arready, - input wire [ 3:0] m_axi_rid, - input wire [2047:0] m_axi_rdata, - input wire [ 7:0] m_axi_rresp, - input wire [ 3:0] m_axi_rlast, - input wire [ 3:0] m_axi_ruser, - input wire [ 3:0] m_axi_rvalid, - output wire [ 3:0] m_axi_rready, + output wire [ 7:0] m_axi_awid, + output wire [ 383:0] m_axi_awaddr, + output wire [ 63:0] m_axi_awlen, + output wire [ 23:0] m_axi_awsize, + output wire [ 15:0] m_axi_awburst, + output wire [ 7:0] m_axi_awlock, + output wire [ 31:0] m_axi_awcache, + output wire [ 23:0] m_axi_awprot, + output wire [ 31:0] m_axi_awqos, + output wire [ 31:0] m_axi_awregion, + output wire [ 7:0] m_axi_awuser, + output wire [ 7:0] m_axi_awvalid, + input wire [ 7:0] m_axi_awready, + output wire [4191:0] m_axi_wdata, + output wire [ 511:0] m_axi_wstrb, + output wire [ 7:0] m_axi_wlast, + output wire [ 7:0] m_axi_wuser, + output wire [ 7:0] m_axi_wvalid, + input wire [ 7:0] m_axi_wready, + input wire [ 7:0] m_axi_bid, + input wire [ 15:0] m_axi_bresp, + input wire [ 7:0] m_axi_buser, + input wire [ 7:0] m_axi_bvalid, + output wire [ 7:0] m_axi_bready, + output wire [ 7:0] m_axi_arid, + output wire [ 383:0] m_axi_araddr, + output wire [ 63:0] m_axi_arlen, + output wire [ 23:0] m_axi_arsize, + output wire [ 15:0] m_axi_arburst, + output wire [ 7:0] m_axi_arlock, + output wire [ 31:0] m_axi_arcache, + output wire [ 31:0] m_axi_arprot, + output wire [ 31:0] m_axi_arqos, + output wire [ 31:0] m_axi_arregion, + output wire [ 7:0] m_axi_aruser, + output wire [ 7:0] m_axi_arvalid, + input wire [ 7:0] m_axi_arready, + input wire [ 7:0] m_axi_rid, + input wire [4191:0] m_axi_rdata, + input wire [ 15:0] m_axi_rresp, + input wire [ 7:0] m_axi_rlast, + input wire [ 7:0] m_axi_ruser, + input wire [ 7:0] m_axi_rvalid, + output wire [ 7:0] m_axi_rready, // Transport Adapters /////////////// @@ -731,12 +732,12 @@ module rfnoc_image_core #( // time wire [ 63:0] radio0_radio_time; // radio - wire [ 255:0] radio0_radio_rx_data; - wire [ 7:0] radio0_radio_rx_stb; - wire [ 7:0] radio0_radio_rx_running; - wire [ 255:0] radio0_radio_tx_data; - wire [ 7:0] radio0_radio_tx_stb; - wire [ 7:0] radio0_radio_tx_running; + wire [1023:0] radio0_radio_rx_data; + wire [ 31:0] radio0_radio_rx_stb; + wire [ 31:0] radio0_radio_rx_running; + wire [1023:0] radio0_radio_tx_data; + wire [ 31:0] radio0_radio_tx_stb; + wire [ 31:0] radio0_radio_tx_running; rfnoc_block_radio #( .THIS_PORTID (4), @@ -802,50 +803,50 @@ module rfnoc_image_core #( // axi_ram wire [ 0:0] replay0_axi_rst; - wire [ 3:0] replay0_m_axi_awid; - wire [ 191:0] replay0_m_axi_awaddr; - wire [ 31:0] replay0_m_axi_awlen; - wire [ 11:0] replay0_m_axi_awsize; - wire [ 7:0] replay0_m_axi_awburst; - wire [ 3:0] replay0_m_axi_awlock; - wire [ 15:0] replay0_m_axi_awcache; - wire [ 11:0] replay0_m_axi_awprot; - wire [ 15:0] replay0_m_axi_awqos; - wire [ 15:0] replay0_m_axi_awregion; - wire [ 3:0] replay0_m_axi_awuser; - wire [ 3:0] replay0_m_axi_awvalid; - wire [ 3:0] replay0_m_axi_awready; - wire [2047:0] replay0_m_axi_wdata; - wire [ 255:0] replay0_m_axi_wstrb; - wire [ 3:0] replay0_m_axi_wlast; - wire [ 3:0] replay0_m_axi_wuser; - wire [ 3:0] replay0_m_axi_wvalid; - wire [ 3:0] replay0_m_axi_wready; - wire [ 3:0] replay0_m_axi_bid; - wire [ 7:0] replay0_m_axi_bresp; - wire [ 3:0] replay0_m_axi_buser; - wire [ 3:0] replay0_m_axi_bvalid; - wire [ 3:0] replay0_m_axi_bready; - wire [ 3:0] replay0_m_axi_arid; - wire [ 191:0] replay0_m_axi_araddr; - wire [ 31:0] replay0_m_axi_arlen; - wire [ 11:0] replay0_m_axi_arsize; - wire [ 7:0] replay0_m_axi_arburst; - wire [ 3:0] replay0_m_axi_arlock; - wire [ 15:0] replay0_m_axi_arcache; - wire [ 11:0] replay0_m_axi_arprot; - wire [ 15:0] replay0_m_axi_arqos; - wire [ 15:0] replay0_m_axi_arregion; - wire [ 3:0] replay0_m_axi_aruser; - wire [ 3:0] replay0_m_axi_arvalid; - wire [ 3:0] replay0_m_axi_arready; - wire [ 3:0] replay0_m_axi_rid; - wire [2047:0] replay0_m_axi_rdata; - wire [ 7:0] replay0_m_axi_rresp; - wire [ 3:0] replay0_m_axi_rlast; - wire [ 3:0] replay0_m_axi_ruser; - wire [ 3:0] replay0_m_axi_rvalid; - wire [ 3:0] replay0_m_axi_rready; + wire [ 7:0] replay0_m_axi_awid; + wire [ 383:0] replay0_m_axi_awaddr; + wire [ 63:0] replay0_m_axi_awlen; + wire [ 23:0] replay0_m_axi_awsize; + wire [ 15:0] replay0_m_axi_awburst; + wire [ 7:0] replay0_m_axi_awlock; + wire [ 31:0] replay0_m_axi_awcache; + wire [ 23:0] replay0_m_axi_awprot; + wire [ 31:0] replay0_m_axi_awqos; + wire [ 31:0] replay0_m_axi_awregion; + wire [ 7:0] replay0_m_axi_awuser; + wire [ 7:0] replay0_m_axi_awvalid; + wire [ 7:0] replay0_m_axi_awready; + wire [4191:0] replay0_m_axi_wdata; + wire [ 511:0] replay0_m_axi_wstrb; + wire [ 7:0] replay0_m_axi_wlast; + wire [ 7:0] replay0_m_axi_wuser; + wire [ 7:0] replay0_m_axi_wvalid; + wire [ 7:0] replay0_m_axi_wready; + wire [ 7:0] replay0_m_axi_bid; + wire [ 15:0] replay0_m_axi_bresp; + wire [ 7:0] replay0_m_axi_buser; + wire [ 7:0] replay0_m_axi_bvalid; + wire [ 7:0] replay0_m_axi_bready; + wire [ 7:0] replay0_m_axi_arid; + wire [ 383:0] replay0_m_axi_araddr; + wire [ 63:0] replay0_m_axi_arlen; + wire [ 23:0] replay0_m_axi_arsize; + wire [ 15:0] replay0_m_axi_arburst; + wire [ 7:0] replay0_m_axi_arlock; + wire [ 31:0] replay0_m_axi_arcache; + wire [ 31:0] replay0_m_axi_arprot; + wire [ 31:0] replay0_m_axi_arqos; + wire [ 31:0] replay0_m_axi_arregion; + wire [ 7:0] replay0_m_axi_aruser; + wire [ 7:0] replay0_m_axi_arvalid; + wire [ 7:0] replay0_m_axi_arready; + wire [ 7:0] replay0_m_axi_rid; + wire [4191:0] replay0_m_axi_rdata; + wire [ 15:0] replay0_m_axi_rresp; + wire [ 7:0] replay0_m_axi_rlast; + wire [ 7:0] replay0_m_axi_ruser; + wire [ 7:0] replay0_m_axi_rvalid; + wire [ 7:0] replay0_m_axi_rready; rfnoc_block_replay #( .THIS_PORTID (5), diff --git a/top/n3xx/n310_bist_image_core.v b/top/n3xx/n310_bist_image_core.v index 057e813..d85c811 100644 --- a/top/n3xx/n310_bist_image_core.v +++ b/top/n3xx/n310_bist_image_core.v @@ -35,6 +35,7 @@ module rfnoc_image_core #( input wire core_arst, input wire radio_clk, input wire dram_clk, + input wire ce_clk, // Basic input wire [ 15:0] device_id, @@ -65,65 +66,65 @@ module rfnoc_image_core #( // time input wire [ 63:0] radio_time, // radio0 - input wire [ 255:0] radio_rx_data_radio0, - input wire [ 7:0] radio_rx_stb_radio0, - output wire [ 7:0] radio_rx_running_radio0, - output wire [ 255:0] radio_tx_data_radio0, - input wire [ 7:0] radio_tx_stb_radio0, - output wire [ 7:0] radio_tx_running_radio0, + input wire [1023:0] radio_rx_data_radio0, + input wire [ 31:0] radio_rx_stb_radio0, + output wire [ 31:0] radio_rx_running_radio0, + output wire [1023:0] radio_tx_data_radio0, + input wire [ 31:0] radio_tx_stb_radio0, + output wire [ 31:0] radio_tx_running_radio0, // radio1 - input wire [ 255:0] radio_rx_data_radio1, - input wire [ 7:0] radio_rx_stb_radio1, - output wire [ 7:0] radio_rx_running_radio1, - output wire [ 255:0] radio_tx_data_radio1, - input wire [ 7:0] radio_tx_stb_radio1, - output wire [ 7:0] radio_tx_running_radio1, + input wire [1023:0] radio_rx_data_radio1, + input wire [ 31:0] radio_rx_stb_radio1, + output wire [ 31:0] radio_rx_running_radio1, + output wire [1023:0] radio_tx_data_radio1, + input wire [ 31:0] radio_tx_stb_radio1, + output wire [ 31:0] radio_tx_running_radio1, // dram input wire [ 0:0] axi_rst, - output wire [ 3:0] m_axi_awid, - output wire [ 191:0] m_axi_awaddr, - output wire [ 31:0] m_axi_awlen, - output wire [ 11:0] m_axi_awsize, - output wire [ 7:0] m_axi_awburst, - output wire [ 3:0] m_axi_awlock, - output wire [ 15:0] m_axi_awcache, - output wire [ 11:0] m_axi_awprot, - output wire [ 15:0] m_axi_awqos, - output wire [ 15:0] m_axi_awregion, - output wire [ 3:0] m_axi_awuser, - output wire [ 3:0] m_axi_awvalid, - input wire [ 3:0] m_axi_awready, - output wire [2047:0] m_axi_wdata, - output wire [ 255:0] m_axi_wstrb, - output wire [ 3:0] m_axi_wlast, - output wire [ 3:0] m_axi_wuser, - output wire [ 3:0] m_axi_wvalid, - input wire [ 3:0] m_axi_wready, - input wire [ 3:0] m_axi_bid, - input wire [ 7:0] m_axi_bresp, - input wire [ 3:0] m_axi_buser, - input wire [ 3:0] m_axi_bvalid, - output wire [ 3:0] m_axi_bready, - output wire [ 3:0] m_axi_arid, - output wire [ 191:0] m_axi_araddr, - output wire [ 31:0] m_axi_arlen, - output wire [ 11:0] m_axi_arsize, - output wire [ 7:0] m_axi_arburst, - output wire [ 3:0] m_axi_arlock, - output wire [ 15:0] m_axi_arcache, - output wire [ 11:0] m_axi_arprot, - output wire [ 15:0] m_axi_arqos, - output wire [ 15:0] m_axi_arregion, - output wire [ 3:0] m_axi_aruser, - output wire [ 3:0] m_axi_arvalid, - input wire [ 3:0] m_axi_arready, - input wire [ 3:0] m_axi_rid, - input wire [2047:0] m_axi_rdata, - input wire [ 7:0] m_axi_rresp, - input wire [ 3:0] m_axi_rlast, - input wire [ 3:0] m_axi_ruser, - input wire [ 3:0] m_axi_rvalid, - output wire [ 3:0] m_axi_rready, + output wire [ 7:0] m_axi_awid, + output wire [ 383:0] m_axi_awaddr, + output wire [ 63:0] m_axi_awlen, + output wire [ 23:0] m_axi_awsize, + output wire [ 15:0] m_axi_awburst, + output wire [ 7:0] m_axi_awlock, + output wire [ 31:0] m_axi_awcache, + output wire [ 23:0] m_axi_awprot, + output wire [ 31:0] m_axi_awqos, + output wire [ 31:0] m_axi_awregion, + output wire [ 7:0] m_axi_awuser, + output wire [ 7:0] m_axi_awvalid, + input wire [ 7:0] m_axi_awready, + output wire [4191:0] m_axi_wdata, + output wire [ 511:0] m_axi_wstrb, + output wire [ 7:0] m_axi_wlast, + output wire [ 7:0] m_axi_wuser, + output wire [ 7:0] m_axi_wvalid, + input wire [ 7:0] m_axi_wready, + input wire [ 7:0] m_axi_bid, + input wire [ 15:0] m_axi_bresp, + input wire [ 7:0] m_axi_buser, + input wire [ 7:0] m_axi_bvalid, + output wire [ 7:0] m_axi_bready, + output wire [ 7:0] m_axi_arid, + output wire [ 383:0] m_axi_araddr, + output wire [ 63:0] m_axi_arlen, + output wire [ 23:0] m_axi_arsize, + output wire [ 15:0] m_axi_arburst, + output wire [ 7:0] m_axi_arlock, + output wire [ 31:0] m_axi_arcache, + output wire [ 31:0] m_axi_arprot, + output wire [ 31:0] m_axi_arqos, + output wire [ 31:0] m_axi_arregion, + output wire [ 7:0] m_axi_aruser, + output wire [ 7:0] m_axi_arvalid, + input wire [ 7:0] m_axi_arready, + input wire [ 7:0] m_axi_rid, + input wire [4191:0] m_axi_rdata, + input wire [ 15:0] m_axi_rresp, + input wire [ 7:0] m_axi_rlast, + input wire [ 7:0] m_axi_ruser, + input wire [ 7:0] m_axi_rvalid, + output wire [ 7:0] m_axi_rready, // Transport Adapters /////////////// @@ -819,12 +820,12 @@ module rfnoc_image_core #( // time wire [ 63:0] radio0_radio_time; // radio - wire [ 255:0] radio0_radio_rx_data; - wire [ 7:0] radio0_radio_rx_stb; - wire [ 7:0] radio0_radio_rx_running; - wire [ 255:0] radio0_radio_tx_data; - wire [ 7:0] radio0_radio_tx_stb; - wire [ 7:0] radio0_radio_tx_running; + wire [1023:0] radio0_radio_rx_data; + wire [ 31:0] radio0_radio_rx_stb; + wire [ 31:0] radio0_radio_rx_running; + wire [1023:0] radio0_radio_tx_data; + wire [ 31:0] radio0_radio_tx_stb; + wire [ 31:0] radio0_radio_tx_running; rfnoc_block_radio #( .THIS_PORTID (2), @@ -902,12 +903,12 @@ module rfnoc_image_core #( // time wire [ 63:0] radio1_radio_time; // radio - wire [ 255:0] radio1_radio_rx_data; - wire [ 7:0] radio1_radio_rx_stb; - wire [ 7:0] radio1_radio_rx_running; - wire [ 255:0] radio1_radio_tx_data; - wire [ 7:0] radio1_radio_tx_stb; - wire [ 7:0] radio1_radio_tx_running; + wire [1023:0] radio1_radio_rx_data; + wire [ 31:0] radio1_radio_rx_stb; + wire [ 31:0] radio1_radio_rx_running; + wire [1023:0] radio1_radio_tx_data; + wire [ 31:0] radio1_radio_tx_stb; + wire [ 31:0] radio1_radio_tx_running; rfnoc_block_radio #( .THIS_PORTID (3), @@ -973,50 +974,50 @@ module rfnoc_image_core #( // axi_ram wire [ 0:0] fifo0_axi_rst; - wire [ 3:0] fifo0_m_axi_awid; - wire [ 191:0] fifo0_m_axi_awaddr; - wire [ 31:0] fifo0_m_axi_awlen; - wire [ 11:0] fifo0_m_axi_awsize; - wire [ 7:0] fifo0_m_axi_awburst; - wire [ 3:0] fifo0_m_axi_awlock; - wire [ 15:0] fifo0_m_axi_awcache; - wire [ 11:0] fifo0_m_axi_awprot; - wire [ 15:0] fifo0_m_axi_awqos; - wire [ 15:0] fifo0_m_axi_awregion; - wire [ 3:0] fifo0_m_axi_awuser; - wire [ 3:0] fifo0_m_axi_awvalid; - wire [ 3:0] fifo0_m_axi_awready; - wire [2047:0] fifo0_m_axi_wdata; - wire [ 255:0] fifo0_m_axi_wstrb; - wire [ 3:0] fifo0_m_axi_wlast; - wire [ 3:0] fifo0_m_axi_wuser; - wire [ 3:0] fifo0_m_axi_wvalid; - wire [ 3:0] fifo0_m_axi_wready; - wire [ 3:0] fifo0_m_axi_bid; - wire [ 7:0] fifo0_m_axi_bresp; - wire [ 3:0] fifo0_m_axi_buser; - wire [ 3:0] fifo0_m_axi_bvalid; - wire [ 3:0] fifo0_m_axi_bready; - wire [ 3:0] fifo0_m_axi_arid; - wire [ 191:0] fifo0_m_axi_araddr; - wire [ 31:0] fifo0_m_axi_arlen; - wire [ 11:0] fifo0_m_axi_arsize; - wire [ 7:0] fifo0_m_axi_arburst; - wire [ 3:0] fifo0_m_axi_arlock; - wire [ 15:0] fifo0_m_axi_arcache; - wire [ 11:0] fifo0_m_axi_arprot; - wire [ 15:0] fifo0_m_axi_arqos; - wire [ 15:0] fifo0_m_axi_arregion; - wire [ 3:0] fifo0_m_axi_aruser; - wire [ 3:0] fifo0_m_axi_arvalid; - wire [ 3:0] fifo0_m_axi_arready; - wire [ 3:0] fifo0_m_axi_rid; - wire [2047:0] fifo0_m_axi_rdata; - wire [ 7:0] fifo0_m_axi_rresp; - wire [ 3:0] fifo0_m_axi_rlast; - wire [ 3:0] fifo0_m_axi_ruser; - wire [ 3:0] fifo0_m_axi_rvalid; - wire [ 3:0] fifo0_m_axi_rready; + wire [ 7:0] fifo0_m_axi_awid; + wire [ 383:0] fifo0_m_axi_awaddr; + wire [ 63:0] fifo0_m_axi_awlen; + wire [ 23:0] fifo0_m_axi_awsize; + wire [ 15:0] fifo0_m_axi_awburst; + wire [ 7:0] fifo0_m_axi_awlock; + wire [ 31:0] fifo0_m_axi_awcache; + wire [ 23:0] fifo0_m_axi_awprot; + wire [ 31:0] fifo0_m_axi_awqos; + wire [ 31:0] fifo0_m_axi_awregion; + wire [ 7:0] fifo0_m_axi_awuser; + wire [ 7:0] fifo0_m_axi_awvalid; + wire [ 7:0] fifo0_m_axi_awready; + wire [4191:0] fifo0_m_axi_wdata; + wire [ 511:0] fifo0_m_axi_wstrb; + wire [ 7:0] fifo0_m_axi_wlast; + wire [ 7:0] fifo0_m_axi_wuser; + wire [ 7:0] fifo0_m_axi_wvalid; + wire [ 7:0] fifo0_m_axi_wready; + wire [ 7:0] fifo0_m_axi_bid; + wire [ 15:0] fifo0_m_axi_bresp; + wire [ 7:0] fifo0_m_axi_buser; + wire [ 7:0] fifo0_m_axi_bvalid; + wire [ 7:0] fifo0_m_axi_bready; + wire [ 7:0] fifo0_m_axi_arid; + wire [ 383:0] fifo0_m_axi_araddr; + wire [ 63:0] fifo0_m_axi_arlen; + wire [ 23:0] fifo0_m_axi_arsize; + wire [ 15:0] fifo0_m_axi_arburst; + wire [ 7:0] fifo0_m_axi_arlock; + wire [ 31:0] fifo0_m_axi_arcache; + wire [ 31:0] fifo0_m_axi_arprot; + wire [ 31:0] fifo0_m_axi_arqos; + wire [ 31:0] fifo0_m_axi_arregion; + wire [ 7:0] fifo0_m_axi_aruser; + wire [ 7:0] fifo0_m_axi_arvalid; + wire [ 7:0] fifo0_m_axi_arready; + wire [ 7:0] fifo0_m_axi_rid; + wire [4191:0] fifo0_m_axi_rdata; + wire [ 15:0] fifo0_m_axi_rresp; + wire [ 7:0] fifo0_m_axi_rlast; + wire [ 7:0] fifo0_m_axi_ruser; + wire [ 7:0] fifo0_m_axi_rvalid; + wire [ 7:0] fifo0_m_axi_rready; rfnoc_block_axi_ram_fifo #( .THIS_PORTID (4), diff --git a/top/n3xx/n310_rfnoc_image_core.v b/top/n3xx/n310_rfnoc_image_core.v index 564e10d..2774c3f 100644 --- a/top/n3xx/n310_rfnoc_image_core.v +++ b/top/n3xx/n310_rfnoc_image_core.v @@ -35,6 +35,7 @@ module rfnoc_image_core #( input wire core_arst, input wire radio_clk, input wire dram_clk, + input wire ce_clk, // Basic input wire [ 15:0] device_id, @@ -65,65 +66,65 @@ module rfnoc_image_core #( // time input wire [ 63:0] radio_time, // radio0 - input wire [ 255:0] radio_rx_data_radio0, - input wire [ 7:0] radio_rx_stb_radio0, - output wire [ 7:0] radio_rx_running_radio0, - output wire [ 255:0] radio_tx_data_radio0, - input wire [ 7:0] radio_tx_stb_radio0, - output wire [ 7:0] radio_tx_running_radio0, + input wire [1023:0] radio_rx_data_radio0, + input wire [ 31:0] radio_rx_stb_radio0, + output wire [ 31:0] radio_rx_running_radio0, + output wire [1023:0] radio_tx_data_radio0, + input wire [ 31:0] radio_tx_stb_radio0, + output wire [ 31:0] radio_tx_running_radio0, // radio1 - input wire [ 255:0] radio_rx_data_radio1, - input wire [ 7:0] radio_rx_stb_radio1, - output wire [ 7:0] radio_rx_running_radio1, - output wire [ 255:0] radio_tx_data_radio1, - input wire [ 7:0] radio_tx_stb_radio1, - output wire [ 7:0] radio_tx_running_radio1, + input wire [1023:0] radio_rx_data_radio1, + input wire [ 31:0] radio_rx_stb_radio1, + output wire [ 31:0] radio_rx_running_radio1, + output wire [1023:0] radio_tx_data_radio1, + input wire [ 31:0] radio_tx_stb_radio1, + output wire [ 31:0] radio_tx_running_radio1, // dram input wire [ 0:0] axi_rst, - output wire [ 3:0] m_axi_awid, - output wire [ 191:0] m_axi_awaddr, - output wire [ 31:0] m_axi_awlen, - output wire [ 11:0] m_axi_awsize, - output wire [ 7:0] m_axi_awburst, - output wire [ 3:0] m_axi_awlock, - output wire [ 15:0] m_axi_awcache, - output wire [ 11:0] m_axi_awprot, - output wire [ 15:0] m_axi_awqos, - output wire [ 15:0] m_axi_awregion, - output wire [ 3:0] m_axi_awuser, - output wire [ 3:0] m_axi_awvalid, - input wire [ 3:0] m_axi_awready, - output wire [2047:0] m_axi_wdata, - output wire [ 255:0] m_axi_wstrb, - output wire [ 3:0] m_axi_wlast, - output wire [ 3:0] m_axi_wuser, - output wire [ 3:0] m_axi_wvalid, - input wire [ 3:0] m_axi_wready, - input wire [ 3:0] m_axi_bid, - input wire [ 7:0] m_axi_bresp, - input wire [ 3:0] m_axi_buser, - input wire [ 3:0] m_axi_bvalid, - output wire [ 3:0] m_axi_bready, - output wire [ 3:0] m_axi_arid, - output wire [ 191:0] m_axi_araddr, - output wire [ 31:0] m_axi_arlen, - output wire [ 11:0] m_axi_arsize, - output wire [ 7:0] m_axi_arburst, - output wire [ 3:0] m_axi_arlock, - output wire [ 15:0] m_axi_arcache, - output wire [ 11:0] m_axi_arprot, - output wire [ 15:0] m_axi_arqos, - output wire [ 15:0] m_axi_arregion, - output wire [ 3:0] m_axi_aruser, - output wire [ 3:0] m_axi_arvalid, - input wire [ 3:0] m_axi_arready, - input wire [ 3:0] m_axi_rid, - input wire [2047:0] m_axi_rdata, - input wire [ 7:0] m_axi_rresp, - input wire [ 3:0] m_axi_rlast, - input wire [ 3:0] m_axi_ruser, - input wire [ 3:0] m_axi_rvalid, - output wire [ 3:0] m_axi_rready, + output wire [ 7:0] m_axi_awid, + output wire [ 383:0] m_axi_awaddr, + output wire [ 63:0] m_axi_awlen, + output wire [ 23:0] m_axi_awsize, + output wire [ 15:0] m_axi_awburst, + output wire [ 7:0] m_axi_awlock, + output wire [ 31:0] m_axi_awcache, + output wire [ 23:0] m_axi_awprot, + output wire [ 31:0] m_axi_awqos, + output wire [ 31:0] m_axi_awregion, + output wire [ 7:0] m_axi_awuser, + output wire [ 7:0] m_axi_awvalid, + input wire [ 7:0] m_axi_awready, + output wire [4191:0] m_axi_wdata, + output wire [ 511:0] m_axi_wstrb, + output wire [ 7:0] m_axi_wlast, + output wire [ 7:0] m_axi_wuser, + output wire [ 7:0] m_axi_wvalid, + input wire [ 7:0] m_axi_wready, + input wire [ 7:0] m_axi_bid, + input wire [ 15:0] m_axi_bresp, + input wire [ 7:0] m_axi_buser, + input wire [ 7:0] m_axi_bvalid, + output wire [ 7:0] m_axi_bready, + output wire [ 7:0] m_axi_arid, + output wire [ 383:0] m_axi_araddr, + output wire [ 63:0] m_axi_arlen, + output wire [ 23:0] m_axi_arsize, + output wire [ 15:0] m_axi_arburst, + output wire [ 7:0] m_axi_arlock, + output wire [ 31:0] m_axi_arcache, + output wire [ 31:0] m_axi_arprot, + output wire [ 31:0] m_axi_arqos, + output wire [ 31:0] m_axi_arregion, + output wire [ 7:0] m_axi_aruser, + output wire [ 7:0] m_axi_arvalid, + input wire [ 7:0] m_axi_arready, + input wire [ 7:0] m_axi_rid, + input wire [4191:0] m_axi_rdata, + input wire [ 15:0] m_axi_rresp, + input wire [ 7:0] m_axi_rlast, + input wire [ 7:0] m_axi_ruser, + input wire [ 7:0] m_axi_rvalid, + output wire [ 7:0] m_axi_rready, // Transport Adapters /////////////// @@ -1089,12 +1090,12 @@ module rfnoc_image_core #( // time wire [ 63:0] radio0_radio_time; // radio - wire [ 255:0] radio0_radio_rx_data; - wire [ 7:0] radio0_radio_rx_stb; - wire [ 7:0] radio0_radio_rx_running; - wire [ 255:0] radio0_radio_tx_data; - wire [ 7:0] radio0_radio_tx_stb; - wire [ 7:0] radio0_radio_tx_running; + wire [1023:0] radio0_radio_rx_data; + wire [ 31:0] radio0_radio_rx_stb; + wire [ 31:0] radio0_radio_rx_running; + wire [1023:0] radio0_radio_tx_data; + wire [ 31:0] radio0_radio_tx_stb; + wire [ 31:0] radio0_radio_tx_running; rfnoc_block_radio #( .THIS_PORTID (4), @@ -1262,12 +1263,12 @@ module rfnoc_image_core #( // time wire [ 63:0] radio1_radio_time; // radio - wire [ 255:0] radio1_radio_rx_data; - wire [ 7:0] radio1_radio_rx_stb; - wire [ 7:0] radio1_radio_rx_running; - wire [ 255:0] radio1_radio_tx_data; - wire [ 7:0] radio1_radio_tx_stb; - wire [ 7:0] radio1_radio_tx_running; + wire [1023:0] radio1_radio_rx_data; + wire [ 31:0] radio1_radio_rx_stb; + wire [ 31:0] radio1_radio_rx_running; + wire [1023:0] radio1_radio_tx_data; + wire [ 31:0] radio1_radio_tx_stb; + wire [ 31:0] radio1_radio_tx_running; rfnoc_block_radio #( .THIS_PORTID (7), @@ -1333,50 +1334,50 @@ module rfnoc_image_core #( // axi_ram wire [ 0:0] replay0_axi_rst; - wire [ 3:0] replay0_m_axi_awid; - wire [ 191:0] replay0_m_axi_awaddr; - wire [ 31:0] replay0_m_axi_awlen; - wire [ 11:0] replay0_m_axi_awsize; - wire [ 7:0] replay0_m_axi_awburst; - wire [ 3:0] replay0_m_axi_awlock; - wire [ 15:0] replay0_m_axi_awcache; - wire [ 11:0] replay0_m_axi_awprot; - wire [ 15:0] replay0_m_axi_awqos; - wire [ 15:0] replay0_m_axi_awregion; - wire [ 3:0] replay0_m_axi_awuser; - wire [ 3:0] replay0_m_axi_awvalid; - wire [ 3:0] replay0_m_axi_awready; - wire [2047:0] replay0_m_axi_wdata; - wire [ 255:0] replay0_m_axi_wstrb; - wire [ 3:0] replay0_m_axi_wlast; - wire [ 3:0] replay0_m_axi_wuser; - wire [ 3:0] replay0_m_axi_wvalid; - wire [ 3:0] replay0_m_axi_wready; - wire [ 3:0] replay0_m_axi_bid; - wire [ 7:0] replay0_m_axi_bresp; - wire [ 3:0] replay0_m_axi_buser; - wire [ 3:0] replay0_m_axi_bvalid; - wire [ 3:0] replay0_m_axi_bready; - wire [ 3:0] replay0_m_axi_arid; - wire [ 191:0] replay0_m_axi_araddr; - wire [ 31:0] replay0_m_axi_arlen; - wire [ 11:0] replay0_m_axi_arsize; - wire [ 7:0] replay0_m_axi_arburst; - wire [ 3:0] replay0_m_axi_arlock; - wire [ 15:0] replay0_m_axi_arcache; - wire [ 11:0] replay0_m_axi_arprot; - wire [ 15:0] replay0_m_axi_arqos; - wire [ 15:0] replay0_m_axi_arregion; - wire [ 3:0] replay0_m_axi_aruser; - wire [ 3:0] replay0_m_axi_arvalid; - wire [ 3:0] replay0_m_axi_arready; - wire [ 3:0] replay0_m_axi_rid; - wire [2047:0] replay0_m_axi_rdata; - wire [ 7:0] replay0_m_axi_rresp; - wire [ 3:0] replay0_m_axi_rlast; - wire [ 3:0] replay0_m_axi_ruser; - wire [ 3:0] replay0_m_axi_rvalid; - wire [ 3:0] replay0_m_axi_rready; + wire [ 7:0] replay0_m_axi_awid; + wire [ 383:0] replay0_m_axi_awaddr; + wire [ 63:0] replay0_m_axi_awlen; + wire [ 23:0] replay0_m_axi_awsize; + wire [ 15:0] replay0_m_axi_awburst; + wire [ 7:0] replay0_m_axi_awlock; + wire [ 31:0] replay0_m_axi_awcache; + wire [ 23:0] replay0_m_axi_awprot; + wire [ 31:0] replay0_m_axi_awqos; + wire [ 31:0] replay0_m_axi_awregion; + wire [ 7:0] replay0_m_axi_awuser; + wire [ 7:0] replay0_m_axi_awvalid; + wire [ 7:0] replay0_m_axi_awready; + wire [4191:0] replay0_m_axi_wdata; + wire [ 511:0] replay0_m_axi_wstrb; + wire [ 7:0] replay0_m_axi_wlast; + wire [ 7:0] replay0_m_axi_wuser; + wire [ 7:0] replay0_m_axi_wvalid; + wire [ 7:0] replay0_m_axi_wready; + wire [ 7:0] replay0_m_axi_bid; + wire [ 15:0] replay0_m_axi_bresp; + wire [ 7:0] replay0_m_axi_buser; + wire [ 7:0] replay0_m_axi_bvalid; + wire [ 7:0] replay0_m_axi_bready; + wire [ 7:0] replay0_m_axi_arid; + wire [ 383:0] replay0_m_axi_araddr; + wire [ 63:0] replay0_m_axi_arlen; + wire [ 23:0] replay0_m_axi_arsize; + wire [ 15:0] replay0_m_axi_arburst; + wire [ 7:0] replay0_m_axi_arlock; + wire [ 31:0] replay0_m_axi_arcache; + wire [ 31:0] replay0_m_axi_arprot; + wire [ 31:0] replay0_m_axi_arqos; + wire [ 31:0] replay0_m_axi_arregion; + wire [ 7:0] replay0_m_axi_aruser; + wire [ 7:0] replay0_m_axi_arvalid; + wire [ 7:0] replay0_m_axi_arready; + wire [ 7:0] replay0_m_axi_rid; + wire [4191:0] replay0_m_axi_rdata; + wire [ 15:0] replay0_m_axi_rresp; + wire [ 7:0] replay0_m_axi_rlast; + wire [ 7:0] replay0_m_axi_ruser; + wire [ 7:0] replay0_m_axi_rvalid; + wire [ 7:0] replay0_m_axi_rready; rfnoc_block_replay #( .THIS_PORTID (8), diff --git a/top/n3xx/n320_bist_image_core.v b/top/n3xx/n320_bist_image_core.v index c3feb57..0d42234 100644 --- a/top/n3xx/n320_bist_image_core.v +++ b/top/n3xx/n320_bist_image_core.v @@ -35,6 +35,7 @@ module rfnoc_image_core #( input wire core_arst, input wire radio_clk, input wire dram_clk, + input wire ce_clk, // Basic input wire [ 15:0] device_id, @@ -65,65 +66,65 @@ module rfnoc_image_core #( // time input wire [ 63:0] radio_time, // radio0 - input wire [ 255:0] radio_rx_data_radio0, - input wire [ 7:0] radio_rx_stb_radio0, - output wire [ 7:0] radio_rx_running_radio0, - output wire [ 255:0] radio_tx_data_radio0, - input wire [ 7:0] radio_tx_stb_radio0, - output wire [ 7:0] radio_tx_running_radio0, + input wire [1023:0] radio_rx_data_radio0, + input wire [ 31:0] radio_rx_stb_radio0, + output wire [ 31:0] radio_rx_running_radio0, + output wire [1023:0] radio_tx_data_radio0, + input wire [ 31:0] radio_tx_stb_radio0, + output wire [ 31:0] radio_tx_running_radio0, // radio1 - input wire [ 255:0] radio_rx_data_radio1, - input wire [ 7:0] radio_rx_stb_radio1, - output wire [ 7:0] radio_rx_running_radio1, - output wire [ 255:0] radio_tx_data_radio1, - input wire [ 7:0] radio_tx_stb_radio1, - output wire [ 7:0] radio_tx_running_radio1, + input wire [1023:0] radio_rx_data_radio1, + input wire [ 31:0] radio_rx_stb_radio1, + output wire [ 31:0] radio_rx_running_radio1, + output wire [1023:0] radio_tx_data_radio1, + input wire [ 31:0] radio_tx_stb_radio1, + output wire [ 31:0] radio_tx_running_radio1, // dram input wire [ 0:0] axi_rst, - output wire [ 3:0] m_axi_awid, - output wire [ 191:0] m_axi_awaddr, - output wire [ 31:0] m_axi_awlen, - output wire [ 11:0] m_axi_awsize, - output wire [ 7:0] m_axi_awburst, - output wire [ 3:0] m_axi_awlock, - output wire [ 15:0] m_axi_awcache, - output wire [ 11:0] m_axi_awprot, - output wire [ 15:0] m_axi_awqos, - output wire [ 15:0] m_axi_awregion, - output wire [ 3:0] m_axi_awuser, - output wire [ 3:0] m_axi_awvalid, - input wire [ 3:0] m_axi_awready, - output wire [2047:0] m_axi_wdata, - output wire [ 255:0] m_axi_wstrb, - output wire [ 3:0] m_axi_wlast, - output wire [ 3:0] m_axi_wuser, - output wire [ 3:0] m_axi_wvalid, - input wire [ 3:0] m_axi_wready, - input wire [ 3:0] m_axi_bid, - input wire [ 7:0] m_axi_bresp, - input wire [ 3:0] m_axi_buser, - input wire [ 3:0] m_axi_bvalid, - output wire [ 3:0] m_axi_bready, - output wire [ 3:0] m_axi_arid, - output wire [ 191:0] m_axi_araddr, - output wire [ 31:0] m_axi_arlen, - output wire [ 11:0] m_axi_arsize, - output wire [ 7:0] m_axi_arburst, - output wire [ 3:0] m_axi_arlock, - output wire [ 15:0] m_axi_arcache, - output wire [ 11:0] m_axi_arprot, - output wire [ 15:0] m_axi_arqos, - output wire [ 15:0] m_axi_arregion, - output wire [ 3:0] m_axi_aruser, - output wire [ 3:0] m_axi_arvalid, - input wire [ 3:0] m_axi_arready, - input wire [ 3:0] m_axi_rid, - input wire [2047:0] m_axi_rdata, - input wire [ 7:0] m_axi_rresp, - input wire [ 3:0] m_axi_rlast, - input wire [ 3:0] m_axi_ruser, - input wire [ 3:0] m_axi_rvalid, - output wire [ 3:0] m_axi_rready, + output wire [ 7:0] m_axi_awid, + output wire [ 383:0] m_axi_awaddr, + output wire [ 63:0] m_axi_awlen, + output wire [ 23:0] m_axi_awsize, + output wire [ 15:0] m_axi_awburst, + output wire [ 7:0] m_axi_awlock, + output wire [ 31:0] m_axi_awcache, + output wire [ 23:0] m_axi_awprot, + output wire [ 31:0] m_axi_awqos, + output wire [ 31:0] m_axi_awregion, + output wire [ 7:0] m_axi_awuser, + output wire [ 7:0] m_axi_awvalid, + input wire [ 7:0] m_axi_awready, + output wire [4191:0] m_axi_wdata, + output wire [ 511:0] m_axi_wstrb, + output wire [ 7:0] m_axi_wlast, + output wire [ 7:0] m_axi_wuser, + output wire [ 7:0] m_axi_wvalid, + input wire [ 7:0] m_axi_wready, + input wire [ 7:0] m_axi_bid, + input wire [ 15:0] m_axi_bresp, + input wire [ 7:0] m_axi_buser, + input wire [ 7:0] m_axi_bvalid, + output wire [ 7:0] m_axi_bready, + output wire [ 7:0] m_axi_arid, + output wire [ 383:0] m_axi_araddr, + output wire [ 63:0] m_axi_arlen, + output wire [ 23:0] m_axi_arsize, + output wire [ 15:0] m_axi_arburst, + output wire [ 7:0] m_axi_arlock, + output wire [ 31:0] m_axi_arcache, + output wire [ 31:0] m_axi_arprot, + output wire [ 31:0] m_axi_arqos, + output wire [ 31:0] m_axi_arregion, + output wire [ 7:0] m_axi_aruser, + output wire [ 7:0] m_axi_arvalid, + input wire [ 7:0] m_axi_arready, + input wire [ 7:0] m_axi_rid, + input wire [4191:0] m_axi_rdata, + input wire [ 15:0] m_axi_rresp, + input wire [ 7:0] m_axi_rlast, + input wire [ 7:0] m_axi_ruser, + input wire [ 7:0] m_axi_rvalid, + output wire [ 7:0] m_axi_rready, // Transport Adapters /////////////// @@ -655,12 +656,12 @@ module rfnoc_image_core #( // time wire [ 63:0] radio0_radio_time; // radio - wire [ 255:0] radio0_radio_rx_data; - wire [ 7:0] radio0_radio_rx_stb; - wire [ 7:0] radio0_radio_rx_running; - wire [ 255:0] radio0_radio_tx_data; - wire [ 7:0] radio0_radio_tx_stb; - wire [ 7:0] radio0_radio_tx_running; + wire [1023:0] radio0_radio_rx_data; + wire [ 31:0] radio0_radio_rx_stb; + wire [ 31:0] radio0_radio_rx_running; + wire [1023:0] radio0_radio_tx_data; + wire [ 31:0] radio0_radio_tx_stb; + wire [ 31:0] radio0_radio_tx_running; rfnoc_block_radio #( .THIS_PORTID (2), @@ -738,12 +739,12 @@ module rfnoc_image_core #( // time wire [ 63:0] radio1_radio_time; // radio - wire [ 255:0] radio1_radio_rx_data; - wire [ 7:0] radio1_radio_rx_stb; - wire [ 7:0] radio1_radio_rx_running; - wire [ 255:0] radio1_radio_tx_data; - wire [ 7:0] radio1_radio_tx_stb; - wire [ 7:0] radio1_radio_tx_running; + wire [1023:0] radio1_radio_rx_data; + wire [ 31:0] radio1_radio_rx_stb; + wire [ 31:0] radio1_radio_rx_running; + wire [1023:0] radio1_radio_tx_data; + wire [ 31:0] radio1_radio_tx_stb; + wire [ 31:0] radio1_radio_tx_running; rfnoc_block_radio #( .THIS_PORTID (3), @@ -809,50 +810,50 @@ module rfnoc_image_core #( // axi_ram wire [ 0:0] fifo0_axi_rst; - wire [ 3:0] fifo0_m_axi_awid; - wire [ 191:0] fifo0_m_axi_awaddr; - wire [ 31:0] fifo0_m_axi_awlen; - wire [ 11:0] fifo0_m_axi_awsize; - wire [ 7:0] fifo0_m_axi_awburst; - wire [ 3:0] fifo0_m_axi_awlock; - wire [ 15:0] fifo0_m_axi_awcache; - wire [ 11:0] fifo0_m_axi_awprot; - wire [ 15:0] fifo0_m_axi_awqos; - wire [ 15:0] fifo0_m_axi_awregion; - wire [ 3:0] fifo0_m_axi_awuser; - wire [ 3:0] fifo0_m_axi_awvalid; - wire [ 3:0] fifo0_m_axi_awready; - wire [2047:0] fifo0_m_axi_wdata; - wire [ 255:0] fifo0_m_axi_wstrb; - wire [ 3:0] fifo0_m_axi_wlast; - wire [ 3:0] fifo0_m_axi_wuser; - wire [ 3:0] fifo0_m_axi_wvalid; - wire [ 3:0] fifo0_m_axi_wready; - wire [ 3:0] fifo0_m_axi_bid; - wire [ 7:0] fifo0_m_axi_bresp; - wire [ 3:0] fifo0_m_axi_buser; - wire [ 3:0] fifo0_m_axi_bvalid; - wire [ 3:0] fifo0_m_axi_bready; - wire [ 3:0] fifo0_m_axi_arid; - wire [ 191:0] fifo0_m_axi_araddr; - wire [ 31:0] fifo0_m_axi_arlen; - wire [ 11:0] fifo0_m_axi_arsize; - wire [ 7:0] fifo0_m_axi_arburst; - wire [ 3:0] fifo0_m_axi_arlock; - wire [ 15:0] fifo0_m_axi_arcache; - wire [ 11:0] fifo0_m_axi_arprot; - wire [ 15:0] fifo0_m_axi_arqos; - wire [ 15:0] fifo0_m_axi_arregion; - wire [ 3:0] fifo0_m_axi_aruser; - wire [ 3:0] fifo0_m_axi_arvalid; - wire [ 3:0] fifo0_m_axi_arready; - wire [ 3:0] fifo0_m_axi_rid; - wire [2047:0] fifo0_m_axi_rdata; - wire [ 7:0] fifo0_m_axi_rresp; - wire [ 3:0] fifo0_m_axi_rlast; - wire [ 3:0] fifo0_m_axi_ruser; - wire [ 3:0] fifo0_m_axi_rvalid; - wire [ 3:0] fifo0_m_axi_rready; + wire [ 7:0] fifo0_m_axi_awid; + wire [ 383:0] fifo0_m_axi_awaddr; + wire [ 63:0] fifo0_m_axi_awlen; + wire [ 23:0] fifo0_m_axi_awsize; + wire [ 15:0] fifo0_m_axi_awburst; + wire [ 7:0] fifo0_m_axi_awlock; + wire [ 31:0] fifo0_m_axi_awcache; + wire [ 23:0] fifo0_m_axi_awprot; + wire [ 31:0] fifo0_m_axi_awqos; + wire [ 31:0] fifo0_m_axi_awregion; + wire [ 7:0] fifo0_m_axi_awuser; + wire [ 7:0] fifo0_m_axi_awvalid; + wire [ 7:0] fifo0_m_axi_awready; + wire [4191:0] fifo0_m_axi_wdata; + wire [ 511:0] fifo0_m_axi_wstrb; + wire [ 7:0] fifo0_m_axi_wlast; + wire [ 7:0] fifo0_m_axi_wuser; + wire [ 7:0] fifo0_m_axi_wvalid; + wire [ 7:0] fifo0_m_axi_wready; + wire [ 7:0] fifo0_m_axi_bid; + wire [ 15:0] fifo0_m_axi_bresp; + wire [ 7:0] fifo0_m_axi_buser; + wire [ 7:0] fifo0_m_axi_bvalid; + wire [ 7:0] fifo0_m_axi_bready; + wire [ 7:0] fifo0_m_axi_arid; + wire [ 383:0] fifo0_m_axi_araddr; + wire [ 63:0] fifo0_m_axi_arlen; + wire [ 23:0] fifo0_m_axi_arsize; + wire [ 15:0] fifo0_m_axi_arburst; + wire [ 7:0] fifo0_m_axi_arlock; + wire [ 31:0] fifo0_m_axi_arcache; + wire [ 31:0] fifo0_m_axi_arprot; + wire [ 31:0] fifo0_m_axi_arqos; + wire [ 31:0] fifo0_m_axi_arregion; + wire [ 7:0] fifo0_m_axi_aruser; + wire [ 7:0] fifo0_m_axi_arvalid; + wire [ 7:0] fifo0_m_axi_arready; + wire [ 7:0] fifo0_m_axi_rid; + wire [4191:0] fifo0_m_axi_rdata; + wire [ 15:0] fifo0_m_axi_rresp; + wire [ 7:0] fifo0_m_axi_rlast; + wire [ 7:0] fifo0_m_axi_ruser; + wire [ 7:0] fifo0_m_axi_rvalid; + wire [ 7:0] fifo0_m_axi_rready; rfnoc_block_axi_ram_fifo #( .THIS_PORTID (4), diff --git a/top/n3xx/n320_rfnoc_image_core.v b/top/n3xx/n320_rfnoc_image_core.v index 1114c9e..99e50cf 100644 --- a/top/n3xx/n320_rfnoc_image_core.v +++ b/top/n3xx/n320_rfnoc_image_core.v @@ -35,6 +35,7 @@ module rfnoc_image_core #( input wire core_arst, input wire radio_clk, input wire dram_clk, + input wire ce_clk, // Basic input wire [ 15:0] device_id, @@ -65,65 +66,65 @@ module rfnoc_image_core #( // time input wire [ 63:0] radio_time, // radio0 - input wire [ 255:0] radio_rx_data_radio0, - input wire [ 7:0] radio_rx_stb_radio0, - output wire [ 7:0] radio_rx_running_radio0, - output wire [ 255:0] radio_tx_data_radio0, - input wire [ 7:0] radio_tx_stb_radio0, - output wire [ 7:0] radio_tx_running_radio0, + input wire [1023:0] radio_rx_data_radio0, + input wire [ 31:0] radio_rx_stb_radio0, + output wire [ 31:0] radio_rx_running_radio0, + output wire [1023:0] radio_tx_data_radio0, + input wire [ 31:0] radio_tx_stb_radio0, + output wire [ 31:0] radio_tx_running_radio0, // radio1 - input wire [ 255:0] radio_rx_data_radio1, - input wire [ 7:0] radio_rx_stb_radio1, - output wire [ 7:0] radio_rx_running_radio1, - output wire [ 255:0] radio_tx_data_radio1, - input wire [ 7:0] radio_tx_stb_radio1, - output wire [ 7:0] radio_tx_running_radio1, + input wire [1023:0] radio_rx_data_radio1, + input wire [ 31:0] radio_rx_stb_radio1, + output wire [ 31:0] radio_rx_running_radio1, + output wire [1023:0] radio_tx_data_radio1, + input wire [ 31:0] radio_tx_stb_radio1, + output wire [ 31:0] radio_tx_running_radio1, // dram input wire [ 0:0] axi_rst, - output wire [ 3:0] m_axi_awid, - output wire [ 191:0] m_axi_awaddr, - output wire [ 31:0] m_axi_awlen, - output wire [ 11:0] m_axi_awsize, - output wire [ 7:0] m_axi_awburst, - output wire [ 3:0] m_axi_awlock, - output wire [ 15:0] m_axi_awcache, - output wire [ 11:0] m_axi_awprot, - output wire [ 15:0] m_axi_awqos, - output wire [ 15:0] m_axi_awregion, - output wire [ 3:0] m_axi_awuser, - output wire [ 3:0] m_axi_awvalid, - input wire [ 3:0] m_axi_awready, - output wire [2047:0] m_axi_wdata, - output wire [ 255:0] m_axi_wstrb, - output wire [ 3:0] m_axi_wlast, - output wire [ 3:0] m_axi_wuser, - output wire [ 3:0] m_axi_wvalid, - input wire [ 3:0] m_axi_wready, - input wire [ 3:0] m_axi_bid, - input wire [ 7:0] m_axi_bresp, - input wire [ 3:0] m_axi_buser, - input wire [ 3:0] m_axi_bvalid, - output wire [ 3:0] m_axi_bready, - output wire [ 3:0] m_axi_arid, - output wire [ 191:0] m_axi_araddr, - output wire [ 31:0] m_axi_arlen, - output wire [ 11:0] m_axi_arsize, - output wire [ 7:0] m_axi_arburst, - output wire [ 3:0] m_axi_arlock, - output wire [ 15:0] m_axi_arcache, - output wire [ 11:0] m_axi_arprot, - output wire [ 15:0] m_axi_arqos, - output wire [ 15:0] m_axi_arregion, - output wire [ 3:0] m_axi_aruser, - output wire [ 3:0] m_axi_arvalid, - input wire [ 3:0] m_axi_arready, - input wire [ 3:0] m_axi_rid, - input wire [2047:0] m_axi_rdata, - input wire [ 7:0] m_axi_rresp, - input wire [ 3:0] m_axi_rlast, - input wire [ 3:0] m_axi_ruser, - input wire [ 3:0] m_axi_rvalid, - output wire [ 3:0] m_axi_rready, + output wire [ 7:0] m_axi_awid, + output wire [ 383:0] m_axi_awaddr, + output wire [ 63:0] m_axi_awlen, + output wire [ 23:0] m_axi_awsize, + output wire [ 15:0] m_axi_awburst, + output wire [ 7:0] m_axi_awlock, + output wire [ 31:0] m_axi_awcache, + output wire [ 23:0] m_axi_awprot, + output wire [ 31:0] m_axi_awqos, + output wire [ 31:0] m_axi_awregion, + output wire [ 7:0] m_axi_awuser, + output wire [ 7:0] m_axi_awvalid, + input wire [ 7:0] m_axi_awready, + output wire [4191:0] m_axi_wdata, + output wire [ 511:0] m_axi_wstrb, + output wire [ 7:0] m_axi_wlast, + output wire [ 7:0] m_axi_wuser, + output wire [ 7:0] m_axi_wvalid, + input wire [ 7:0] m_axi_wready, + input wire [ 7:0] m_axi_bid, + input wire [ 15:0] m_axi_bresp, + input wire [ 7:0] m_axi_buser, + input wire [ 7:0] m_axi_bvalid, + output wire [ 7:0] m_axi_bready, + output wire [ 7:0] m_axi_arid, + output wire [ 383:0] m_axi_araddr, + output wire [ 63:0] m_axi_arlen, + output wire [ 23:0] m_axi_arsize, + output wire [ 15:0] m_axi_arburst, + output wire [ 7:0] m_axi_arlock, + output wire [ 31:0] m_axi_arcache, + output wire [ 31:0] m_axi_arprot, + output wire [ 31:0] m_axi_arqos, + output wire [ 31:0] m_axi_arregion, + output wire [ 7:0] m_axi_aruser, + output wire [ 7:0] m_axi_arvalid, + input wire [ 7:0] m_axi_arready, + input wire [ 7:0] m_axi_rid, + input wire [4191:0] m_axi_rdata, + input wire [ 15:0] m_axi_rresp, + input wire [ 7:0] m_axi_rlast, + input wire [ 7:0] m_axi_ruser, + input wire [ 7:0] m_axi_rvalid, + output wire [ 7:0] m_axi_rready, // Transport Adapters /////////////// @@ -761,12 +762,12 @@ module rfnoc_image_core #( // time wire [ 63:0] radio0_radio_time; // radio - wire [ 255:0] radio0_radio_rx_data; - wire [ 7:0] radio0_radio_rx_stb; - wire [ 7:0] radio0_radio_rx_running; - wire [ 255:0] radio0_radio_tx_data; - wire [ 7:0] radio0_radio_tx_stb; - wire [ 7:0] radio0_radio_tx_running; + wire [1023:0] radio0_radio_rx_data; + wire [ 31:0] radio0_radio_rx_stb; + wire [ 31:0] radio0_radio_rx_running; + wire [1023:0] radio0_radio_tx_data; + wire [ 31:0] radio0_radio_tx_stb; + wire [ 31:0] radio0_radio_tx_running; rfnoc_block_radio #( .THIS_PORTID (4), @@ -934,12 +935,12 @@ module rfnoc_image_core #( // time wire [ 63:0] radio1_radio_time; // radio - wire [ 255:0] radio1_radio_rx_data; - wire [ 7:0] radio1_radio_rx_stb; - wire [ 7:0] radio1_radio_rx_running; - wire [ 255:0] radio1_radio_tx_data; - wire [ 7:0] radio1_radio_tx_stb; - wire [ 7:0] radio1_radio_tx_running; + wire [1023:0] radio1_radio_rx_data; + wire [ 31:0] radio1_radio_rx_stb; + wire [ 31:0] radio1_radio_rx_running; + wire [1023:0] radio1_radio_tx_data; + wire [ 31:0] radio1_radio_tx_stb; + wire [ 31:0] radio1_radio_tx_running; rfnoc_block_radio #( .THIS_PORTID (7), @@ -1005,50 +1006,50 @@ module rfnoc_image_core #( // axi_ram wire [ 0:0] replay0_axi_rst; - wire [ 3:0] replay0_m_axi_awid; - wire [ 191:0] replay0_m_axi_awaddr; - wire [ 31:0] replay0_m_axi_awlen; - wire [ 11:0] replay0_m_axi_awsize; - wire [ 7:0] replay0_m_axi_awburst; - wire [ 3:0] replay0_m_axi_awlock; - wire [ 15:0] replay0_m_axi_awcache; - wire [ 11:0] replay0_m_axi_awprot; - wire [ 15:0] replay0_m_axi_awqos; - wire [ 15:0] replay0_m_axi_awregion; - wire [ 3:0] replay0_m_axi_awuser; - wire [ 3:0] replay0_m_axi_awvalid; - wire [ 3:0] replay0_m_axi_awready; - wire [2047:0] replay0_m_axi_wdata; - wire [ 255:0] replay0_m_axi_wstrb; - wire [ 3:0] replay0_m_axi_wlast; - wire [ 3:0] replay0_m_axi_wuser; - wire [ 3:0] replay0_m_axi_wvalid; - wire [ 3:0] replay0_m_axi_wready; - wire [ 3:0] replay0_m_axi_bid; - wire [ 7:0] replay0_m_axi_bresp; - wire [ 3:0] replay0_m_axi_buser; - wire [ 3:0] replay0_m_axi_bvalid; - wire [ 3:0] replay0_m_axi_bready; - wire [ 3:0] replay0_m_axi_arid; - wire [ 191:0] replay0_m_axi_araddr; - wire [ 31:0] replay0_m_axi_arlen; - wire [ 11:0] replay0_m_axi_arsize; - wire [ 7:0] replay0_m_axi_arburst; - wire [ 3:0] replay0_m_axi_arlock; - wire [ 15:0] replay0_m_axi_arcache; - wire [ 11:0] replay0_m_axi_arprot; - wire [ 15:0] replay0_m_axi_arqos; - wire [ 15:0] replay0_m_axi_arregion; - wire [ 3:0] replay0_m_axi_aruser; - wire [ 3:0] replay0_m_axi_arvalid; - wire [ 3:0] replay0_m_axi_arready; - wire [ 3:0] replay0_m_axi_rid; - wire [2047:0] replay0_m_axi_rdata; - wire [ 7:0] replay0_m_axi_rresp; - wire [ 3:0] replay0_m_axi_rlast; - wire [ 3:0] replay0_m_axi_ruser; - wire [ 3:0] replay0_m_axi_rvalid; - wire [ 3:0] replay0_m_axi_rready; + wire [ 7:0] replay0_m_axi_awid; + wire [ 383:0] replay0_m_axi_awaddr; + wire [ 63:0] replay0_m_axi_awlen; + wire [ 23:0] replay0_m_axi_awsize; + wire [ 15:0] replay0_m_axi_awburst; + wire [ 7:0] replay0_m_axi_awlock; + wire [ 31:0] replay0_m_axi_awcache; + wire [ 23:0] replay0_m_axi_awprot; + wire [ 31:0] replay0_m_axi_awqos; + wire [ 31:0] replay0_m_axi_awregion; + wire [ 7:0] replay0_m_axi_awuser; + wire [ 7:0] replay0_m_axi_awvalid; + wire [ 7:0] replay0_m_axi_awready; + wire [4191:0] replay0_m_axi_wdata; + wire [ 511:0] replay0_m_axi_wstrb; + wire [ 7:0] replay0_m_axi_wlast; + wire [ 7:0] replay0_m_axi_wuser; + wire [ 7:0] replay0_m_axi_wvalid; + wire [ 7:0] replay0_m_axi_wready; + wire [ 7:0] replay0_m_axi_bid; + wire [ 15:0] replay0_m_axi_bresp; + wire [ 7:0] replay0_m_axi_buser; + wire [ 7:0] replay0_m_axi_bvalid; + wire [ 7:0] replay0_m_axi_bready; + wire [ 7:0] replay0_m_axi_arid; + wire [ 383:0] replay0_m_axi_araddr; + wire [ 63:0] replay0_m_axi_arlen; + wire [ 23:0] replay0_m_axi_arsize; + wire [ 15:0] replay0_m_axi_arburst; + wire [ 7:0] replay0_m_axi_arlock; + wire [ 31:0] replay0_m_axi_arcache; + wire [ 31:0] replay0_m_axi_arprot; + wire [ 31:0] replay0_m_axi_arqos; + wire [ 31:0] replay0_m_axi_arregion; + wire [ 7:0] replay0_m_axi_aruser; + wire [ 7:0] replay0_m_axi_arvalid; + wire [ 7:0] replay0_m_axi_arready; + wire [ 7:0] replay0_m_axi_rid; + wire [4191:0] replay0_m_axi_rdata; + wire [ 15:0] replay0_m_axi_rresp; + wire [ 7:0] replay0_m_axi_rlast; + wire [ 7:0] replay0_m_axi_ruser; + wire [ 7:0] replay0_m_axi_rvalid; + wire [ 7:0] replay0_m_axi_rready; rfnoc_block_replay #( .THIS_PORTID (8), @@ -1202,11 +1203,11 @@ module rfnoc_image_core #( //--------------------------------------------------------------------------- assign radio0_radio_clk = radio_clk; - assign ddc0_ce_clk = radio_clk; - assign duc0_ce_clk = radio_clk; + assign ddc0_ce_clk = ce_clk; + assign duc0_ce_clk = ce_clk; assign radio1_radio_clk = radio_clk; - assign ddc1_ce_clk = radio_clk; - assign duc1_ce_clk = radio_clk; + assign ddc1_ce_clk = ce_clk; + assign duc1_ce_clk = ce_clk; assign replay0_mem_clk = dram_clk; diff --git a/top/n3xx/n320_rfnoc_image_core.yml b/top/n3xx/n320_rfnoc_image_core.yml index 669ebe0..0ed93d4 100644 --- a/top/n3xx/n320_rfnoc_image_core.yml +++ b/top/n3xx/n320_rfnoc_image_core.yml @@ -109,9 +109,9 @@ connections: # - dstport = Clock domain on the destination block to connect clk_domains: - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } - - { srcblk: _device_, srcport: radio, dstblk: ddc0, dstport: ce } - - { srcblk: _device_, srcport: radio, dstblk: duc0, dstport: ce } + - { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce } + - { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce } - { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio } - - { srcblk: _device_, srcport: radio, dstblk: ddc1, dstport: ce } - - { srcblk: _device_, srcport: radio, dstblk: duc1, dstport: ce } + - { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce } + - { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce } - { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem } diff --git a/top/n3xx/n3xx_clocking.v b/top/n3xx/n3xx_clocking.v index 11738f2..a1d0770 100644 --- a/top/n3xx/n3xx_clocking.v +++ b/top/n3xx/n3xx_clocking.v @@ -44,7 +44,11 @@ module n3xx_clocking ( output meas_clk, output ddr3_dma_clk, input misc_clks_reset, - output misc_clks_locked, + output reg misc_clks_locked, + + // CE Clock + input clk200, + output ce_clk, // PPS Capture & Selection input ext_pps_from_pin, @@ -137,14 +141,93 @@ module n3xx_clocking ( //---------------------------------------------------------------------------- // __primary________166.666667____________0.010 + wire misc_locked; + misc_clock_gen misc_clock_gen_i ( .clk_in (misc_clks_ref), .meas_clk (meas_clk), .ddr3_dma_clk (ddr3_dma_clk), .reset (misc_clks_reset), - .locked (misc_clks_locked) + .locked (misc_locked) ); + // Compute Engine Clock + // + //---------------------------------------------------------------------------- + // Output Output Phase Duty Cycle Pk-to-Pk Phase + // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + //---------------------------------------------------------------------------- + // __ce_clk__266.66667______0.000______50.0______112.125____110.663 + // + //---------------------------------------------------------------------------- + // Input Clock Freq (MHz) Input Jitter (UI) + //---------------------------------------------------------------------------- + // __primary_____________200____________0.010 + + wire ce_gen_clkfbout; + wire ce_gen_clkout0; + wire ce_gen_locked; + + PLLE2_ADV #( + .BANDWIDTH ("OPTIMIZED"), + .COMPENSATION ("ZHOLD" ), + .STARTUP_WAIT ("FALSE" ), + .DIVCLK_DIVIDE (3 ), + .CLKFBOUT_MULT (16 ), + .CLKFBOUT_PHASE (0.000 ), + .CLKOUT0_DIVIDE (4 ), + .CLKOUT0_PHASE (0.000 ), + .CLKOUT0_DUTY_CYCLE(0.500 ), + .CLKIN1_PERIOD (5.000 ) + ) ce_clk_gen_i ( + .CLKFBOUT(ce_gen_clkfbout), + .CLKOUT0 (ce_gen_clkout0 ), + .CLKOUT1 ( ), + .CLKOUT2 ( ), + .CLKOUT3 ( ), + .CLKOUT4 ( ), + .CLKOUT5 ( ), + .CLKFBIN (ce_gen_clkfbout), + .CLKIN1 (clk200 ), + .CLKIN2 (1'b0 ), + .CLKINSEL(1'b1 ), + .DADDR (7'h0 ), + .DCLK (1'b0 ), + .DEN (1'b0 ), + .DI (16'h0 ), + .DO ( ), + .DRDY ( ), + .DWE (1'b0 ), + .LOCKED (ce_gen_locked ), + .PWRDWN (1'b0 ), + .RST (misc_clks_reset) + ); + + BUFG ce_clk_buf ( + .O(ce_clk ), + .I(ce_gen_clkout0) + ); + + wire misc_locked_clk200; + wire ce_lockec_clk200; + + synchronizer synchronizer_misc ( + .clk(clk200 ), + .rst(1'b0 ), + .in (misc_locked ), + .out(misc_locked_clk200) + ); + + synchronizer synchronizer_ce ( + .clk(clk200 ), + .rst(1'b0 ), + .in (ce_gen_locked ), + .out(ce_locked_clk200) + ); + + always @(posedge clk200) begin + misc_clks_locked <= misc_locked_clk200 & ce_locked_clk200; + end // PPS Capture and Generation : /////////////////////////////////////////////////////// // diff --git a/top/n3xx/n3xx_core.v b/top/n3xx/n3xx_core.v index f561378..4a36b86 100644 --- a/top/n3xx/n3xx_core.v +++ b/top/n3xx/n3xx_core.v @@ -36,6 +36,7 @@ module n3xx_core #( input bus_rst, input ddr3_dma_clk, input clk40, + input ce_clk, // Clocking and PPS Controls/Indicators input pps, @@ -1138,6 +1139,7 @@ module n3xx_core #( .device_id (device_id ), .radio_clk (radio_clk ), .dram_clk (ddr3_dma_clk), + .ce_clk (ce_clk), `ifndef N300 .m_ctrlport_radio1_req_wr (m_ctrlport_req_wr_radio1 ), .m_ctrlport_radio1_req_rd (m_ctrlport_req_rd_radio1 ),