miegl/b210-k7-fpga
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fpga: n3xx: Add CE clock

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Adds a 266.667 MHz compute engine clock and uses it instead of the
radio clock for the DDC and DUC. Using a faster clock than the radio
allows the DDC and DUC to drain after a stall in the data flow.


Original-commit: ff55d406a02cc934a5c238d22c836bea08ade3d1
This commit is contained in:
Wade Fife
2023-10-18 22:23:55 -05:00
parent e4d9a9a448
commit 2612487d43
12 changed files with 761 additions and 658 deletions
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top/n3xx/n320_rfnoc_image_core.yml
+4 -4
View File
@@ -109,9 +109,9 @@ connections:
# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
- { srcblk: _device_, srcport: radio, dstblk: ddc0, dstport: ce }
- { srcblk: _device_, srcport: radio, dstblk: duc0, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce }
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
- { srcblk: _device_, srcport: radio, dstblk: ddc1, dstport: ce }
- { srcblk: _device_, srcport: radio, dstblk: duc1, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce }
- { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce }
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }