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fpga: n3xx: Add CE clock

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Adds a 266.667 MHz compute engine clock and uses it instead of the
radio clock for the DDC and DUC. Using a faster clock than the radio
allows the DDC and DUC to drain after a stall in the data flow.


Original-commit: ff55d406a02cc934a5c238d22c836bea08ade3d1
This commit is contained in:
Wade Fife
2023-10-18 22:23:55 -05:00
parent e4d9a9a448
commit 2612487d43
12 changed files with 761 additions and 658 deletions
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top/n3xx/mb_clocks.xdc
+4
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@@ -64,6 +64,10 @@ set_input_jitter [get_clocks bus_clk] $bus_clk_jitter
create_generated_clock -name meas_clk_fb [get_pins {n3xx_clocking_i/misc_clock_gen_i/inst/mmcm_adv_inst/CLKFBOUT}]
create_generated_clock -name meas_clk [get_pins {n3xx_clocking_i/misc_clock_gen_i/inst/mmcm_adv_inst/CLKOUT0}]
# CE Clock
create_generated_clock -name ce_clk_fb [get_pins {n3xx_clocking_i/ce_clk_gen_i/CLKFBOUT}]
create_generated_clock -name ce_clk [get_pins {n3xx_clocking_i/ce_clk_gen_i/CLKOUT0}]
#*******************************************************************************
## White Rabbit DAC
# Constrain the DIN and NSYNC bits around the clock output. No readback.