fpga: n3xx: Add CE clock

Adds a 266.667 MHz compute engine clock and uses it instead of the radio clock for the DDC and DUC. Using a faster clock than the radio allows the DDC and DUC to drain after a stall in the data flow. Original-commit: ff55d406a02cc934a5c238d22c836bea08ade3d1
2023-10-18 22:23:55 -05:00
parent e4d9a9a448
commit 2612487d43
12 changed files with 761 additions and 658 deletions
@@ -737,6 +737,7 @@ module n3xx (
  wire        clk40;
  wire        meas_clk_ref;
  wire        bus_clk;
+  wire        ce_clk;
  wire        gige_refclk;
  wire        gige_refclk_bufg;
  wire        xgige_refclk;
@@ -860,6 +861,8 @@ module n3xx (
    .ddr3_dma_clk(ddr3_dma_clk),
    .misc_clks_reset(meas_clk_reset),
    .misc_clks_locked(meas_clk_locked),
+    .clk200(bus_clk),
+    .ce_clk(ce_clk),
    .ext_pps_from_pin(REF_1PPS_IN),
    .gps_pps_from_pin(GPS_1PPS),
    .pps_select(pps_select),
@@ -3573,6 +3576,7 @@ module n3xx (
    .bus_rst(bus_rst),
    .ddr3_dma_clk(ddr3_dma_clk),
    .clk40(clk40),
+    .ce_clk(ce_clk),

    // Clocking and PPS Controls/Indicators
    .pps(pps_radioclk1x),