fpga: x400: Upgrade to Vivado 2021.1
Commit includes: - Upgrade x400-specific IP - Removal of xge_pcs_pma IP patch Original-commit: e94deac2efb8c3167eb2d70a385a8fa0ad657b55
This commit is contained in:
Sam O'Brien
@@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder]
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################################################################
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# Check if script is running in correct Vivado version.
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################################################################
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set scripts_vivado_version 2019.1
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set scripts_vivado_version 2021.1
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set current_vivado_version [version -short]
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if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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puts ""
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catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
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catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
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return 1
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}
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@@ -83,10 +83,10 @@ if { ${design_name} eq "" } {
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# 4): Current design opened AND is empty AND names diff; design_name exists in project.
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if { $cur_design ne $design_name } {
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common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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set design_name [get_property NAME $cur_design]
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}
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common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
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common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
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} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
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# USE CASES:
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@@ -107,11 +107,11 @@ if { ${design_name} eq "" } {
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# 8) No opened design, design_name not in project.
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# 9) Current opened design, has components, but diff names, design_name not in project.
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common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
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common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
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create_bd_design $design_name
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common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
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common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
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current_bd_design $design_name
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}
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@@ -123,10 +123,10 @@ if { ${design_name} eq "" } {
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[15:8] = invert DAC channels
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[7:0] = invert ADC channels" [get_bd_designs $design_name]
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common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
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common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
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if { $nRet != 0 } {
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catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
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catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
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return $nRet
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}
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@@ -143,16 +143,16 @@ xilinx.com:ip:xlconcat:2.1\
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xilinx.com:ip:xlconstant:1.1\
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xilinx.com:ip:clk_wiz:6.0\
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xilinx.com:ip:axi_gpio:2.0\
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xilinx.com:ip:usp_rf_data_converter:2.1\
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xilinx.com:ip:usp_rf_data_converter:2.5\
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xilinx.com:ip:xlslice:1.0\
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xilinx.com:ip:axi_protocol_converter:2.1\
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xilinx.com:ip:axi_dma:7.1\
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xilinx.com:ip:smartconnect:1.0\
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xilinx.com:ip:util_ds_buf:2.1\
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xilinx.com:ip:util_ds_buf:2.2\
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"
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set list_ips_missing ""
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common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
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common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
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foreach ip_vlnv $list_check_ips {
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set ip_obj [get_ipdefs -all $ip_vlnv]
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@@ -162,7 +162,7 @@ xilinx.com:ip:util_ds_buf:2.1\
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}
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if { $list_ips_missing ne "" } {
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catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
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catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
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set bCheckIPsPassed 0
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}
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@@ -182,7 +182,7 @@ gpio_to_axis_mux\
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"
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set list_mods_missing ""
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common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
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common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
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foreach mod_vlnv $list_check_mods {
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if { [can_resolve_reference $mod_vlnv] == 0 } {
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@@ -191,14 +191,14 @@ gpio_to_axis_mux\
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}
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if { $list_mods_missing ne "" } {
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catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
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common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above."
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catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
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common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
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set bCheckIPsPassed 0
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}
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}
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if { $bCheckIPsPassed != 1 } {
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common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
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common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
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return 3
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}
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@@ -213,21 +213,21 @@ proc create_hier_cell_rf_clock_buffers { parentCell nameHier } {
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variable script_folder
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if { $parentCell eq "" || $nameHier eq "" } {
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catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_rf_clock_buffers() - Empty argument(s)!"}
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catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_rf_clock_buffers() - Empty argument(s)!"}
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return
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}
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# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
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catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
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return
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}
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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return
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}
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@@ -252,13 +252,13 @@ proc create_hier_cell_rf_clock_buffers { parentCell nameHier } {
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create_bd_pin -dir I -from 0 -to 0 -type clk rfdc_clk_pll
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# Create instance: rfdc_clk_1x_buf, and set properties
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set rfdc_clk_1x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 rfdc_clk_1x_buf ]
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set rfdc_clk_1x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 rfdc_clk_1x_buf ]
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set_property -dict [ list \
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CONFIG.C_BUF_TYPE {BUFGCE} \
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] $rfdc_clk_1x_buf
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# Create instance: rfdc_clk_2x_buf, and set properties
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set rfdc_clk_2x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 rfdc_clk_2x_buf ]
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set rfdc_clk_2x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 rfdc_clk_2x_buf ]
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set_property -dict [ list \
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CONFIG.C_BUF_TYPE {BUFGCE} \
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] $rfdc_clk_2x_buf
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@@ -281,21 +281,21 @@ proc create_hier_cell_calibration_muxes { parentCell nameHier } {
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variable script_folder
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if { $parentCell eq "" || $nameHier eq "" } {
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catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_calibration_muxes() - Empty argument(s)!"}
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catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_calibration_muxes() - Empty argument(s)!"}
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return
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}
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# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
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catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
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return
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}
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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return
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}
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@@ -347,10 +347,10 @@ proc create_hier_cell_calibration_muxes { parentCell nameHier } {
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set block_name gpio_to_axis_mux
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set block_cell_name gpio_to_axis_mux_0
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if { [catch {set gpio_to_axis_mux_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
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catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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return 1
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} elseif { $gpio_to_axis_mux_0 eq "" } {
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catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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return 1
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}
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set_property -dict [ list \
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@@ -385,21 +385,21 @@ proc create_hier_cell_ThresholdRegister { parentCell nameHier } {
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variable script_folder
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if { $parentCell eq "" || $nameHier eq "" } {
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catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_ThresholdRegister() - Empty argument(s)!"}
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catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_ThresholdRegister() - Empty argument(s)!"}
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return
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}
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# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
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catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
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return
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}
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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return
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}
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@@ -475,21 +475,21 @@ proc create_hier_cell_eth_dma_internal { parentCell nameHier } {
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variable script_folder
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if { $parentCell eq "" || $nameHier eq "" } {
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catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_eth_dma_internal() - Empty argument(s)!"}
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catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_eth_dma_internal() - Empty argument(s)!"}
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return
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}
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# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
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catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
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return
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}
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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return
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}
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@@ -577,21 +577,21 @@ proc create_hier_cell_axi_interconnect_common { parentCell nameHier } {
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variable script_folder
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if { $parentCell eq "" || $nameHier eq "" } {
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catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_axi_interconnect_common() - Empty argument(s)!"}
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catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_axi_interconnect_common() - Empty argument(s)!"}
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return
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}
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# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
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catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
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return
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}
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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return
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}
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@@ -666,21 +666,21 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
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variable script_folder
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if { $parentCell eq "" || $nameHier eq "" } {
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catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_rfdc() - Empty argument(s)!"}
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catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_rfdc() - Empty argument(s)!"}
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return
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}
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# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
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catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
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||||
return
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||||
}
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||||
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
|
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if { $parentType ne "hier" } {
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catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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return
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||||
}
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||||
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@@ -800,10 +800,10 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
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set block_name capture_sysref
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set block_cell_name capture_sysref
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if { [catch {set capture_sysref [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
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catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $capture_sysref eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
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||||
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||||
@@ -823,10 +823,10 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
set block_name clock_gates
|
||||
set block_cell_name clock_gates_0
|
||||
if { [catch {set clock_gates_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $clock_gates_0 eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
@@ -941,7 +941,7 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
create_hier_cell_rf_clock_buffers $hier_obj rf_clock_buffers
|
||||
|
||||
# Create instance: rf_data_converter, and set properties
|
||||
set rf_data_converter [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.1 rf_data_converter ]
|
||||
set rf_data_converter [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.5 rf_data_converter ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADC0_Enable {1} \
|
||||
CONFIG.ADC0_Fabric_Freq {184.320} \
|
||||
@@ -1200,10 +1200,10 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
set block_name rf_nco_reset
|
||||
set block_cell_name rf_nco_reset_0
|
||||
if { [catch {set rf_nco_reset_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $rf_nco_reset_0 eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
@@ -1211,10 +1211,10 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
set block_name rf_reset_controller
|
||||
set block_cell_name rf_reset_controller_0
|
||||
if { [catch {set rf_reset_controller_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $rf_reset_controller_0 eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
@@ -1354,21 +1354,21 @@ proc create_hier_cell_ps { parentCell nameHier } {
|
||||
variable script_folder
|
||||
|
||||
if { $parentCell eq "" || $nameHier eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_ps() - Empty argument(s)!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_ps() - Empty argument(s)!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
@@ -1441,6 +1441,11 @@ proc create_hier_cell_ps { parentCell nameHier } {
|
||||
# Create instance: cpld_jtag_engine, and set properties
|
||||
set cpld_jtag_engine [ create_bd_cell -type ip -vlnv ettus.com:ip:axi_bitq:1.0 cpld_jtag_engine ]
|
||||
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.CLK_DOMAIN {x4xx_ps_rfdc_bd_clk40} \
|
||||
] [get_bd_intf_pins /ps/cpld_jtag_engine/S_AXI]
|
||||
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.CLK_DOMAIN {x4xx_ps_rfdc_bd_clk40} \
|
||||
@@ -1951,8 +1956,14 @@ proc create_hier_cell_ps { parentCell nameHier } {
|
||||
CONFIG.PSU_MIO_9_POLARITY {Default} \
|
||||
CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \
|
||||
CONFIG.PSU_MIO_9_SLEW {slow} \
|
||||
CONFIG.PSU_MIO_TREE_PERIPHERALS {GPIO0 MIO#GPIO0 MIO#I2C 0#I2C 0#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#UART 0#UART 0#UART 1#UART 1#PMU GPO 2#PMU GPO 3#I2C 1#I2C 1#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \
|
||||
CONFIG.PSU_MIO_TREE_SIGNALS {gpio0[0]#gpio0[1]#scl_out#sda_out#gpio0[4]#gpio0[5]#sclk_out#n_ss_out[2]#n_ss_out[1]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#sdio0_data_out[4]#sdio0_data_out[5]#sdio0_data_out[6]#sdio0_data_out[7]#sdio0_cmd_out#sdio0_clk_out#sdio0_bus_pow#gpio0[24]#gpio0[25]#gpio1[26]#gpio1[27]#gpio1[28]#gpio1[29]#rxd#txd#txd#rxd#gpo[2]#gpo[3]#scl_out#sda_out#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#gpio1[44]#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out} \
|
||||
CONFIG.PSU_MIO_TREE_PERIPHERALS {GPIO0 MIO#GPIO0 MIO#I2C 0#I2C 0#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#SPI 1#SPI\
|
||||
1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO0\
|
||||
MIO#GPIO0 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#UART 0#UART 0#UART 1#UART\
|
||||
1#PMU GPO 2#PMU GPO 3#I2C 1#I2C 1#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#GPIO1\
|
||||
MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB\
|
||||
0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem\
|
||||
3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3}\
|
||||
CONFIG.PSU_MIO_TREE_SIGNALS {gpio0[0]#gpio0[1]#scl_out#sda_out#gpio0[4]#gpio0[5]#sclk_out#n_ss_out[2]#n_ss_out[1]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#sdio0_data_out[4]#sdio0_data_out[5]#sdio0_data_out[6]#sdio0_data_out[7]#sdio0_cmd_out#sdio0_clk_out#sdio0_bus_pow#gpio0[24]#gpio0[25]#gpio1[26]#gpio1[27]#gpio1[28]#gpio1[29]#rxd#txd#txd#rxd#gpo[2]#gpo[3]#scl_out#sda_out#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#gpio1[44]#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\
|
||||
CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \
|
||||
CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \
|
||||
CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \
|
||||
@@ -2664,6 +2675,7 @@ proc create_hier_cell_ps { parentCell nameHier } {
|
||||
CONFIG.PSU__OCM_BANK1__POWER__ON {1} \
|
||||
CONFIG.PSU__OCM_BANK2__POWER__ON {1} \
|
||||
CONFIG.PSU__OCM_BANK3__POWER__ON {1} \
|
||||
CONFIG.PSU__OVERRIDE_HPX_QOS {0} \
|
||||
CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \
|
||||
CONFIG.PSU__PCIE__ACS_VIOLAION {0} \
|
||||
CONFIG.PSU__PCIE__ACS_VIOLATION {0} \
|
||||
@@ -2771,14 +2783,37 @@ proc create_hier_cell_ps { parentCell nameHier } {
|
||||
CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \
|
||||
CONFIG.PSU__PROTECTION__DEBUG {0} \
|
||||
CONFIG.PSU__PROTECTION__ENABLE {0} \
|
||||
CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000 ;SIZE:1280;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD000000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD010000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD020000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD030000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD040000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD050000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD610000 ;SIZE:512;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD5D0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware} \
|
||||
CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000 ;SIZE:1280;UNIT:KB ;RegionTZ:Secure\
|
||||
;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD000000\
|
||||
;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\
|
||||
Firmware | SA:0xFD010000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\
|
||||
;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD020000\
|
||||
;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\
|
||||
Firmware | SA:0xFD030000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\
|
||||
;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD040000\
|
||||
;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\
|
||||
Firmware | SA:0xFD050000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\
|
||||
;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD610000\
|
||||
;SIZE:512;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\
|
||||
Firmware | SA:0xFD5D0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\
|
||||
;WrAllowed:Read/Write;subsystemId:PMU Firmware}\
|
||||
CONFIG.PSU__PROTECTION__LOCK_UNUSED_SEGMENTS {0} \
|
||||
CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF5E0000 ;SIZE:2560;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFCC0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF180000 ;SIZE:768;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF410000 ;SIZE:640;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFA70000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF9A0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware} \
|
||||
CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;1|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;0|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
|
||||
CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure} \
|
||||
CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\
|
||||
;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF5E0000 ;SIZE:2560;UNIT:KB\
|
||||
;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFCC0000\
|
||||
;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\
|
||||
Firmware|SA:0xFF180000 ;SIZE:768;UNIT:KB ;RegionTZ:Secure\
|
||||
;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF410000 ;SIZE:640;UNIT:KB\
|
||||
;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFA70000\
|
||||
;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\
|
||||
Firmware|SA:0xFF9A0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\
|
||||
;WrAllowed:Read/Write;subsystemId:PMU Firmware}\
|
||||
CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;1|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;0|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\
|
||||
CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure}\
|
||||
CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \
|
||||
CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \
|
||||
CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;0|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;0|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;0|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
|
||||
CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;0|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;0|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\
|
||||
Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\
|
||||
CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU} \
|
||||
CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \
|
||||
CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \
|
||||
@@ -3046,14 +3081,14 @@ proc create_root_design { parentCell } {
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
@@ -3411,18 +3446,16 @@ proc create_root_design { parentCell } {
|
||||
CONFIG.POLARITY {ACTIVE_HIGH} \
|
||||
] $adc_reset_pulse_dclk
|
||||
set adc_rfdc_axi_resetn_rclk [ create_bd_port -dir O adc_rfdc_axi_resetn_rclk ]
|
||||
set bus_clk [ create_bd_port -dir I -type clk bus_clk ]
|
||||
set bus_clk [ create_bd_port -dir I -type clk -freq_hz 200000000 bus_clk ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_BUSIF {m_axis_eth_dma:s_axis_eth_dma:s_axi_hpc1} \
|
||||
CONFIG.ASSOCIATED_RESET {bus_rstn} \
|
||||
CONFIG.FREQ_HZ {200000000} \
|
||||
] $bus_clk
|
||||
set bus_rstn [ create_bd_port -dir I -type rst bus_rstn ]
|
||||
set clk40 [ create_bd_port -dir I -type clk clk40 ]
|
||||
set clk40 [ create_bd_port -dir I -type clk -freq_hz 40000000 clk40 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_BUSIF {m_axi_app:m_axi_mpm_ep:m_axi_core:m_axi_rpu:m_axi_eth_internal} \
|
||||
CONFIG.ASSOCIATED_RESET {clk40_rstn} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
] $clk40
|
||||
set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ]
|
||||
set dac_data_in_resetn_dclk [ create_bd_port -dir O dac_data_in_resetn_dclk ]
|
||||
@@ -3473,10 +3506,7 @@ proc create_root_design { parentCell } {
|
||||
set pl_resetn1 [ create_bd_port -dir O -type rst pl_resetn1 ]
|
||||
set pl_resetn2 [ create_bd_port -dir O -type rst pl_resetn2 ]
|
||||
set pl_resetn3 [ create_bd_port -dir O -type rst pl_resetn3 ]
|
||||
set pll_ref_clk_in [ create_bd_port -dir I -type clk pll_ref_clk_in ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {61440000} \
|
||||
] $pll_ref_clk_in
|
||||
set pll_ref_clk_in [ create_bd_port -dir I -type clk -freq_hz 61440000 pll_ref_clk_in ]
|
||||
set pll_ref_clk_out [ create_bd_port -dir O -type clk pll_ref_clk_out ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {61440000} \
|
||||
@@ -3494,16 +3524,14 @@ proc create_root_design { parentCell } {
|
||||
CONFIG.FREQ_HZ {368640000} \
|
||||
] $rfdc_clk_2x
|
||||
set rfdc_irq [ create_bd_port -dir O -type intr rfdc_irq ]
|
||||
set s_axi_hp0_aclk [ create_bd_port -dir I -type clk s_axi_hp0_aclk ]
|
||||
set s_axi_hp0_aclk [ create_bd_port -dir I -type clk -freq_hz 40000000 s_axi_hp0_aclk ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_BUSIF {s_axi_hp0} \
|
||||
CONFIG.ASSOCIATED_RESET {s_axi_hp0_aresetn} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
] $s_axi_hp0_aclk
|
||||
set s_axi_hp1_aclk [ create_bd_port -dir I -type clk s_axi_hp1_aclk ]
|
||||
set s_axi_hp1_aclk [ create_bd_port -dir I -type clk -freq_hz 40000000 s_axi_hp1_aclk ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_BUSIF {s_axi_hp1} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
] $s_axi_hp1_aclk
|
||||
set s_axi_hpc0_aclk [ create_bd_port -dir I -type clk s_axi_hpc0_aclk ]
|
||||
set_property -dict [ list \
|
||||
@@ -3616,51 +3644,45 @@ proc create_root_design { parentCell } {
|
||||
connect_bd_net -net sysref_pl_in_1 [get_bd_ports sysref_pl_in] [get_bd_pins rfdc/sysref_pl_in]
|
||||
|
||||
# Create address segments
|
||||
create_bd_addr_seg -range 0x00004000 -offset 0x0010000A4000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs ps/eth_dma_internal/axi_eth_dma_internal/S_AXI_LITE/Reg] SEG_axi_eth_dma_internal_Reg
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x001000155000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/ThresholdRegister/axi_gpio_0/S_AXI/Reg] SEG_axi_gpio_0_Reg
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x001000154000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/calibration_muxes/axi_gpio_data/S_AXI/Reg] SEG_axi_gpio_data_Reg
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x001000000000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs ps/cpld_jtag_engine/S_AXI/reg0] SEG_cpld_jtag_engine_reg0
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x001000140000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/data_clock_mmcm/s_axi_lite/Reg] SEG_data_clock_mmcm_Reg
|
||||
create_bd_addr_seg -range 0x000200000000 -offset 0x001200000000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_app/Reg] SEG_m_axi_app_Reg
|
||||
create_bd_addr_seg -range 0x00004000 -offset 0x0010000A0000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_core/Reg] SEG_m_axi_core_0_Reg
|
||||
create_bd_addr_seg -range 0x00004000 -offset 0x0010000A8000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_eth_internal/Reg] SEG_m_axi_eth_internal_Reg
|
||||
create_bd_addr_seg -range 0x00020000 -offset 0x001000080000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_mpm_ep/Reg] SEG_m_axi_mpm_ep_Reg
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x80000000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_rpu/Reg] SEG_m_axi_rpu_Reg
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x001000156000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_clock_gate_control/S_AXI/Reg] SEG_reg_clock_gate_control_Reg
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x001000150000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_invert_iq/S_AXI/Reg] SEG_reg_invert_iq_Reg
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x001000151000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_reset_mmcm/S_AXI/Reg] SEG_reg_reset_mmcm_Reg
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x001000153000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rf_axi_status/S_AXI/Reg] SEG_reg_rf_axi_status_Reg
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x001000152000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rf_reset_control/S_AXI/Reg] SEG_reg_rf_reset_control_Reg
|
||||
create_bd_addr_seg -range 0x00040000 -offset 0x001000100000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/rf_data_converter/s_axi/Reg] SEG_rf_data_converter_Reg
|
||||
create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_SG] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] SEG_inst_zynq_ps_HPC1_DDR_HIGH
|
||||
create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] SEG_inst_zynq_ps_HPC1_DDR_HIGH
|
||||
create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_S2MM] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] SEG_inst_zynq_ps_HPC1_DDR_HIGH
|
||||
create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_SG] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] SEG_inst_zynq_ps_HPC1_DDR_LOW
|
||||
create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] SEG_inst_zynq_ps_HPC1_DDR_LOW
|
||||
create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_S2MM] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] SEG_inst_zynq_ps_HPC1_DDR_LOW
|
||||
create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces s_axi_hp0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP2/HP0_DDR_HIGH] SEG_inst_zynq_ps_HP0_DDR_HIGH
|
||||
create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP2/HP0_DDR_LOW] SEG_inst_zynq_ps_HP0_DDR_LOW
|
||||
create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces s_axi_hp0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP2/HP0_LPS_OCM] SEG_inst_zynq_ps_HP0_LPS_OCM
|
||||
create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces s_axi_hp1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP3/HP1_DDR_HIGH] SEG_inst_zynq_ps_HP1_DDR_HIGH
|
||||
create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP3/HP1_DDR_LOW] SEG_inst_zynq_ps_HP1_DDR_LOW
|
||||
create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces s_axi_hp1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP3/HP1_LPS_OCM] SEG_inst_zynq_ps_HP1_LPS_OCM
|
||||
create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces s_axi_hpc0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP0/HPC0_DDR_HIGH] SEG_inst_zynq_ps_HPC0_DDR_HIGH
|
||||
create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hpc0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP0/HPC0_DDR_LOW] SEG_inst_zynq_ps_HPC0_DDR_LOW
|
||||
create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces s_axi_hpc0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP0/HPC0_LPS_OCM] SEG_inst_zynq_ps_HPC0_LPS_OCM
|
||||
create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces s_axi_hpc1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] SEG_inst_zynq_ps_HPC1_DDR_HIGH
|
||||
create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hpc1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] SEG_inst_zynq_ps_HPC1_DDR_LOW
|
||||
create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces s_axi_hpc1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM] SEG_inst_zynq_ps_HPC1_LPS_OCM
|
||||
assign_bd_address -offset 0x0010000A4000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs ps/eth_dma_internal/axi_eth_dma_internal/S_AXI_LITE/Reg] -force
|
||||
assign_bd_address -offset 0x001000155000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/ThresholdRegister/axi_gpio_0/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x001000154000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/calibration_muxes/axi_gpio_data/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x001000000000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs ps/cpld_jtag_engine/S_AXI/reg0] -force
|
||||
assign_bd_address -offset 0x001000140000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/data_clock_mmcm/s_axi_lite/Reg] -force
|
||||
assign_bd_address -offset 0x001200000000 -range 0x000200000000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_app/Reg] -force
|
||||
assign_bd_address -offset 0x0010000A0000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_core/Reg] -force
|
||||
assign_bd_address -offset 0x0010000A8000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_eth_internal/Reg] -force
|
||||
assign_bd_address -offset 0x001000080000 -range 0x00020000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_mpm_ep/Reg] -force
|
||||
assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_rpu/Reg] -force
|
||||
assign_bd_address -offset 0x001000156000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_clock_gate_control/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x001000150000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_invert_iq/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x001000151000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_reset_mmcm/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x001000153000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rf_axi_status/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x001000152000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rf_reset_control/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x001000100000 -range 0x00040000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/rf_data_converter/s_axi/Reg] -force
|
||||
assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_SG] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] -force
|
||||
assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] -force
|
||||
assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_S2MM] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_SG] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_S2MM] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] -force
|
||||
assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces s_axi_hp0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP2/HP0_DDR_HIGH] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces s_axi_hp0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP2/HP0_DDR_LOW] -force
|
||||
assign_bd_address -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces s_axi_hp0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP2/HP0_LPS_OCM] -force
|
||||
assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces s_axi_hp1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP3/HP1_DDR_HIGH] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces s_axi_hp1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP3/HP1_DDR_LOW] -force
|
||||
assign_bd_address -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces s_axi_hp1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP3/HP1_LPS_OCM] -force
|
||||
assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces s_axi_hpc0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP0/HPC0_DDR_HIGH] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces s_axi_hpc0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP0/HPC0_DDR_LOW] -force
|
||||
assign_bd_address -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces s_axi_hpc0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP0/HPC0_LPS_OCM] -force
|
||||
assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces s_axi_hpc1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces s_axi_hpc1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] -force
|
||||
assign_bd_address -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces s_axi_hpc1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM] -force
|
||||
|
||||
# Exclude Address Segments
|
||||
create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM] SEG_inst_zynq_ps_HPC1_LPS_OCM
|
||||
exclude_bd_addr_seg [get_bd_addr_segs ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S/SEG_inst_zynq_ps_HPC1_LPS_OCM]
|
||||
|
||||
create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_S2MM] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM] SEG_inst_zynq_ps_HPC1_LPS_OCM
|
||||
exclude_bd_addr_seg [get_bd_addr_segs ps/eth_dma_internal/axi_eth_dma_internal/Data_S2MM/SEG_inst_zynq_ps_HPC1_LPS_OCM]
|
||||
|
||||
create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_SG] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM] SEG_inst_zynq_ps_HPC1_LPS_OCM
|
||||
exclude_bd_addr_seg [get_bd_addr_segs ps/eth_dma_internal/axi_eth_dma_internal/Data_SG/SEG_inst_zynq_ps_HPC1_LPS_OCM]
|
||||
|
||||
exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM]
|
||||
exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_S2MM] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM]
|
||||
exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_SG] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM]
|
||||
|
||||
|
||||
# Restore current instance
|
||||
|
||||
Reference in New Issue
Block a user