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fpga: x400: Upgrade to Vivado 2021.1

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Commit includes:
- Upgrade x400-specific IP
- Removal of xge_pcs_pma IP patch


Original-commit: e94deac2efb8c3167eb2d70a385a8fa0ad657b55
This commit is contained in:
Sam O'Brien
2022-08-25 13:55:30 -05:00
committed by skooNI
parent 6193c765fe
commit 1b952d33df
27 changed files with 1156 additions and 692 deletions
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top/x400/ip/eth_100g_bd/lbus_tb/Makefile
+3 -3
View File
@@ -35,7 +35,7 @@ $(AXI4S_SV_SRCS) \
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm fifo_generator_v13_2_4
MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm fifo_generator_v13_2_5
MODELSIM_ARGS += glbl -t 1fs
# Define toplevel module
TB_TOP_MODULE ?= lbus_all_tb
@@ -50,8 +50,8 @@ $(VIVADO_PATH)/data/verilog/src/glbl.v \
# Suppressing the following worthless reminder.
#* Warning: M:/usrp4-hw/oss-repo/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv(228): (vlog-2583) [SVCHK] -
# Extra checking for conflicts with always_comb and always_latch variables is done at vopt time
SVLOG_ARGS = -suppress 2583 -keep_delta
VLOG_ARGS = -keep_delta
SVLOG_ARGS = -suppress 2583 -keep_delta
VLOG_ARGS = -keep_delta
#-------------------------------------------------
# Bottom-of-Makefile