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fpga: x400: Upgrade to Vivado 2021.1

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Commit includes:
- Upgrade x400-specific IP
- Removal of xge_pcs_pma IP patch


Original-commit: e94deac2efb8c3167eb2d70a385a8fa0ad657b55
This commit is contained in:
Sam O'Brien
2022-08-25 13:55:30 -05:00
committed by skooNI
parent 6193c765fe
commit 1b952d33df
27 changed files with 1156 additions and 692 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/x400/ip/eth_100g_bd/Makefile.inc
+1 -1
View File
@@ -21,7 +21,7 @@ sim/eth_100g_bd.v\
ip/*/ip_0/sim/*.v\
ip/*/sim/*.h\
ip/*/sim/*.v\
ip/eth_100g_bd_cmac_usplus_0_0/cmac_usplus_v2_6_1/*.v\
ip/eth_100g_bd_cmac_usplus_0_0/cmac_usplus_v3_1_4/*.v\
ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0/example_design/*.v\
ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0/header_files/*.h\
ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0.v\
top/x400/ip/eth_100g_bd/eth_100g.sv
+6 -16
View File
@@ -80,6 +80,7 @@ module eth_100g #(
end
end
// synthesis translate_off
//extra simulation checks
localparam USE_MAC_CHECKS = 1;
if (USE_MAC_CHECKS) begin
@@ -124,6 +125,7 @@ module eth_100g #(
assert (mgt_rx.TLAST == 1) else
$fatal(1, "mgt_rx.TLAST must be enabled");
end
// synthesis translate_on
AxiStreamIf #(.DATA_WIDTH(512),.TUSER(0),.TKEEP(0))
eth100g_tx(mgt_clk,mgt_rst);
@@ -1130,23 +1132,11 @@ module eth_100g #(
eth_100g_bd eth_100g_bd_i (
.refclk_clk_n(refclk_n),
.refclk_clk_p(refclk_p),
.gt_rx_gt_port_0_n(rx_n[0]),
.gt_rx_gt_port_0_p(rx_p[0]),
.gt_rx_gt_port_1_n(rx_n[1]),
.gt_rx_gt_port_1_p(rx_p[1]),
.gt_rx_gt_port_2_n(rx_n[2]),
.gt_rx_gt_port_2_p(rx_p[2]),
.gt_rx_gt_port_3_n(rx_n[3]),
.gt_rx_gt_port_3_p(rx_p[3]),
.gt_serial_port_0_grx_n(rx_n),
.gt_serial_port_0_grx_p(rx_p),
.gt_serial_port_0_gtx_n(tx_n),
.gt_serial_port_0_gtx_p(tx_p),
.init_clk(clk100),
.gt_tx_gt_port_0_n(tx_n[0]),
.gt_tx_gt_port_0_p(tx_p[0]),
.gt_tx_gt_port_1_n(tx_n[1]),
.gt_tx_gt_port_1_p(tx_p[1]),
.gt_tx_gt_port_2_n(tx_n[2]),
.gt_tx_gt_port_2_p(tx_p[2]),
.gt_tx_gt_port_3_n(tx_n[3]),
.gt_tx_gt_port_3_p(tx_p[3]),
.sys_reset(areset),
.usr_rx_reset(usr_rx_reset),
.usr_tx_reset(usr_tx_reset),
top/x400/ip/eth_100g_bd/eth_100g_bd.tcl
+20 -26
View File
@@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2019.1
set scripts_vivado_version 2021.1
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
@@ -76,10 +76,10 @@ if { ${design_name} eq "" } {
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
if { $cur_design ne $design_name } {
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
@@ -100,19 +100,19 @@ if { ${design_name} eq "" } {
# 8) No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name
}
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
if { $nRet != 0 } {
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
return $nRet
}
@@ -123,12 +123,12 @@ set bCheckIPsPassed 1
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:cmac_usplus:2.6\
xilinx.com:ip:cmac_usplus:3.1\
xilinx.com:ip:xlconstant:1.1\
"
set list_ips_missing ""
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
@@ -138,14 +138,14 @@ xilinx.com:ip:xlconstant:1.1\
}
if { $list_ips_missing ne "" } {
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
@@ -169,14 +169,14 @@ proc create_root_design { parentCell } {
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
@@ -194,9 +194,7 @@ proc create_root_design { parentCell } {
set eth100g_tx [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_cmac_usplus:lbus_ports:2.0 eth100g_tx ]
set gt_rx [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_cmac_usplus:gt_ports:2.0 gt_rx ]
set gt_tx [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_cmac_usplus:gt_ports:2.0 gt_tx ]
set gt_serial_port_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 gt_serial_port_0 ]
set refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 refclk ]
set_property -dict [ list \
@@ -246,10 +244,7 @@ proc create_root_design { parentCell } {
] $gt_txusrclk2
set init_clk [ create_bd_port -dir I -type clk init_clk ]
set pm_tick [ create_bd_port -dir I pm_tick ]
set rx_clk [ create_bd_port -dir I -type clk rx_clk ]
set_property -dict [ list \
CONFIG.FREQ_HZ {322265625} \
] $rx_clk
set rx_clk [ create_bd_port -dir I -type clk -freq_hz 322265625 rx_clk ]
set s_axi_aclk [ create_bd_port -dir I -type clk s_axi_aclk ]
set s_axi_sreset [ create_bd_port -dir I -type rst s_axi_sreset ]
set_property -dict [ list \
@@ -267,7 +262,7 @@ proc create_root_design { parentCell } {
set usr_tx_reset [ create_bd_port -dir O -type rst usr_tx_reset ]
# Create instance: cmac_usplus_0, and set properties
set cmac_usplus_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cmac_usplus:2.6 cmac_usplus_0 ]
set cmac_usplus_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cmac_usplus:3.1 cmac_usplus_0 ]
set_property -dict [ list \
CONFIG.CMAC_CAUI4_MODE {1} \
CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y0} \
@@ -289,7 +284,7 @@ proc create_root_design { parentCell } {
CONFIG.LANE7_GT_LOC {NA} \
CONFIG.LANE8_GT_LOC {NA} \
CONFIG.LANE9_GT_LOC {NA} \
CONFIG.NUM_LANES {4} \
CONFIG.NUM_LANES {4x25} \
CONFIG.RX_CHECK_ACK {0} \
CONFIG.RX_EQ_MODE {AUTO} \
CONFIG.RX_FLOW_CONTROL {1} \
@@ -312,8 +307,7 @@ proc create_root_design { parentCell } {
# Create interface connections
connect_bd_intf_net -intf_net RefClk_1 [get_bd_intf_ports refclk] [get_bd_intf_pins cmac_usplus_0/gt_ref_clk]
connect_bd_intf_net -intf_net Rx_1 [get_bd_intf_ports gt_rx] [get_bd_intf_pins cmac_usplus_0/gt_rx]
connect_bd_intf_net -intf_net cmac_usplus_0_gt_tx [get_bd_intf_ports gt_tx] [get_bd_intf_pins cmac_usplus_0/gt_tx]
connect_bd_intf_net -intf_net cmac_usplus_0_gt_serial_port [get_bd_intf_ports gt_serial_port_0] [get_bd_intf_pins cmac_usplus_0/gt_serial_port]
connect_bd_intf_net -intf_net cmac_usplus_0_lbus_rx [get_bd_intf_ports eth100g_rx] [get_bd_intf_pins cmac_usplus_0/lbus_rx]
connect_bd_intf_net -intf_net eth_100g_tx_1 [get_bd_intf_ports eth100g_tx] [get_bd_intf_pins cmac_usplus_0/lbus_tx]
connect_bd_intf_net -intf_net sDrp_1 [get_bd_intf_ports core_drp] [get_bd_intf_pins cmac_usplus_0/core_drp]
@@ -340,7 +334,7 @@ proc create_root_design { parentCell } {
connect_bd_net -net tie_zero_dout [get_bd_pins cmac_usplus_0/gtwiz_reset_rx_datapath] [get_bd_pins cmac_usplus_0/gtwiz_reset_tx_datapath] [get_bd_pins tie_zero/dout]
# Create address segments
create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces s_axi] [get_bd_addr_segs cmac_usplus_0/s_axi/Reg] SEG_cmac_usplus_0_Reg
assign_bd_address -offset 0x00000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces s_axi] [get_bd_addr_segs cmac_usplus_0/s_axi/Reg] -force
# Restore current instance
top/x400/ip/eth_100g_bd/lbus_tb/Makefile
+3 -3
View File
@@ -35,7 +35,7 @@ $(AXI4S_SV_SRCS) \
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm fifo_generator_v13_2_4
MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm fifo_generator_v13_2_5
MODELSIM_ARGS += glbl -t 1fs
# Define toplevel module
TB_TOP_MODULE ?= lbus_all_tb
@@ -50,8 +50,8 @@ $(VIVADO_PATH)/data/verilog/src/glbl.v \
# Suppressing the following worthless reminder.
#* Warning: M:/usrp4-hw/oss-repo/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv(228): (vlog-2583) [SVCHK] -
# Extra checking for conflicts with always_comb and always_latch variables is done at vopt time
SVLOG_ARGS = -suppress 2583 -keep_delta
VLOG_ARGS = -keep_delta
SVLOG_ARGS = -suppress 2583 -keep_delta
VLOG_ARGS = -keep_delta
#-------------------------------------------------
# Bottom-of-Makefile